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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ |
2 | */ |
3 | /* |
3 | /* |
4 | * |
4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. |
6 | * All Rights Reserved. |
7 | * |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the |
9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including |
10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: |
14 | * the following conditions: |
15 | * |
15 | * |
16 | * The above copyright notice and this permission notice (including the |
16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions |
17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. |
18 | * of the Software. |
19 | * |
19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
27 | * |
28 | */ |
28 | */ |
29 | 29 | ||
30 | #ifndef _I915_DRV_H_ |
30 | #ifndef _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
31 | #define _I915_DRV_H_ |
32 | 32 | ||
33 | #include |
33 | #include |
34 | #include |
34 | #include |
- | 35 | ||
35 | 36 | #include |
|
36 | #include "i915_reg.h" |
37 | #include "i915_reg.h" |
37 | #include "intel_bios.h" |
38 | #include "intel_bios.h" |
38 | #include "intel_ringbuffer.h" |
39 | #include "intel_ringbuffer.h" |
39 | #include "intel_lrc.h" |
40 | #include "intel_lrc.h" |
40 | #include "i915_gem_gtt.h" |
41 | #include "i915_gem_gtt.h" |
41 | #include "i915_gem_render_state.h" |
42 | #include "i915_gem_render_state.h" |
42 | #include |
43 | #include |
43 | #include |
44 | #include |
44 | #include |
45 | #include |
45 | #include |
46 | #include |
46 | #include |
47 | #include |
47 | #include |
48 | #include |
48 | //#include |
49 | #include |
49 | #include |
50 | #include |
50 | #include |
51 | #include |
51 | #include "intel_guc.h" |
52 | #include "intel_guc.h" |
52 | 53 | ||
53 | #include |
54 | #include |
54 | - | ||
55 | #define ioread32(addr) readl(addr) |
- | |
56 | static inline u8 inb(u16 port) |
- | |
57 | { |
- | |
58 | u8 v; |
- | |
59 | asm volatile("inb %1,%0" : "=a" (v) : "dN" (port)); |
- | |
60 | return v; |
- | |
61 | } |
- | |
62 | - | ||
63 | static inline void outb(u8 v, u16 port) |
- | |
64 | { |
- | |
65 | asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); |
- | |
66 | } |
- | |
67 | - | ||
68 | 55 | ||
69 | /* General customization: |
56 | /* General customization: |
70 | */ |
57 | */ |
71 | 58 | ||
72 | #define DRIVER_NAME "i915" |
59 | #define DRIVER_NAME "i915" |
73 | #define DRIVER_DESC "Intel Graphics" |
60 | #define DRIVER_DESC "Intel Graphics" |
74 | #define DRIVER_DATE "20151010" |
61 | #define DRIVER_DATE "20151218" |
75 | 62 | ||
76 | #undef WARN_ON |
63 | #undef WARN_ON |
77 | /* Many gcc seem to no see through this and fall over :( */ |
64 | /* Many gcc seem to no see through this and fall over :( */ |
78 | #if 0 |
65 | #if 0 |
79 | #define WARN_ON(x) ({ \ |
66 | #define WARN_ON(x) ({ \ |
80 | bool __i915_warn_cond = (x); \ |
67 | bool __i915_warn_cond = (x); \ |
81 | if (__builtin_constant_p(__i915_warn_cond)) \ |
68 | if (__builtin_constant_p(__i915_warn_cond)) \ |
82 | BUILD_BUG_ON(__i915_warn_cond); \ |
69 | BUILD_BUG_ON(__i915_warn_cond); \ |
83 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) |
70 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) |
84 | #else |
71 | #else |
85 | #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x ) |
72 | #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x ) |
86 | #endif |
73 | #endif |
87 | 74 | ||
88 | #undef WARN_ON_ONCE |
75 | #undef WARN_ON_ONCE |
89 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x ) |
76 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x ) |
90 | 77 | ||
91 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
78 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
92 | (long) (x), __func__); |
79 | (long) (x), __func__); |
93 | 80 | ||
94 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
81 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
95 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions |
82 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions |
96 | * which may not necessarily be a user visible problem. This will either |
83 | * which may not necessarily be a user visible problem. This will either |
97 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to |
84 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to |
98 | * enable distros and users to tailor their preferred amount of i915 abrt |
85 | * enable distros and users to tailor their preferred amount of i915 abrt |
99 | * spam. |
86 | * spam. |
100 | */ |
87 | */ |
101 | #define I915_STATE_WARN(condition, format...) ({ \ |
88 | #define I915_STATE_WARN(condition, format...) ({ \ |
102 | int __ret_warn_on = !!(condition); \ |
89 | int __ret_warn_on = !!(condition); \ |
103 | if (unlikely(__ret_warn_on)) { \ |
90 | if (unlikely(__ret_warn_on)) { \ |
104 | if (i915.verbose_state_checks) \ |
91 | if (i915.verbose_state_checks) \ |
105 | WARN(1, format); \ |
92 | WARN(1, format); \ |
106 | else \ |
93 | else \ |
107 | DRM_ERROR(format); \ |
94 | DRM_ERROR(format); \ |
108 | } \ |
95 | } \ |
109 | unlikely(__ret_warn_on); \ |
96 | unlikely(__ret_warn_on); \ |
110 | }) |
97 | }) |
111 | 98 | ||
112 | #define I915_STATE_WARN_ON(condition) ({ \ |
99 | #define I915_STATE_WARN_ON(condition) ({ \ |
113 | int __ret_warn_on = !!(condition); \ |
100 | int __ret_warn_on = !!(condition); \ |
114 | if (unlikely(__ret_warn_on)) { \ |
101 | if (unlikely(__ret_warn_on)) { \ |
115 | if (i915.verbose_state_checks) \ |
102 | if (i915.verbose_state_checks) \ |
116 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
103 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
117 | else \ |
104 | else \ |
118 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ |
105 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ |
119 | } \ |
106 | } \ |
120 | unlikely(__ret_warn_on); \ |
107 | unlikely(__ret_warn_on); \ |
121 | }) |
108 | }) |
122 | 109 | ||
123 | static inline const char *yesno(bool v) |
110 | static inline const char *yesno(bool v) |
124 | { |
111 | { |
125 | return v ? "yes" : "no"; |
112 | return v ? "yes" : "no"; |
126 | } |
113 | } |
127 | 114 | ||
128 | enum pipe { |
115 | enum pipe { |
129 | INVALID_PIPE = -1, |
116 | INVALID_PIPE = -1, |
130 | PIPE_A = 0, |
117 | PIPE_A = 0, |
131 | PIPE_B, |
118 | PIPE_B, |
132 | PIPE_C, |
119 | PIPE_C, |
133 | _PIPE_EDP, |
120 | _PIPE_EDP, |
134 | I915_MAX_PIPES = _PIPE_EDP |
121 | I915_MAX_PIPES = _PIPE_EDP |
135 | }; |
122 | }; |
136 | #define pipe_name(p) ((p) + 'A') |
123 | #define pipe_name(p) ((p) + 'A') |
137 | 124 | ||
138 | enum transcoder { |
125 | enum transcoder { |
139 | TRANSCODER_A = 0, |
126 | TRANSCODER_A = 0, |
140 | TRANSCODER_B, |
127 | TRANSCODER_B, |
141 | TRANSCODER_C, |
128 | TRANSCODER_C, |
142 | TRANSCODER_EDP, |
129 | TRANSCODER_EDP, |
143 | I915_MAX_TRANSCODERS |
130 | I915_MAX_TRANSCODERS |
144 | }; |
131 | }; |
145 | #define transcoder_name(t) ((t) + 'A') |
132 | #define transcoder_name(t) ((t) + 'A') |
146 | 133 | ||
147 | /* |
134 | /* |
148 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
135 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
149 | * number of planes per CRTC. Not all platforms really have this many planes, |
136 | * number of planes per CRTC. Not all platforms really have this many planes, |
150 | * which means some arrays of size I915_MAX_PLANES may have unused entries |
137 | * which means some arrays of size I915_MAX_PLANES may have unused entries |
151 | * between the topmost sprite plane and the cursor plane. |
138 | * between the topmost sprite plane and the cursor plane. |
152 | */ |
139 | */ |
153 | enum plane { |
140 | enum plane { |
154 | PLANE_A = 0, |
141 | PLANE_A = 0, |
155 | PLANE_B, |
142 | PLANE_B, |
156 | PLANE_C, |
143 | PLANE_C, |
157 | PLANE_CURSOR, |
144 | PLANE_CURSOR, |
158 | I915_MAX_PLANES, |
145 | I915_MAX_PLANES, |
159 | }; |
146 | }; |
160 | #define plane_name(p) ((p) + 'A') |
147 | #define plane_name(p) ((p) + 'A') |
161 | 148 | ||
162 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
149 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
163 | 150 | ||
164 | enum port { |
151 | enum port { |
165 | PORT_A = 0, |
152 | PORT_A = 0, |
166 | PORT_B, |
153 | PORT_B, |
167 | PORT_C, |
154 | PORT_C, |
168 | PORT_D, |
155 | PORT_D, |
169 | PORT_E, |
156 | PORT_E, |
170 | I915_MAX_PORTS |
157 | I915_MAX_PORTS |
171 | }; |
158 | }; |
172 | #define port_name(p) ((p) + 'A') |
159 | #define port_name(p) ((p) + 'A') |
173 | 160 | ||
174 | #define I915_NUM_PHYS_VLV 2 |
161 | #define I915_NUM_PHYS_VLV 2 |
175 | 162 | ||
176 | enum dpio_channel { |
163 | enum dpio_channel { |
177 | DPIO_CH0, |
164 | DPIO_CH0, |
178 | DPIO_CH1 |
165 | DPIO_CH1 |
179 | }; |
166 | }; |
180 | 167 | ||
181 | enum dpio_phy { |
168 | enum dpio_phy { |
182 | DPIO_PHY0, |
169 | DPIO_PHY0, |
183 | DPIO_PHY1 |
170 | DPIO_PHY1 |
184 | }; |
171 | }; |
185 | 172 | ||
186 | enum intel_display_power_domain { |
173 | enum intel_display_power_domain { |
187 | POWER_DOMAIN_PIPE_A, |
174 | POWER_DOMAIN_PIPE_A, |
188 | POWER_DOMAIN_PIPE_B, |
175 | POWER_DOMAIN_PIPE_B, |
189 | POWER_DOMAIN_PIPE_C, |
176 | POWER_DOMAIN_PIPE_C, |
190 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
177 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
191 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
178 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
192 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
179 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
193 | POWER_DOMAIN_TRANSCODER_A, |
180 | POWER_DOMAIN_TRANSCODER_A, |
194 | POWER_DOMAIN_TRANSCODER_B, |
181 | POWER_DOMAIN_TRANSCODER_B, |
195 | POWER_DOMAIN_TRANSCODER_C, |
182 | POWER_DOMAIN_TRANSCODER_C, |
196 | POWER_DOMAIN_TRANSCODER_EDP, |
183 | POWER_DOMAIN_TRANSCODER_EDP, |
197 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
- | |
198 | POWER_DOMAIN_PORT_DDI_A_4_LANES, |
184 | POWER_DOMAIN_PORT_DDI_A_LANES, |
199 | POWER_DOMAIN_PORT_DDI_B_2_LANES, |
- | |
200 | POWER_DOMAIN_PORT_DDI_B_4_LANES, |
185 | POWER_DOMAIN_PORT_DDI_B_LANES, |
201 | POWER_DOMAIN_PORT_DDI_C_2_LANES, |
- | |
202 | POWER_DOMAIN_PORT_DDI_C_4_LANES, |
186 | POWER_DOMAIN_PORT_DDI_C_LANES, |
203 | POWER_DOMAIN_PORT_DDI_D_2_LANES, |
- | |
204 | POWER_DOMAIN_PORT_DDI_D_4_LANES, |
187 | POWER_DOMAIN_PORT_DDI_D_LANES, |
205 | POWER_DOMAIN_PORT_DDI_E_2_LANES, |
188 | POWER_DOMAIN_PORT_DDI_E_LANES, |
206 | POWER_DOMAIN_PORT_DSI, |
189 | POWER_DOMAIN_PORT_DSI, |
207 | POWER_DOMAIN_PORT_CRT, |
190 | POWER_DOMAIN_PORT_CRT, |
208 | POWER_DOMAIN_PORT_OTHER, |
191 | POWER_DOMAIN_PORT_OTHER, |
209 | POWER_DOMAIN_VGA, |
192 | POWER_DOMAIN_VGA, |
210 | POWER_DOMAIN_AUDIO, |
193 | POWER_DOMAIN_AUDIO, |
211 | POWER_DOMAIN_PLLS, |
194 | POWER_DOMAIN_PLLS, |
212 | POWER_DOMAIN_AUX_A, |
195 | POWER_DOMAIN_AUX_A, |
213 | POWER_DOMAIN_AUX_B, |
196 | POWER_DOMAIN_AUX_B, |
214 | POWER_DOMAIN_AUX_C, |
197 | POWER_DOMAIN_AUX_C, |
215 | POWER_DOMAIN_AUX_D, |
198 | POWER_DOMAIN_AUX_D, |
216 | POWER_DOMAIN_GMBUS, |
199 | POWER_DOMAIN_GMBUS, |
- | 200 | POWER_DOMAIN_MODESET, |
|
217 | POWER_DOMAIN_INIT, |
201 | POWER_DOMAIN_INIT, |
218 | 202 | ||
219 | POWER_DOMAIN_NUM, |
203 | POWER_DOMAIN_NUM, |
220 | }; |
204 | }; |
221 | 205 | ||
222 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
206 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
223 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
207 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
224 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
208 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
225 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
209 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
226 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
210 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
227 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
211 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
228 | 212 | ||
229 | enum hpd_pin { |
213 | enum hpd_pin { |
230 | HPD_NONE = 0, |
214 | HPD_NONE = 0, |
231 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
215 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
232 | HPD_CRT, |
216 | HPD_CRT, |
233 | HPD_SDVO_B, |
217 | HPD_SDVO_B, |
234 | HPD_SDVO_C, |
218 | HPD_SDVO_C, |
235 | HPD_PORT_A, |
219 | HPD_PORT_A, |
236 | HPD_PORT_B, |
220 | HPD_PORT_B, |
237 | HPD_PORT_C, |
221 | HPD_PORT_C, |
238 | HPD_PORT_D, |
222 | HPD_PORT_D, |
239 | HPD_PORT_E, |
223 | HPD_PORT_E, |
240 | HPD_NUM_PINS |
224 | HPD_NUM_PINS |
241 | }; |
225 | }; |
242 | 226 | ||
243 | #define for_each_hpd_pin(__pin) \ |
227 | #define for_each_hpd_pin(__pin) \ |
244 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) |
228 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) |
245 | 229 | ||
246 | struct i915_hotplug { |
230 | struct i915_hotplug { |
247 | struct work_struct hotplug_work; |
231 | struct work_struct hotplug_work; |
248 | 232 | ||
249 | struct { |
233 | struct { |
250 | unsigned long last_jiffies; |
234 | unsigned long last_jiffies; |
251 | int count; |
235 | int count; |
252 | enum { |
236 | enum { |
253 | HPD_ENABLED = 0, |
237 | HPD_ENABLED = 0, |
254 | HPD_DISABLED = 1, |
238 | HPD_DISABLED = 1, |
255 | HPD_MARK_DISABLED = 2 |
239 | HPD_MARK_DISABLED = 2 |
256 | } state; |
240 | } state; |
257 | } stats[HPD_NUM_PINS]; |
241 | } stats[HPD_NUM_PINS]; |
258 | u32 event_bits; |
242 | u32 event_bits; |
259 | struct delayed_work reenable_work; |
243 | struct delayed_work reenable_work; |
260 | 244 | ||
261 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; |
245 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; |
262 | u32 long_port_mask; |
246 | u32 long_port_mask; |
263 | u32 short_port_mask; |
247 | u32 short_port_mask; |
264 | struct work_struct dig_port_work; |
248 | struct work_struct dig_port_work; |
265 | 249 | ||
266 | /* |
250 | /* |
267 | * if we get a HPD irq from DP and a HPD irq from non-DP |
251 | * if we get a HPD irq from DP and a HPD irq from non-DP |
268 | * the non-DP HPD could block the workqueue on a mode config |
252 | * the non-DP HPD could block the workqueue on a mode config |
269 | * mutex getting, that userspace may have taken. However |
253 | * mutex getting, that userspace may have taken. However |
270 | * userspace is waiting on the DP workqueue to run which is |
254 | * userspace is waiting on the DP workqueue to run which is |
271 | * blocked behind the non-DP one. |
255 | * blocked behind the non-DP one. |
272 | */ |
256 | */ |
273 | struct workqueue_struct *dp_wq; |
257 | struct workqueue_struct *dp_wq; |
274 | }; |
258 | }; |
275 | 259 | ||
276 | #define I915_GEM_GPU_DOMAINS \ |
260 | #define I915_GEM_GPU_DOMAINS \ |
277 | (I915_GEM_DOMAIN_RENDER | \ |
261 | (I915_GEM_DOMAIN_RENDER | \ |
278 | I915_GEM_DOMAIN_SAMPLER | \ |
262 | I915_GEM_DOMAIN_SAMPLER | \ |
279 | I915_GEM_DOMAIN_COMMAND | \ |
263 | I915_GEM_DOMAIN_COMMAND | \ |
280 | I915_GEM_DOMAIN_INSTRUCTION | \ |
264 | I915_GEM_DOMAIN_INSTRUCTION | \ |
281 | I915_GEM_DOMAIN_VERTEX) |
265 | I915_GEM_DOMAIN_VERTEX) |
282 | 266 | ||
283 | #define for_each_pipe(__dev_priv, __p) \ |
267 | #define for_each_pipe(__dev_priv, __p) \ |
284 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) |
268 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) |
285 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
269 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
286 | for ((__p) = 0; \ |
270 | for ((__p) = 0; \ |
287 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ |
271 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ |
288 | (__p)++) |
272 | (__p)++) |
289 | #define for_each_sprite(__dev_priv, __p, __s) \ |
273 | #define for_each_sprite(__dev_priv, __p, __s) \ |
290 | for ((__s) = 0; \ |
274 | for ((__s) = 0; \ |
291 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ |
275 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ |
292 | (__s)++) |
276 | (__s)++) |
293 | 277 | ||
294 | #define for_each_crtc(dev, crtc) \ |
278 | #define for_each_crtc(dev, crtc) \ |
295 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
279 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
296 | 280 | ||
297 | #define for_each_intel_plane(dev, intel_plane) \ |
281 | #define for_each_intel_plane(dev, intel_plane) \ |
298 | list_for_each_entry(intel_plane, \ |
282 | list_for_each_entry(intel_plane, \ |
299 | &dev->mode_config.plane_list, \ |
283 | &dev->mode_config.plane_list, \ |
300 | base.head) |
284 | base.head) |
301 | 285 | ||
302 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
286 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
303 | list_for_each_entry(intel_plane, \ |
287 | list_for_each_entry(intel_plane, \ |
304 | &(dev)->mode_config.plane_list, \ |
288 | &(dev)->mode_config.plane_list, \ |
305 | base.head) \ |
289 | base.head) \ |
306 | if ((intel_plane)->pipe == (intel_crtc)->pipe) |
290 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
307 | 291 | ||
308 | #define for_each_intel_crtc(dev, intel_crtc) \ |
292 | #define for_each_intel_crtc(dev, intel_crtc) \ |
309 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) |
293 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) |
310 | 294 | ||
311 | #define for_each_intel_encoder(dev, intel_encoder) \ |
295 | #define for_each_intel_encoder(dev, intel_encoder) \ |
312 | list_for_each_entry(intel_encoder, \ |
296 | list_for_each_entry(intel_encoder, \ |
313 | &(dev)->mode_config.encoder_list, \ |
297 | &(dev)->mode_config.encoder_list, \ |
314 | base.head) |
298 | base.head) |
315 | 299 | ||
316 | #define for_each_intel_connector(dev, intel_connector) \ |
300 | #define for_each_intel_connector(dev, intel_connector) \ |
317 | list_for_each_entry(intel_connector, \ |
301 | list_for_each_entry(intel_connector, \ |
318 | &dev->mode_config.connector_list, \ |
302 | &dev->mode_config.connector_list, \ |
319 | base.head) |
303 | base.head) |
320 | 304 | ||
321 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
305 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
322 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
306 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
323 | if ((intel_encoder)->base.crtc == (__crtc)) |
307 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
324 | 308 | ||
325 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
309 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
326 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
310 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
327 | if ((intel_connector)->base.encoder == (__encoder)) |
311 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
328 | 312 | ||
329 | #define for_each_power_domain(domain, mask) \ |
313 | #define for_each_power_domain(domain, mask) \ |
330 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
314 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
331 | if ((1 << (domain)) & (mask)) |
315 | for_each_if ((1 << (domain)) & (mask)) |
332 | 316 | ||
333 | struct drm_i915_private; |
317 | struct drm_i915_private; |
334 | struct i915_mm_struct; |
318 | struct i915_mm_struct; |
335 | struct i915_mmu_object; |
319 | struct i915_mmu_object; |
336 | 320 | ||
337 | struct drm_i915_file_private { |
321 | struct drm_i915_file_private { |
338 | struct drm_i915_private *dev_priv; |
322 | struct drm_i915_private *dev_priv; |
339 | struct drm_file *file; |
323 | struct drm_file *file; |
340 | 324 | ||
341 | struct { |
325 | struct { |
342 | spinlock_t lock; |
326 | spinlock_t lock; |
343 | struct list_head request_list; |
327 | struct list_head request_list; |
344 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
328 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
345 | * chosen to prevent the CPU getting more than a frame ahead of the GPU |
329 | * chosen to prevent the CPU getting more than a frame ahead of the GPU |
346 | * (when using lax throttling for the frontbuffer). We also use it to |
330 | * (when using lax throttling for the frontbuffer). We also use it to |
347 | * offer free GPU waitboosts for severely congested workloads. |
331 | * offer free GPU waitboosts for severely congested workloads. |
348 | */ |
332 | */ |
349 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) |
333 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) |
350 | } mm; |
334 | } mm; |
351 | struct idr context_idr; |
335 | struct idr context_idr; |
352 | 336 | ||
353 | struct intel_rps_client { |
337 | struct intel_rps_client { |
354 | struct list_head link; |
338 | struct list_head link; |
355 | unsigned boosts; |
339 | unsigned boosts; |
356 | } rps; |
340 | } rps; |
357 | 341 | ||
358 | struct intel_engine_cs *bsd_ring; |
342 | struct intel_engine_cs *bsd_ring; |
359 | }; |
343 | }; |
360 | 344 | ||
361 | enum intel_dpll_id { |
345 | enum intel_dpll_id { |
362 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
346 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
363 | /* real shared dpll ids must be >= 0 */ |
347 | /* real shared dpll ids must be >= 0 */ |
364 | DPLL_ID_PCH_PLL_A = 0, |
348 | DPLL_ID_PCH_PLL_A = 0, |
365 | DPLL_ID_PCH_PLL_B = 1, |
349 | DPLL_ID_PCH_PLL_B = 1, |
366 | /* hsw/bdw */ |
350 | /* hsw/bdw */ |
367 | DPLL_ID_WRPLL1 = 0, |
351 | DPLL_ID_WRPLL1 = 0, |
368 | DPLL_ID_WRPLL2 = 1, |
352 | DPLL_ID_WRPLL2 = 1, |
369 | DPLL_ID_SPLL = 2, |
353 | DPLL_ID_SPLL = 2, |
370 | 354 | ||
371 | /* skl */ |
355 | /* skl */ |
372 | DPLL_ID_SKL_DPLL1 = 0, |
356 | DPLL_ID_SKL_DPLL1 = 0, |
373 | DPLL_ID_SKL_DPLL2 = 1, |
357 | DPLL_ID_SKL_DPLL2 = 1, |
374 | DPLL_ID_SKL_DPLL3 = 2, |
358 | DPLL_ID_SKL_DPLL3 = 2, |
375 | }; |
359 | }; |
376 | #define I915_NUM_PLLS 3 |
360 | #define I915_NUM_PLLS 3 |
377 | 361 | ||
378 | struct intel_dpll_hw_state { |
362 | struct intel_dpll_hw_state { |
379 | /* i9xx, pch plls */ |
363 | /* i9xx, pch plls */ |
380 | uint32_t dpll; |
364 | uint32_t dpll; |
381 | uint32_t dpll_md; |
365 | uint32_t dpll_md; |
382 | uint32_t fp0; |
366 | uint32_t fp0; |
383 | uint32_t fp1; |
367 | uint32_t fp1; |
384 | 368 | ||
385 | /* hsw, bdw */ |
369 | /* hsw, bdw */ |
386 | uint32_t wrpll; |
370 | uint32_t wrpll; |
387 | uint32_t spll; |
371 | uint32_t spll; |
388 | 372 | ||
389 | /* skl */ |
373 | /* skl */ |
390 | /* |
374 | /* |
391 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in |
375 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in |
392 | * lower part of ctrl1 and they get shifted into position when writing |
376 | * lower part of ctrl1 and they get shifted into position when writing |
393 | * the register. This allows us to easily compare the state to share |
377 | * the register. This allows us to easily compare the state to share |
394 | * the DPLL. |
378 | * the DPLL. |
395 | */ |
379 | */ |
396 | uint32_t ctrl1; |
380 | uint32_t ctrl1; |
397 | /* HDMI only, 0 when used for DP */ |
381 | /* HDMI only, 0 when used for DP */ |
398 | uint32_t cfgcr1, cfgcr2; |
382 | uint32_t cfgcr1, cfgcr2; |
399 | 383 | ||
400 | /* bxt */ |
384 | /* bxt */ |
401 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
385 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
402 | pcsdw12; |
386 | pcsdw12; |
403 | }; |
387 | }; |
404 | 388 | ||
405 | struct intel_shared_dpll_config { |
389 | struct intel_shared_dpll_config { |
406 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
390 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
407 | struct intel_dpll_hw_state hw_state; |
391 | struct intel_dpll_hw_state hw_state; |
408 | }; |
392 | }; |
409 | 393 | ||
410 | struct intel_shared_dpll { |
394 | struct intel_shared_dpll { |
411 | struct intel_shared_dpll_config config; |
395 | struct intel_shared_dpll_config config; |
412 | 396 | ||
413 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
397 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
414 | bool on; /* is the PLL actually active? Disabled during modeset */ |
398 | bool on; /* is the PLL actually active? Disabled during modeset */ |
415 | const char *name; |
399 | const char *name; |
416 | /* should match the index in the dev_priv->shared_dplls array */ |
400 | /* should match the index in the dev_priv->shared_dplls array */ |
417 | enum intel_dpll_id id; |
401 | enum intel_dpll_id id; |
418 | /* The mode_set hook is optional and should be used together with the |
402 | /* The mode_set hook is optional and should be used together with the |
419 | * intel_prepare_shared_dpll function. */ |
403 | * intel_prepare_shared_dpll function. */ |
420 | void (*mode_set)(struct drm_i915_private *dev_priv, |
404 | void (*mode_set)(struct drm_i915_private *dev_priv, |
421 | struct intel_shared_dpll *pll); |
405 | struct intel_shared_dpll *pll); |
422 | void (*enable)(struct drm_i915_private *dev_priv, |
406 | void (*enable)(struct drm_i915_private *dev_priv, |
423 | struct intel_shared_dpll *pll); |
407 | struct intel_shared_dpll *pll); |
424 | void (*disable)(struct drm_i915_private *dev_priv, |
408 | void (*disable)(struct drm_i915_private *dev_priv, |
425 | struct intel_shared_dpll *pll); |
409 | struct intel_shared_dpll *pll); |
426 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
410 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
427 | struct intel_shared_dpll *pll, |
411 | struct intel_shared_dpll *pll, |
428 | struct intel_dpll_hw_state *hw_state); |
412 | struct intel_dpll_hw_state *hw_state); |
429 | }; |
413 | }; |
430 | 414 | ||
431 | #define SKL_DPLL0 0 |
415 | #define SKL_DPLL0 0 |
432 | #define SKL_DPLL1 1 |
416 | #define SKL_DPLL1 1 |
433 | #define SKL_DPLL2 2 |
417 | #define SKL_DPLL2 2 |
434 | #define SKL_DPLL3 3 |
418 | #define SKL_DPLL3 3 |
435 | 419 | ||
436 | /* Used by dp and fdi links */ |
420 | /* Used by dp and fdi links */ |
437 | struct intel_link_m_n { |
421 | struct intel_link_m_n { |
438 | uint32_t tu; |
422 | uint32_t tu; |
439 | uint32_t gmch_m; |
423 | uint32_t gmch_m; |
440 | uint32_t gmch_n; |
424 | uint32_t gmch_n; |
441 | uint32_t link_m; |
425 | uint32_t link_m; |
442 | uint32_t link_n; |
426 | uint32_t link_n; |
443 | }; |
427 | }; |
444 | 428 | ||
445 | void intel_link_compute_m_n(int bpp, int nlanes, |
429 | void intel_link_compute_m_n(int bpp, int nlanes, |
446 | int pixel_clock, int link_clock, |
430 | int pixel_clock, int link_clock, |
447 | struct intel_link_m_n *m_n); |
431 | struct intel_link_m_n *m_n); |
448 | 432 | ||
449 | /* Interface history: |
433 | /* Interface history: |
450 | * |
434 | * |
451 | * 1.1: Original. |
435 | * 1.1: Original. |
452 | * 1.2: Add Power Management |
436 | * 1.2: Add Power Management |
453 | * 1.3: Add vblank support |
437 | * 1.3: Add vblank support |
454 | * 1.4: Fix cmdbuffer path, add heap destroy |
438 | * 1.4: Fix cmdbuffer path, add heap destroy |
455 | * 1.5: Add vblank pipe configuration |
439 | * 1.5: Add vblank pipe configuration |
456 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
440 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
457 | * - Support vertical blank on secondary display pipe |
441 | * - Support vertical blank on secondary display pipe |
458 | */ |
442 | */ |
459 | #define DRIVER_MAJOR 1 |
443 | #define DRIVER_MAJOR 1 |
460 | #define DRIVER_MINOR 6 |
444 | #define DRIVER_MINOR 6 |
461 | #define DRIVER_PATCHLEVEL 0 |
445 | #define DRIVER_PATCHLEVEL 0 |
462 | 446 | ||
463 | #define WATCH_LISTS 0 |
447 | #define WATCH_LISTS 0 |
464 | 448 | ||
465 | struct opregion_header; |
449 | struct opregion_header; |
466 | struct opregion_acpi; |
450 | struct opregion_acpi; |
467 | struct opregion_swsci; |
451 | struct opregion_swsci; |
468 | struct opregion_asle; |
452 | struct opregion_asle; |
469 | 453 | ||
470 | struct intel_opregion { |
454 | struct intel_opregion { |
471 | struct opregion_header *header; |
455 | struct opregion_header *header; |
472 | struct opregion_acpi *acpi; |
456 | struct opregion_acpi *acpi; |
473 | struct opregion_swsci *swsci; |
457 | struct opregion_swsci *swsci; |
474 | u32 swsci_gbda_sub_functions; |
458 | u32 swsci_gbda_sub_functions; |
475 | u32 swsci_sbcb_sub_functions; |
459 | u32 swsci_sbcb_sub_functions; |
476 | struct opregion_asle *asle; |
460 | struct opregion_asle *asle; |
477 | void *vbt; |
461 | void *rvda; |
- | 462 | const void *vbt; |
|
- | 463 | u32 vbt_size; |
|
478 | u32 *lid_state; |
464 | u32 *lid_state; |
479 | struct work_struct asle_work; |
465 | struct work_struct asle_work; |
480 | }; |
466 | }; |
481 | #define OPREGION_SIZE (8*1024) |
467 | #define OPREGION_SIZE (8*1024) |
482 | 468 | ||
483 | struct intel_overlay; |
469 | struct intel_overlay; |
484 | struct intel_overlay_error_state; |
470 | struct intel_overlay_error_state; |
485 | 471 | ||
486 | #define I915_FENCE_REG_NONE -1 |
472 | #define I915_FENCE_REG_NONE -1 |
487 | #define I915_MAX_NUM_FENCES 32 |
473 | #define I915_MAX_NUM_FENCES 32 |
488 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
474 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
489 | #define I915_MAX_NUM_FENCE_BITS 6 |
475 | #define I915_MAX_NUM_FENCE_BITS 6 |
490 | 476 | ||
491 | struct drm_i915_fence_reg { |
477 | struct drm_i915_fence_reg { |
492 | struct list_head lru_list; |
478 | struct list_head lru_list; |
493 | struct drm_i915_gem_object *obj; |
479 | struct drm_i915_gem_object *obj; |
494 | int pin_count; |
480 | int pin_count; |
495 | }; |
481 | }; |
496 | 482 | ||
497 | struct sdvo_device_mapping { |
483 | struct sdvo_device_mapping { |
498 | u8 initialized; |
484 | u8 initialized; |
499 | u8 dvo_port; |
485 | u8 dvo_port; |
500 | u8 slave_addr; |
486 | u8 slave_addr; |
501 | u8 dvo_wiring; |
487 | u8 dvo_wiring; |
502 | u8 i2c_pin; |
488 | u8 i2c_pin; |
503 | u8 ddc_pin; |
489 | u8 ddc_pin; |
504 | }; |
490 | }; |
505 | 491 | ||
506 | struct intel_display_error_state; |
492 | struct intel_display_error_state; |
507 | 493 | ||
508 | struct drm_i915_error_state { |
494 | struct drm_i915_error_state { |
509 | struct kref ref; |
495 | struct kref ref; |
510 | struct timeval time; |
496 | struct timeval time; |
511 | 497 | ||
512 | char error_msg[128]; |
498 | char error_msg[128]; |
513 | int iommu; |
499 | int iommu; |
514 | u32 reset_count; |
500 | u32 reset_count; |
515 | u32 suspend_count; |
501 | u32 suspend_count; |
516 | 502 | ||
517 | /* Generic register state */ |
503 | /* Generic register state */ |
518 | u32 eir; |
504 | u32 eir; |
519 | u32 pgtbl_er; |
505 | u32 pgtbl_er; |
520 | u32 ier; |
506 | u32 ier; |
521 | u32 gtier[4]; |
507 | u32 gtier[4]; |
522 | u32 ccid; |
508 | u32 ccid; |
523 | u32 derrmr; |
509 | u32 derrmr; |
524 | u32 forcewake; |
510 | u32 forcewake; |
525 | u32 error; /* gen6+ */ |
511 | u32 error; /* gen6+ */ |
526 | u32 err_int; /* gen7 */ |
512 | u32 err_int; /* gen7 */ |
527 | u32 fault_data0; /* gen8, gen9 */ |
513 | u32 fault_data0; /* gen8, gen9 */ |
528 | u32 fault_data1; /* gen8, gen9 */ |
514 | u32 fault_data1; /* gen8, gen9 */ |
529 | u32 done_reg; |
515 | u32 done_reg; |
530 | u32 gac_eco; |
516 | u32 gac_eco; |
531 | u32 gam_ecochk; |
517 | u32 gam_ecochk; |
532 | u32 gab_ctl; |
518 | u32 gab_ctl; |
533 | u32 gfx_mode; |
519 | u32 gfx_mode; |
534 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
520 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
535 | u64 fence[I915_MAX_NUM_FENCES]; |
521 | u64 fence[I915_MAX_NUM_FENCES]; |
536 | struct intel_overlay_error_state *overlay; |
522 | struct intel_overlay_error_state *overlay; |
537 | struct intel_display_error_state *display; |
523 | struct intel_display_error_state *display; |
538 | struct drm_i915_error_object *semaphore_obj; |
524 | struct drm_i915_error_object *semaphore_obj; |
539 | 525 | ||
540 | struct drm_i915_error_ring { |
526 | struct drm_i915_error_ring { |
541 | bool valid; |
527 | bool valid; |
542 | /* Software tracked state */ |
528 | /* Software tracked state */ |
543 | bool waiting; |
529 | bool waiting; |
544 | int hangcheck_score; |
530 | int hangcheck_score; |
545 | enum intel_ring_hangcheck_action hangcheck_action; |
531 | enum intel_ring_hangcheck_action hangcheck_action; |
546 | int num_requests; |
532 | int num_requests; |
547 | 533 | ||
548 | /* our own tracking of ring head and tail */ |
534 | /* our own tracking of ring head and tail */ |
549 | u32 cpu_ring_head; |
535 | u32 cpu_ring_head; |
550 | u32 cpu_ring_tail; |
536 | u32 cpu_ring_tail; |
551 | 537 | ||
552 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; |
538 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; |
553 | 539 | ||
554 | /* Register state */ |
540 | /* Register state */ |
555 | u32 start; |
541 | u32 start; |
556 | u32 tail; |
542 | u32 tail; |
557 | u32 head; |
543 | u32 head; |
558 | u32 ctl; |
544 | u32 ctl; |
559 | u32 hws; |
545 | u32 hws; |
560 | u32 ipeir; |
546 | u32 ipeir; |
561 | u32 ipehr; |
547 | u32 ipehr; |
562 | u32 instdone; |
548 | u32 instdone; |
563 | u32 bbstate; |
549 | u32 bbstate; |
564 | u32 instpm; |
550 | u32 instpm; |
565 | u32 instps; |
551 | u32 instps; |
566 | u32 seqno; |
552 | u32 seqno; |
567 | u64 bbaddr; |
553 | u64 bbaddr; |
568 | u64 acthd; |
554 | u64 acthd; |
569 | u32 fault_reg; |
555 | u32 fault_reg; |
570 | u64 faddr; |
556 | u64 faddr; |
571 | u32 rc_psmi; /* sleep state */ |
557 | u32 rc_psmi; /* sleep state */ |
572 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; |
558 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; |
573 | 559 | ||
574 | struct drm_i915_error_object { |
560 | struct drm_i915_error_object { |
575 | int page_count; |
561 | int page_count; |
576 | u64 gtt_offset; |
562 | u64 gtt_offset; |
577 | u32 *pages[0]; |
563 | u32 *pages[0]; |
578 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
564 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
579 | 565 | ||
580 | struct drm_i915_error_request { |
566 | struct drm_i915_error_request { |
581 | long jiffies; |
567 | long jiffies; |
582 | u32 seqno; |
568 | u32 seqno; |
583 | u32 tail; |
569 | u32 tail; |
584 | } *requests; |
570 | } *requests; |
585 | 571 | ||
586 | struct { |
572 | struct { |
587 | u32 gfx_mode; |
573 | u32 gfx_mode; |
588 | union { |
574 | union { |
589 | u64 pdp[4]; |
575 | u64 pdp[4]; |
590 | u32 pp_dir_base; |
576 | u32 pp_dir_base; |
591 | }; |
577 | }; |
592 | } vm_info; |
578 | } vm_info; |
593 | 579 | ||
594 | pid_t pid; |
580 | pid_t pid; |
595 | char comm[TASK_COMM_LEN]; |
581 | char comm[TASK_COMM_LEN]; |
596 | } ring[I915_NUM_RINGS]; |
582 | } ring[I915_NUM_RINGS]; |
597 | 583 | ||
598 | struct drm_i915_error_buffer { |
584 | struct drm_i915_error_buffer { |
599 | u32 size; |
585 | u32 size; |
600 | u32 name; |
586 | u32 name; |
601 | u32 rseqno[I915_NUM_RINGS], wseqno; |
587 | u32 rseqno[I915_NUM_RINGS], wseqno; |
602 | u64 gtt_offset; |
588 | u64 gtt_offset; |
603 | u32 read_domains; |
589 | u32 read_domains; |
604 | u32 write_domain; |
590 | u32 write_domain; |
605 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
591 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
606 | s32 pinned:2; |
592 | s32 pinned:2; |
607 | u32 tiling:2; |
593 | u32 tiling:2; |
608 | u32 dirty:1; |
594 | u32 dirty:1; |
609 | u32 purgeable:1; |
595 | u32 purgeable:1; |
610 | u32 userptr:1; |
596 | u32 userptr:1; |
611 | s32 ring:4; |
597 | s32 ring:4; |
612 | u32 cache_level:3; |
598 | u32 cache_level:3; |
613 | } **active_bo, **pinned_bo; |
599 | } **active_bo, **pinned_bo; |
614 | 600 | ||
615 | u32 *active_bo_count, *pinned_bo_count; |
601 | u32 *active_bo_count, *pinned_bo_count; |
616 | u32 vm_count; |
602 | u32 vm_count; |
617 | }; |
603 | }; |
618 | 604 | ||
619 | struct intel_connector; |
605 | struct intel_connector; |
620 | struct intel_encoder; |
606 | struct intel_encoder; |
621 | struct intel_crtc_state; |
607 | struct intel_crtc_state; |
622 | struct intel_initial_plane_config; |
608 | struct intel_initial_plane_config; |
623 | struct intel_crtc; |
609 | struct intel_crtc; |
624 | struct intel_limit; |
610 | struct intel_limit; |
625 | struct dpll; |
611 | struct dpll; |
626 | 612 | ||
627 | struct drm_i915_display_funcs { |
613 | struct drm_i915_display_funcs { |
628 | int (*get_display_clock_speed)(struct drm_device *dev); |
614 | int (*get_display_clock_speed)(struct drm_device *dev); |
629 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
615 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
630 | /** |
616 | /** |
631 | * find_dpll() - Find the best values for the PLL |
617 | * find_dpll() - Find the best values for the PLL |
632 | * @limit: limits for the PLL |
618 | * @limit: limits for the PLL |
633 | * @crtc: current CRTC |
619 | * @crtc: current CRTC |
634 | * @target: target frequency in kHz |
620 | * @target: target frequency in kHz |
635 | * @refclk: reference clock frequency in kHz |
621 | * @refclk: reference clock frequency in kHz |
636 | * @match_clock: if provided, @best_clock P divider must |
622 | * @match_clock: if provided, @best_clock P divider must |
637 | * match the P divider from @match_clock |
623 | * match the P divider from @match_clock |
638 | * used for LVDS downclocking |
624 | * used for LVDS downclocking |
639 | * @best_clock: best PLL values found |
625 | * @best_clock: best PLL values found |
640 | * |
626 | * |
641 | * Returns true on success, false on failure. |
627 | * Returns true on success, false on failure. |
642 | */ |
628 | */ |
643 | bool (*find_dpll)(const struct intel_limit *limit, |
629 | bool (*find_dpll)(const struct intel_limit *limit, |
644 | struct intel_crtc_state *crtc_state, |
630 | struct intel_crtc_state *crtc_state, |
645 | int target, int refclk, |
631 | int target, int refclk, |
646 | struct dpll *match_clock, |
632 | struct dpll *match_clock, |
647 | struct dpll *best_clock); |
633 | struct dpll *best_clock); |
- | 634 | int (*compute_pipe_wm)(struct intel_crtc *crtc, |
|
- | 635 | struct drm_atomic_state *state); |
|
648 | void (*update_wm)(struct drm_crtc *crtc); |
636 | void (*update_wm)(struct drm_crtc *crtc); |
649 | void (*update_sprite_wm)(struct drm_plane *plane, |
- | |
650 | struct drm_crtc *crtc, |
- | |
651 | uint32_t sprite_width, uint32_t sprite_height, |
- | |
652 | int pixel_size, bool enable, bool scaled); |
- | |
653 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
637 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
654 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); |
638 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); |
655 | /* Returns the active state of the crtc, and if the crtc is active, |
639 | /* Returns the active state of the crtc, and if the crtc is active, |
656 | * fills out the pipe-config with the hw state. */ |
640 | * fills out the pipe-config with the hw state. */ |
657 | bool (*get_pipe_config)(struct intel_crtc *, |
641 | bool (*get_pipe_config)(struct intel_crtc *, |
658 | struct intel_crtc_state *); |
642 | struct intel_crtc_state *); |
659 | void (*get_initial_plane_config)(struct intel_crtc *, |
643 | void (*get_initial_plane_config)(struct intel_crtc *, |
660 | struct intel_initial_plane_config *); |
644 | struct intel_initial_plane_config *); |
661 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
645 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
662 | struct intel_crtc_state *crtc_state); |
646 | struct intel_crtc_state *crtc_state); |
663 | void (*crtc_enable)(struct drm_crtc *crtc); |
647 | void (*crtc_enable)(struct drm_crtc *crtc); |
664 | void (*crtc_disable)(struct drm_crtc *crtc); |
648 | void (*crtc_disable)(struct drm_crtc *crtc); |
665 | void (*audio_codec_enable)(struct drm_connector *connector, |
649 | void (*audio_codec_enable)(struct drm_connector *connector, |
666 | struct intel_encoder *encoder, |
650 | struct intel_encoder *encoder, |
667 | const struct drm_display_mode *adjusted_mode); |
651 | const struct drm_display_mode *adjusted_mode); |
668 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
652 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
669 | void (*fdi_link_train)(struct drm_crtc *crtc); |
653 | void (*fdi_link_train)(struct drm_crtc *crtc); |
670 | void (*init_clock_gating)(struct drm_device *dev); |
654 | void (*init_clock_gating)(struct drm_device *dev); |
671 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
655 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
672 | struct drm_framebuffer *fb, |
656 | struct drm_framebuffer *fb, |
673 | struct drm_i915_gem_object *obj, |
657 | struct drm_i915_gem_object *obj, |
674 | struct drm_i915_gem_request *req, |
658 | struct drm_i915_gem_request *req, |
675 | uint32_t flags); |
659 | uint32_t flags); |
676 | void (*update_primary_plane)(struct drm_crtc *crtc, |
660 | void (*update_primary_plane)(struct drm_crtc *crtc, |
677 | struct drm_framebuffer *fb, |
661 | struct drm_framebuffer *fb, |
678 | int x, int y); |
662 | int x, int y); |
679 | void (*hpd_irq_setup)(struct drm_device *dev); |
663 | void (*hpd_irq_setup)(struct drm_device *dev); |
680 | /* clock updates for mode set */ |
664 | /* clock updates for mode set */ |
681 | /* cursor updates */ |
665 | /* cursor updates */ |
682 | /* render clock increase/decrease */ |
666 | /* render clock increase/decrease */ |
683 | /* display clock increase/decrease */ |
667 | /* display clock increase/decrease */ |
684 | /* pll clock increase/decrease */ |
668 | /* pll clock increase/decrease */ |
685 | }; |
669 | }; |
686 | 670 | ||
687 | enum forcewake_domain_id { |
671 | enum forcewake_domain_id { |
688 | FW_DOMAIN_ID_RENDER = 0, |
672 | FW_DOMAIN_ID_RENDER = 0, |
689 | FW_DOMAIN_ID_BLITTER, |
673 | FW_DOMAIN_ID_BLITTER, |
690 | FW_DOMAIN_ID_MEDIA, |
674 | FW_DOMAIN_ID_MEDIA, |
691 | 675 | ||
692 | FW_DOMAIN_ID_COUNT |
676 | FW_DOMAIN_ID_COUNT |
693 | }; |
677 | }; |
694 | 678 | ||
695 | enum forcewake_domains { |
679 | enum forcewake_domains { |
696 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), |
680 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), |
697 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), |
681 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), |
698 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), |
682 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), |
699 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | |
683 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | |
700 | FORCEWAKE_BLITTER | |
684 | FORCEWAKE_BLITTER | |
701 | FORCEWAKE_MEDIA) |
685 | FORCEWAKE_MEDIA) |
702 | }; |
686 | }; |
703 | 687 | ||
704 | struct intel_uncore_funcs { |
688 | struct intel_uncore_funcs { |
705 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
689 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
706 | enum forcewake_domains domains); |
690 | enum forcewake_domains domains); |
707 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
691 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
708 | enum forcewake_domains domains); |
692 | enum forcewake_domains domains); |
709 | 693 | ||
710 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
694 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
711 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
695 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
712 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
696 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
713 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
697 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); |
714 | 698 | ||
715 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
699 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, |
716 | uint8_t val, bool trace); |
700 | uint8_t val, bool trace); |
717 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
701 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, |
718 | uint16_t val, bool trace); |
702 | uint16_t val, bool trace); |
719 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
703 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, |
720 | uint32_t val, bool trace); |
704 | uint32_t val, bool trace); |
721 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
705 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, |
722 | uint64_t val, bool trace); |
706 | uint64_t val, bool trace); |
723 | }; |
707 | }; |
724 | 708 | ||
725 | struct intel_uncore { |
709 | struct intel_uncore { |
726 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
710 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
727 | 711 | ||
728 | struct intel_uncore_funcs funcs; |
712 | struct intel_uncore_funcs funcs; |
729 | 713 | ||
730 | unsigned fifo_count; |
714 | unsigned fifo_count; |
731 | enum forcewake_domains fw_domains; |
715 | enum forcewake_domains fw_domains; |
732 | 716 | ||
733 | struct intel_uncore_forcewake_domain { |
717 | struct intel_uncore_forcewake_domain { |
734 | struct drm_i915_private *i915; |
718 | struct drm_i915_private *i915; |
735 | enum forcewake_domain_id id; |
719 | enum forcewake_domain_id id; |
736 | unsigned wake_count; |
720 | unsigned wake_count; |
737 | struct timer_list timer; |
721 | struct timer_list timer; |
738 | u32 reg_set; |
722 | i915_reg_t reg_set; |
739 | u32 val_set; |
723 | u32 val_set; |
740 | u32 val_clear; |
724 | u32 val_clear; |
741 | u32 reg_ack; |
725 | i915_reg_t reg_ack; |
742 | u32 reg_post; |
726 | i915_reg_t reg_post; |
743 | u32 val_reset; |
727 | u32 val_reset; |
744 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
728 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
745 | }; |
729 | }; |
746 | 730 | ||
747 | /* Iterate over initialised fw domains */ |
731 | /* Iterate over initialised fw domains */ |
748 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ |
732 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ |
749 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ |
733 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ |
750 | (i__) < FW_DOMAIN_ID_COUNT; \ |
734 | (i__) < FW_DOMAIN_ID_COUNT; \ |
751 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ |
735 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ |
752 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
736 | for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) |
753 | 737 | ||
754 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ |
738 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ |
755 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) |
739 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) |
756 | 740 | ||
757 | enum csr_state { |
741 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
758 | FW_UNINITIALIZED = 0, |
742 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) |
759 | FW_LOADED, |
- | |
760 | FW_FAILED |
- | |
761 | }; |
743 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) |
- | 744 | ||
762 | 745 | struct intel_csr { |
|
763 | struct intel_csr { |
746 | struct work_struct work; |
764 | const char *fw_path; |
747 | const char *fw_path; |
765 | uint32_t *dmc_payload; |
748 | uint32_t *dmc_payload; |
766 | uint32_t dmc_fw_size; |
749 | uint32_t dmc_fw_size; |
- | 750 | uint32_t version; |
|
767 | uint32_t mmio_count; |
751 | uint32_t mmio_count; |
768 | uint32_t mmioaddr[8]; |
752 | i915_reg_t mmioaddr[8]; |
769 | uint32_t mmiodata[8]; |
753 | uint32_t mmiodata[8]; |
770 | enum csr_state state; |
754 | uint32_t dc_state; |
771 | }; |
755 | }; |
772 | 756 | ||
773 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
757 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
774 | func(is_mobile) sep \ |
758 | func(is_mobile) sep \ |
775 | func(is_i85x) sep \ |
759 | func(is_i85x) sep \ |
776 | func(is_i915g) sep \ |
760 | func(is_i915g) sep \ |
777 | func(is_i945gm) sep \ |
761 | func(is_i945gm) sep \ |
778 | func(is_g33) sep \ |
762 | func(is_g33) sep \ |
779 | func(need_gfx_hws) sep \ |
763 | func(need_gfx_hws) sep \ |
780 | func(is_g4x) sep \ |
764 | func(is_g4x) sep \ |
781 | func(is_pineview) sep \ |
765 | func(is_pineview) sep \ |
782 | func(is_broadwater) sep \ |
766 | func(is_broadwater) sep \ |
783 | func(is_crestline) sep \ |
767 | func(is_crestline) sep \ |
784 | func(is_ivybridge) sep \ |
768 | func(is_ivybridge) sep \ |
785 | func(is_valleyview) sep \ |
769 | func(is_valleyview) sep \ |
- | 770 | func(is_cherryview) sep \ |
|
786 | func(is_haswell) sep \ |
771 | func(is_haswell) sep \ |
787 | func(is_skylake) sep \ |
772 | func(is_skylake) sep \ |
- | 773 | func(is_broxton) sep \ |
|
- | 774 | func(is_kabylake) sep \ |
|
788 | func(is_preliminary) sep \ |
775 | func(is_preliminary) sep \ |
789 | func(has_fbc) sep \ |
776 | func(has_fbc) sep \ |
790 | func(has_pipe_cxsr) sep \ |
777 | func(has_pipe_cxsr) sep \ |
791 | func(has_hotplug) sep \ |
778 | func(has_hotplug) sep \ |
792 | func(cursor_needs_physical) sep \ |
779 | func(cursor_needs_physical) sep \ |
793 | func(has_overlay) sep \ |
780 | func(has_overlay) sep \ |
794 | func(overlay_needs_physical) sep \ |
781 | func(overlay_needs_physical) sep \ |
795 | func(supports_tv) sep \ |
782 | func(supports_tv) sep \ |
796 | func(has_llc) sep \ |
783 | func(has_llc) sep \ |
797 | func(has_ddi) sep \ |
784 | func(has_ddi) sep \ |
798 | func(has_fpga_dbg) |
785 | func(has_fpga_dbg) |
799 | 786 | ||
800 | #define DEFINE_FLAG(name) u8 name:1 |
787 | #define DEFINE_FLAG(name) u8 name:1 |
801 | #define SEP_SEMICOLON ; |
788 | #define SEP_SEMICOLON ; |
802 | 789 | ||
803 | struct intel_device_info { |
790 | struct intel_device_info { |
804 | u32 display_mmio_offset; |
791 | u32 display_mmio_offset; |
805 | u16 device_id; |
792 | u16 device_id; |
806 | u8 num_pipes:3; |
793 | u8 num_pipes:3; |
807 | u8 num_sprites[I915_MAX_PIPES]; |
794 | u8 num_sprites[I915_MAX_PIPES]; |
808 | u8 gen; |
795 | u8 gen; |
809 | u8 ring_mask; /* Rings supported by the HW */ |
796 | u8 ring_mask; /* Rings supported by the HW */ |
810 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
797 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
811 | /* Register offsets for the various display pipes and transcoders */ |
798 | /* Register offsets for the various display pipes and transcoders */ |
812 | int pipe_offsets[I915_MAX_TRANSCODERS]; |
799 | int pipe_offsets[I915_MAX_TRANSCODERS]; |
813 | int trans_offsets[I915_MAX_TRANSCODERS]; |
800 | int trans_offsets[I915_MAX_TRANSCODERS]; |
814 | int palette_offsets[I915_MAX_PIPES]; |
801 | int palette_offsets[I915_MAX_PIPES]; |
815 | int cursor_offsets[I915_MAX_PIPES]; |
802 | int cursor_offsets[I915_MAX_PIPES]; |
816 | 803 | ||
817 | /* Slice/subslice/EU info */ |
804 | /* Slice/subslice/EU info */ |
818 | u8 slice_total; |
805 | u8 slice_total; |
819 | u8 subslice_total; |
806 | u8 subslice_total; |
820 | u8 subslice_per_slice; |
807 | u8 subslice_per_slice; |
821 | u8 eu_total; |
808 | u8 eu_total; |
822 | u8 eu_per_subslice; |
809 | u8 eu_per_subslice; |
823 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
810 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
824 | u8 subslice_7eu[3]; |
811 | u8 subslice_7eu[3]; |
825 | u8 has_slice_pg:1; |
812 | u8 has_slice_pg:1; |
826 | u8 has_subslice_pg:1; |
813 | u8 has_subslice_pg:1; |
827 | u8 has_eu_pg:1; |
814 | u8 has_eu_pg:1; |
828 | }; |
815 | }; |
829 | 816 | ||
830 | #undef DEFINE_FLAG |
817 | #undef DEFINE_FLAG |
831 | #undef SEP_SEMICOLON |
818 | #undef SEP_SEMICOLON |
832 | 819 | ||
833 | enum i915_cache_level { |
820 | enum i915_cache_level { |
834 | I915_CACHE_NONE = 0, |
821 | I915_CACHE_NONE = 0, |
835 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
822 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
836 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
823 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
837 | caches, eg sampler/render caches, and the |
824 | caches, eg sampler/render caches, and the |
838 | large Last-Level-Cache. LLC is coherent with |
825 | large Last-Level-Cache. LLC is coherent with |
839 | the CPU, but L3 is only visible to the GPU. */ |
826 | the CPU, but L3 is only visible to the GPU. */ |
840 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
827 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
841 | }; |
828 | }; |
842 | 829 | ||
843 | struct i915_ctx_hang_stats { |
830 | struct i915_ctx_hang_stats { |
844 | /* This context had batch pending when hang was declared */ |
831 | /* This context had batch pending when hang was declared */ |
845 | unsigned batch_pending; |
832 | unsigned batch_pending; |
846 | 833 | ||
847 | /* This context had batch active when hang was declared */ |
834 | /* This context had batch active when hang was declared */ |
848 | unsigned batch_active; |
835 | unsigned batch_active; |
849 | 836 | ||
850 | /* Time when this context was last blamed for a GPU reset */ |
837 | /* Time when this context was last blamed for a GPU reset */ |
851 | unsigned long guilty_ts; |
838 | unsigned long guilty_ts; |
852 | 839 | ||
853 | /* If the contexts causes a second GPU hang within this time, |
840 | /* If the contexts causes a second GPU hang within this time, |
854 | * it is permanently banned from submitting any more work. |
841 | * it is permanently banned from submitting any more work. |
855 | */ |
842 | */ |
856 | unsigned long ban_period_seconds; |
843 | unsigned long ban_period_seconds; |
857 | 844 | ||
858 | /* This context is banned to submit more work */ |
845 | /* This context is banned to submit more work */ |
859 | bool banned; |
846 | bool banned; |
860 | }; |
847 | }; |
861 | 848 | ||
862 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
849 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
863 | #define DEFAULT_CONTEXT_HANDLE 0 |
850 | #define DEFAULT_CONTEXT_HANDLE 0 |
864 | 851 | ||
865 | #define CONTEXT_NO_ZEROMAP (1<<0) |
852 | #define CONTEXT_NO_ZEROMAP (1<<0) |
866 | /** |
853 | /** |
867 | * struct intel_context - as the name implies, represents a context. |
854 | * struct intel_context - as the name implies, represents a context. |
868 | * @ref: reference count. |
855 | * @ref: reference count. |
869 | * @user_handle: userspace tracking identity for this context. |
856 | * @user_handle: userspace tracking identity for this context. |
870 | * @remap_slice: l3 row remapping information. |
857 | * @remap_slice: l3 row remapping information. |
871 | * @flags: context specific flags: |
858 | * @flags: context specific flags: |
872 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. |
859 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. |
873 | * @file_priv: filp associated with this context (NULL for global default |
860 | * @file_priv: filp associated with this context (NULL for global default |
874 | * context). |
861 | * context). |
875 | * @hang_stats: information about the role of this context in possible GPU |
862 | * @hang_stats: information about the role of this context in possible GPU |
876 | * hangs. |
863 | * hangs. |
877 | * @ppgtt: virtual memory space used by this context. |
864 | * @ppgtt: virtual memory space used by this context. |
878 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
865 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
879 | * initialized (legacy ring submission mechanism only). |
866 | * initialized (legacy ring submission mechanism only). |
880 | * @link: link in the global list of contexts. |
867 | * @link: link in the global list of contexts. |
881 | * |
868 | * |
882 | * Contexts are memory images used by the hardware to store copies of their |
869 | * Contexts are memory images used by the hardware to store copies of their |
883 | * internal state. |
870 | * internal state. |
884 | */ |
871 | */ |
885 | struct intel_context { |
872 | struct intel_context { |
886 | struct kref ref; |
873 | struct kref ref; |
887 | int user_handle; |
874 | int user_handle; |
888 | uint8_t remap_slice; |
875 | uint8_t remap_slice; |
889 | struct drm_i915_private *i915; |
876 | struct drm_i915_private *i915; |
890 | int flags; |
877 | int flags; |
891 | struct drm_i915_file_private *file_priv; |
878 | struct drm_i915_file_private *file_priv; |
892 | struct i915_ctx_hang_stats hang_stats; |
879 | struct i915_ctx_hang_stats hang_stats; |
893 | struct i915_hw_ppgtt *ppgtt; |
880 | struct i915_hw_ppgtt *ppgtt; |
894 | 881 | ||
895 | /* Legacy ring buffer submission */ |
882 | /* Legacy ring buffer submission */ |
896 | struct { |
883 | struct { |
897 | struct drm_i915_gem_object *rcs_state; |
884 | struct drm_i915_gem_object *rcs_state; |
898 | bool initialized; |
885 | bool initialized; |
899 | } legacy_hw_ctx; |
886 | } legacy_hw_ctx; |
900 | 887 | ||
901 | /* Execlists */ |
888 | /* Execlists */ |
902 | struct { |
889 | struct { |
903 | struct drm_i915_gem_object *state; |
890 | struct drm_i915_gem_object *state; |
904 | struct intel_ringbuffer *ringbuf; |
891 | struct intel_ringbuffer *ringbuf; |
905 | int pin_count; |
892 | int pin_count; |
906 | } engine[I915_NUM_RINGS]; |
893 | } engine[I915_NUM_RINGS]; |
907 | 894 | ||
908 | struct list_head link; |
895 | struct list_head link; |
909 | }; |
896 | }; |
910 | 897 | ||
911 | enum fb_op_origin { |
898 | enum fb_op_origin { |
912 | ORIGIN_GTT, |
899 | ORIGIN_GTT, |
913 | ORIGIN_CPU, |
900 | ORIGIN_CPU, |
914 | ORIGIN_CS, |
901 | ORIGIN_CS, |
915 | ORIGIN_FLIP, |
902 | ORIGIN_FLIP, |
916 | ORIGIN_DIRTYFB, |
903 | ORIGIN_DIRTYFB, |
917 | }; |
904 | }; |
918 | 905 | ||
919 | struct i915_fbc { |
906 | struct i915_fbc { |
920 | /* This is always the inner lock when overlapping with struct_mutex and |
907 | /* This is always the inner lock when overlapping with struct_mutex and |
921 | * it's the outer lock when overlapping with stolen_lock. */ |
908 | * it's the outer lock when overlapping with stolen_lock. */ |
922 | struct mutex lock; |
909 | struct mutex lock; |
923 | unsigned long uncompressed_size; |
- | |
924 | unsigned threshold; |
910 | unsigned threshold; |
925 | unsigned int fb_id; |
911 | unsigned int fb_id; |
926 | unsigned int possible_framebuffer_bits; |
912 | unsigned int possible_framebuffer_bits; |
927 | unsigned int busy_bits; |
913 | unsigned int busy_bits; |
928 | struct intel_crtc *crtc; |
914 | struct intel_crtc *crtc; |
929 | int y; |
915 | int y; |
930 | 916 | ||
931 | struct drm_mm_node compressed_fb; |
917 | struct drm_mm_node compressed_fb; |
932 | struct drm_mm_node *compressed_llb; |
918 | struct drm_mm_node *compressed_llb; |
933 | 919 | ||
934 | bool false_color; |
920 | bool false_color; |
935 | - | ||
936 | /* Tracks whether the HW is actually enabled, not whether the feature is |
- | |
937 | * possible. */ |
921 | |
- | 922 | bool enabled; |
|
938 | bool enabled; |
923 | bool active; |
939 | 924 | ||
940 | struct intel_fbc_work { |
925 | struct intel_fbc_work { |
941 | struct delayed_work work; |
926 | bool scheduled; |
- | 927 | struct work_struct work; |
|
942 | struct intel_crtc *crtc; |
928 | struct drm_framebuffer *fb; |
- | 929 | unsigned long enable_jiffies; |
|
- | 930 | } work; |
|
943 | struct drm_framebuffer *fb; |
- | |
944 | } *fbc_work; |
- | |
945 | - | ||
946 | enum no_fbc_reason { |
- | |
947 | FBC_OK, /* FBC is enabled */ |
- | |
948 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
- | |
949 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
- | |
950 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
- | |
951 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
- | |
952 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
- | |
953 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
- | |
954 | FBC_NOT_TILED, /* buffer not tiled */ |
- | |
955 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
- | |
956 | FBC_MODULE_PARAM, |
- | |
957 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
- | |
958 | FBC_ROTATION, /* rotation is not supported */ |
- | |
959 | FBC_IN_DBG_MASTER, /* kernel debugger is active */ |
- | |
960 | FBC_BAD_STRIDE, /* stride is not supported */ |
- | |
961 | FBC_PIXEL_RATE, /* pixel rate is too big */ |
- | |
962 | FBC_PIXEL_FORMAT /* pixel format is invalid */ |
931 | |
963 | } no_fbc_reason; |
932 | const char *no_fbc_reason; |
964 | 933 | ||
965 | bool (*fbc_enabled)(struct drm_i915_private *dev_priv); |
934 | bool (*is_active)(struct drm_i915_private *dev_priv); |
966 | void (*enable_fbc)(struct intel_crtc *crtc); |
935 | void (*activate)(struct intel_crtc *crtc); |
967 | void (*disable_fbc)(struct drm_i915_private *dev_priv); |
936 | void (*deactivate)(struct drm_i915_private *dev_priv); |
968 | }; |
937 | }; |
969 | 938 | ||
970 | /** |
939 | /** |
971 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
940 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
972 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
941 | * LOW_RR is the lowest eDP panel refresh rate found from EDID |
973 | * parsing for same resolution. |
942 | * parsing for same resolution. |
974 | */ |
943 | */ |
975 | enum drrs_refresh_rate_type { |
944 | enum drrs_refresh_rate_type { |
976 | DRRS_HIGH_RR, |
945 | DRRS_HIGH_RR, |
977 | DRRS_LOW_RR, |
946 | DRRS_LOW_RR, |
978 | DRRS_MAX_RR, /* RR count */ |
947 | DRRS_MAX_RR, /* RR count */ |
979 | }; |
948 | }; |
980 | 949 | ||
981 | enum drrs_support_type { |
950 | enum drrs_support_type { |
982 | DRRS_NOT_SUPPORTED = 0, |
951 | DRRS_NOT_SUPPORTED = 0, |
983 | STATIC_DRRS_SUPPORT = 1, |
952 | STATIC_DRRS_SUPPORT = 1, |
984 | SEAMLESS_DRRS_SUPPORT = 2 |
953 | SEAMLESS_DRRS_SUPPORT = 2 |
985 | }; |
954 | }; |
986 | 955 | ||
987 | struct intel_dp; |
956 | struct intel_dp; |
988 | struct i915_drrs { |
957 | struct i915_drrs { |
989 | struct mutex mutex; |
958 | struct mutex mutex; |
990 | struct delayed_work work; |
959 | struct delayed_work work; |
991 | struct intel_dp *dp; |
960 | struct intel_dp *dp; |
992 | unsigned busy_frontbuffer_bits; |
961 | unsigned busy_frontbuffer_bits; |
993 | enum drrs_refresh_rate_type refresh_rate_type; |
962 | enum drrs_refresh_rate_type refresh_rate_type; |
994 | enum drrs_support_type type; |
963 | enum drrs_support_type type; |
995 | }; |
964 | }; |
996 | 965 | ||
997 | struct i915_psr { |
966 | struct i915_psr { |
998 | struct mutex lock; |
967 | struct mutex lock; |
999 | bool sink_support; |
968 | bool sink_support; |
1000 | bool source_ok; |
969 | bool source_ok; |
1001 | struct intel_dp *enabled; |
970 | struct intel_dp *enabled; |
1002 | bool active; |
971 | bool active; |
1003 | struct delayed_work work; |
972 | struct delayed_work work; |
1004 | unsigned busy_frontbuffer_bits; |
973 | unsigned busy_frontbuffer_bits; |
1005 | bool psr2_support; |
974 | bool psr2_support; |
1006 | bool aux_frame_sync; |
975 | bool aux_frame_sync; |
1007 | }; |
976 | }; |
1008 | 977 | ||
1009 | enum intel_pch { |
978 | enum intel_pch { |
1010 | PCH_NONE = 0, /* No PCH present */ |
979 | PCH_NONE = 0, /* No PCH present */ |
1011 | PCH_IBX, /* Ibexpeak PCH */ |
980 | PCH_IBX, /* Ibexpeak PCH */ |
1012 | PCH_CPT, /* Cougarpoint PCH */ |
981 | PCH_CPT, /* Cougarpoint PCH */ |
1013 | PCH_LPT, /* Lynxpoint PCH */ |
982 | PCH_LPT, /* Lynxpoint PCH */ |
1014 | PCH_SPT, /* Sunrisepoint PCH */ |
983 | PCH_SPT, /* Sunrisepoint PCH */ |
1015 | PCH_NOP, |
984 | PCH_NOP, |
1016 | }; |
985 | }; |
1017 | 986 | ||
1018 | enum intel_sbi_destination { |
987 | enum intel_sbi_destination { |
1019 | SBI_ICLK, |
988 | SBI_ICLK, |
1020 | SBI_MPHY, |
989 | SBI_MPHY, |
1021 | }; |
990 | }; |
1022 | 991 | ||
1023 | #define QUIRK_PIPEA_FORCE (1<<0) |
992 | #define QUIRK_PIPEA_FORCE (1<<0) |
1024 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
993 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
1025 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
994 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
1026 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
995 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
1027 | #define QUIRK_PIPEB_FORCE (1<<4) |
996 | #define QUIRK_PIPEB_FORCE (1<<4) |
1028 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
997 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
1029 | 998 | ||
1030 | struct intel_fbdev; |
999 | struct intel_fbdev; |
1031 | struct intel_fbc_work; |
1000 | struct intel_fbc_work; |
1032 | 1001 | ||
1033 | struct intel_gmbus { |
1002 | struct intel_gmbus { |
1034 | struct i2c_adapter adapter; |
1003 | struct i2c_adapter adapter; |
1035 | u32 force_bit; |
1004 | u32 force_bit; |
1036 | u32 reg0; |
1005 | u32 reg0; |
1037 | u32 gpio_reg; |
1006 | i915_reg_t gpio_reg; |
1038 | struct i2c_algo_bit_data bit_algo; |
1007 | struct i2c_algo_bit_data bit_algo; |
1039 | struct drm_i915_private *dev_priv; |
1008 | struct drm_i915_private *dev_priv; |
1040 | }; |
1009 | }; |
1041 | 1010 | ||
1042 | struct i915_suspend_saved_registers { |
1011 | struct i915_suspend_saved_registers { |
1043 | u32 saveDSPARB; |
1012 | u32 saveDSPARB; |
1044 | u32 saveLVDS; |
1013 | u32 saveLVDS; |
1045 | u32 savePP_ON_DELAYS; |
1014 | u32 savePP_ON_DELAYS; |
1046 | u32 savePP_OFF_DELAYS; |
1015 | u32 savePP_OFF_DELAYS; |
1047 | u32 savePP_ON; |
1016 | u32 savePP_ON; |
1048 | u32 savePP_OFF; |
1017 | u32 savePP_OFF; |
1049 | u32 savePP_CONTROL; |
1018 | u32 savePP_CONTROL; |
1050 | u32 savePP_DIVISOR; |
1019 | u32 savePP_DIVISOR; |
1051 | u32 saveFBC_CONTROL; |
1020 | u32 saveFBC_CONTROL; |
1052 | u32 saveCACHE_MODE_0; |
1021 | u32 saveCACHE_MODE_0; |
1053 | u32 saveMI_ARB_STATE; |
1022 | u32 saveMI_ARB_STATE; |
1054 | u32 saveSWF0[16]; |
1023 | u32 saveSWF0[16]; |
1055 | u32 saveSWF1[16]; |
1024 | u32 saveSWF1[16]; |
1056 | u32 saveSWF3[3]; |
1025 | u32 saveSWF3[3]; |
1057 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1026 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1058 | u32 savePCH_PORT_HOTPLUG; |
1027 | u32 savePCH_PORT_HOTPLUG; |
1059 | u16 saveGCDGMBUS; |
1028 | u16 saveGCDGMBUS; |
1060 | }; |
1029 | }; |
1061 | 1030 | ||
1062 | struct vlv_s0ix_state { |
1031 | struct vlv_s0ix_state { |
1063 | /* GAM */ |
1032 | /* GAM */ |
1064 | u32 wr_watermark; |
1033 | u32 wr_watermark; |
1065 | u32 gfx_prio_ctrl; |
1034 | u32 gfx_prio_ctrl; |
1066 | u32 arb_mode; |
1035 | u32 arb_mode; |
1067 | u32 gfx_pend_tlb0; |
1036 | u32 gfx_pend_tlb0; |
1068 | u32 gfx_pend_tlb1; |
1037 | u32 gfx_pend_tlb1; |
1069 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; |
1038 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; |
1070 | u32 media_max_req_count; |
1039 | u32 media_max_req_count; |
1071 | u32 gfx_max_req_count; |
1040 | u32 gfx_max_req_count; |
1072 | u32 render_hwsp; |
1041 | u32 render_hwsp; |
1073 | u32 ecochk; |
1042 | u32 ecochk; |
1074 | u32 bsd_hwsp; |
1043 | u32 bsd_hwsp; |
1075 | u32 blt_hwsp; |
1044 | u32 blt_hwsp; |
1076 | u32 tlb_rd_addr; |
1045 | u32 tlb_rd_addr; |
1077 | 1046 | ||
1078 | /* MBC */ |
1047 | /* MBC */ |
1079 | u32 g3dctl; |
1048 | u32 g3dctl; |
1080 | u32 gsckgctl; |
1049 | u32 gsckgctl; |
1081 | u32 mbctl; |
1050 | u32 mbctl; |
1082 | 1051 | ||
1083 | /* GCP */ |
1052 | /* GCP */ |
1084 | u32 ucgctl1; |
1053 | u32 ucgctl1; |
1085 | u32 ucgctl3; |
1054 | u32 ucgctl3; |
1086 | u32 rcgctl1; |
1055 | u32 rcgctl1; |
1087 | u32 rcgctl2; |
1056 | u32 rcgctl2; |
1088 | u32 rstctl; |
1057 | u32 rstctl; |
1089 | u32 misccpctl; |
1058 | u32 misccpctl; |
1090 | 1059 | ||
1091 | /* GPM */ |
1060 | /* GPM */ |
1092 | u32 gfxpause; |
1061 | u32 gfxpause; |
1093 | u32 rpdeuhwtc; |
1062 | u32 rpdeuhwtc; |
1094 | u32 rpdeuc; |
1063 | u32 rpdeuc; |
1095 | u32 ecobus; |
1064 | u32 ecobus; |
1096 | u32 pwrdwnupctl; |
1065 | u32 pwrdwnupctl; |
1097 | u32 rp_down_timeout; |
1066 | u32 rp_down_timeout; |
1098 | u32 rp_deucsw; |
1067 | u32 rp_deucsw; |
1099 | u32 rcubmabdtmr; |
1068 | u32 rcubmabdtmr; |
1100 | u32 rcedata; |
1069 | u32 rcedata; |
1101 | u32 spare2gh; |
1070 | u32 spare2gh; |
1102 | 1071 | ||
1103 | /* Display 1 CZ domain */ |
1072 | /* Display 1 CZ domain */ |
1104 | u32 gt_imr; |
1073 | u32 gt_imr; |
1105 | u32 gt_ier; |
1074 | u32 gt_ier; |
1106 | u32 pm_imr; |
1075 | u32 pm_imr; |
1107 | u32 pm_ier; |
1076 | u32 pm_ier; |
1108 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; |
1077 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; |
1109 | 1078 | ||
1110 | /* GT SA CZ domain */ |
1079 | /* GT SA CZ domain */ |
1111 | u32 tilectl; |
1080 | u32 tilectl; |
1112 | u32 gt_fifoctl; |
1081 | u32 gt_fifoctl; |
1113 | u32 gtlc_wake_ctrl; |
1082 | u32 gtlc_wake_ctrl; |
1114 | u32 gtlc_survive; |
1083 | u32 gtlc_survive; |
1115 | u32 pmwgicz; |
1084 | u32 pmwgicz; |
1116 | 1085 | ||
1117 | /* Display 2 CZ domain */ |
1086 | /* Display 2 CZ domain */ |
1118 | u32 gu_ctl0; |
1087 | u32 gu_ctl0; |
1119 | u32 gu_ctl1; |
1088 | u32 gu_ctl1; |
1120 | u32 pcbr; |
1089 | u32 pcbr; |
1121 | u32 clock_gate_dis2; |
1090 | u32 clock_gate_dis2; |
1122 | }; |
1091 | }; |
1123 | 1092 | ||
1124 | struct intel_rps_ei { |
1093 | struct intel_rps_ei { |
1125 | u32 cz_clock; |
1094 | u32 cz_clock; |
1126 | u32 render_c0; |
1095 | u32 render_c0; |
1127 | u32 media_c0; |
1096 | u32 media_c0; |
1128 | }; |
1097 | }; |
1129 | 1098 | ||
1130 | struct intel_gen6_power_mgmt { |
1099 | struct intel_gen6_power_mgmt { |
1131 | /* |
1100 | /* |
1132 | * work, interrupts_enabled and pm_iir are protected by |
1101 | * work, interrupts_enabled and pm_iir are protected by |
1133 | * dev_priv->irq_lock |
1102 | * dev_priv->irq_lock |
1134 | */ |
1103 | */ |
1135 | struct work_struct work; |
1104 | struct work_struct work; |
1136 | bool interrupts_enabled; |
1105 | bool interrupts_enabled; |
1137 | u32 pm_iir; |
1106 | u32 pm_iir; |
1138 | 1107 | ||
1139 | /* Frequencies are stored in potentially platform dependent multiples. |
1108 | /* Frequencies are stored in potentially platform dependent multiples. |
1140 | * In other words, *_freq needs to be multiplied by X to be interesting. |
1109 | * In other words, *_freq needs to be multiplied by X to be interesting. |
1141 | * Soft limits are those which are used for the dynamic reclocking done |
1110 | * Soft limits are those which are used for the dynamic reclocking done |
1142 | * by the driver (raise frequencies under heavy loads, and lower for |
1111 | * by the driver (raise frequencies under heavy loads, and lower for |
1143 | * lighter loads). Hard limits are those imposed by the hardware. |
1112 | * lighter loads). Hard limits are those imposed by the hardware. |
1144 | * |
1113 | * |
1145 | * A distinction is made for overclocking, which is never enabled by |
1114 | * A distinction is made for overclocking, which is never enabled by |
1146 | * default, and is considered to be above the hard limit if it's |
1115 | * default, and is considered to be above the hard limit if it's |
1147 | * possible at all. |
1116 | * possible at all. |
1148 | */ |
1117 | */ |
1149 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ |
1118 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ |
1150 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ |
1119 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ |
1151 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ |
1120 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ |
1152 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ |
1121 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ |
1153 | u8 min_freq; /* AKA RPn. Minimum frequency */ |
1122 | u8 min_freq; /* AKA RPn. Minimum frequency */ |
1154 | u8 idle_freq; /* Frequency to request when we are idle */ |
1123 | u8 idle_freq; /* Frequency to request when we are idle */ |
1155 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1124 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1156 | u8 rp1_freq; /* "less than" RP0 power/freqency */ |
1125 | u8 rp1_freq; /* "less than" RP0 power/freqency */ |
1157 | u8 rp0_freq; /* Non-overclocked max frequency. */ |
1126 | u8 rp0_freq; /* Non-overclocked max frequency. */ |
1158 | 1127 | ||
1159 | u8 up_threshold; /* Current %busy required to uplock */ |
1128 | u8 up_threshold; /* Current %busy required to uplock */ |
1160 | u8 down_threshold; /* Current %busy required to downclock */ |
1129 | u8 down_threshold; /* Current %busy required to downclock */ |
1161 | 1130 | ||
1162 | int last_adj; |
1131 | int last_adj; |
1163 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
1132 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
1164 | 1133 | ||
1165 | spinlock_t client_lock; |
1134 | spinlock_t client_lock; |
1166 | struct list_head clients; |
1135 | struct list_head clients; |
1167 | bool client_boost; |
1136 | bool client_boost; |
1168 | 1137 | ||
1169 | bool enabled; |
1138 | bool enabled; |
1170 | struct delayed_work delayed_resume_work; |
1139 | struct delayed_work delayed_resume_work; |
1171 | unsigned boosts; |
1140 | unsigned boosts; |
1172 | 1141 | ||
1173 | struct intel_rps_client semaphores, mmioflips; |
1142 | struct intel_rps_client semaphores, mmioflips; |
1174 | 1143 | ||
1175 | /* manual wa residency calculations */ |
1144 | /* manual wa residency calculations */ |
1176 | struct intel_rps_ei ei; |
1145 | struct intel_rps_ei up_ei, down_ei; |
1177 | 1146 | ||
1178 | /* |
1147 | /* |
1179 | * Protects RPS/RC6 register access and PCU communication. |
1148 | * Protects RPS/RC6 register access and PCU communication. |
1180 | * Must be taken after struct_mutex if nested. Note that |
1149 | * Must be taken after struct_mutex if nested. Note that |
1181 | * this lock may be held for long periods of time when |
1150 | * this lock may be held for long periods of time when |
1182 | * talking to hw - so only take it when talking to hw! |
1151 | * talking to hw - so only take it when talking to hw! |
1183 | */ |
1152 | */ |
1184 | struct mutex hw_lock; |
1153 | struct mutex hw_lock; |
1185 | }; |
1154 | }; |
1186 | 1155 | ||
1187 | /* defined intel_pm.c */ |
1156 | /* defined intel_pm.c */ |
1188 | extern spinlock_t mchdev_lock; |
1157 | extern spinlock_t mchdev_lock; |
1189 | 1158 | ||
1190 | struct intel_ilk_power_mgmt { |
1159 | struct intel_ilk_power_mgmt { |
1191 | u8 cur_delay; |
1160 | u8 cur_delay; |
1192 | u8 min_delay; |
1161 | u8 min_delay; |
1193 | u8 max_delay; |
1162 | u8 max_delay; |
1194 | u8 fmax; |
1163 | u8 fmax; |
1195 | u8 fstart; |
1164 | u8 fstart; |
1196 | 1165 | ||
1197 | u64 last_count1; |
1166 | u64 last_count1; |
1198 | unsigned long last_time1; |
1167 | unsigned long last_time1; |
1199 | unsigned long chipset_power; |
1168 | unsigned long chipset_power; |
1200 | u64 last_count2; |
1169 | u64 last_count2; |
1201 | u64 last_time2; |
1170 | u64 last_time2; |
1202 | unsigned long gfx_power; |
1171 | unsigned long gfx_power; |
1203 | u8 corr; |
1172 | u8 corr; |
1204 | 1173 | ||
1205 | int c_m; |
1174 | int c_m; |
1206 | int r_t; |
1175 | int r_t; |
1207 | }; |
1176 | }; |
1208 | 1177 | ||
1209 | struct drm_i915_private; |
1178 | struct drm_i915_private; |
1210 | struct i915_power_well; |
1179 | struct i915_power_well; |
1211 | 1180 | ||
1212 | struct i915_power_well_ops { |
1181 | struct i915_power_well_ops { |
1213 | /* |
1182 | /* |
1214 | * Synchronize the well's hw state to match the current sw state, for |
1183 | * Synchronize the well's hw state to match the current sw state, for |
1215 | * example enable/disable it based on the current refcount. Called |
1184 | * example enable/disable it based on the current refcount. Called |
1216 | * during driver init and resume time, possibly after first calling |
1185 | * during driver init and resume time, possibly after first calling |
1217 | * the enable/disable handlers. |
1186 | * the enable/disable handlers. |
1218 | */ |
1187 | */ |
1219 | void (*sync_hw)(struct drm_i915_private *dev_priv, |
1188 | void (*sync_hw)(struct drm_i915_private *dev_priv, |
1220 | struct i915_power_well *power_well); |
1189 | struct i915_power_well *power_well); |
1221 | /* |
1190 | /* |
1222 | * Enable the well and resources that depend on it (for example |
1191 | * Enable the well and resources that depend on it (for example |
1223 | * interrupts located on the well). Called after the 0->1 refcount |
1192 | * interrupts located on the well). Called after the 0->1 refcount |
1224 | * transition. |
1193 | * transition. |
1225 | */ |
1194 | */ |
1226 | void (*enable)(struct drm_i915_private *dev_priv, |
1195 | void (*enable)(struct drm_i915_private *dev_priv, |
1227 | struct i915_power_well *power_well); |
1196 | struct i915_power_well *power_well); |
1228 | /* |
1197 | /* |
1229 | * Disable the well and resources that depend on it. Called after |
1198 | * Disable the well and resources that depend on it. Called after |
1230 | * the 1->0 refcount transition. |
1199 | * the 1->0 refcount transition. |
1231 | */ |
1200 | */ |
1232 | void (*disable)(struct drm_i915_private *dev_priv, |
1201 | void (*disable)(struct drm_i915_private *dev_priv, |
1233 | struct i915_power_well *power_well); |
1202 | struct i915_power_well *power_well); |
1234 | /* Returns the hw enabled state. */ |
1203 | /* Returns the hw enabled state. */ |
1235 | bool (*is_enabled)(struct drm_i915_private *dev_priv, |
1204 | bool (*is_enabled)(struct drm_i915_private *dev_priv, |
1236 | struct i915_power_well *power_well); |
1205 | struct i915_power_well *power_well); |
1237 | }; |
1206 | }; |
1238 | 1207 | ||
1239 | /* Power well structure for haswell */ |
1208 | /* Power well structure for haswell */ |
1240 | struct i915_power_well { |
1209 | struct i915_power_well { |
1241 | const char *name; |
1210 | const char *name; |
1242 | bool always_on; |
1211 | bool always_on; |
1243 | /* power well enable/disable usage count */ |
1212 | /* power well enable/disable usage count */ |
1244 | int count; |
1213 | int count; |
1245 | /* cached hw enabled state */ |
1214 | /* cached hw enabled state */ |
1246 | bool hw_enabled; |
1215 | bool hw_enabled; |
1247 | unsigned long domains; |
1216 | unsigned long domains; |
1248 | unsigned long data; |
1217 | unsigned long data; |
1249 | const struct i915_power_well_ops *ops; |
1218 | const struct i915_power_well_ops *ops; |
1250 | }; |
1219 | }; |
1251 | 1220 | ||
1252 | struct i915_power_domains { |
1221 | struct i915_power_domains { |
1253 | /* |
1222 | /* |
1254 | * Power wells needed for initialization at driver init and suspend |
1223 | * Power wells needed for initialization at driver init and suspend |
1255 | * time are on. They are kept on until after the first modeset. |
1224 | * time are on. They are kept on until after the first modeset. |
1256 | */ |
1225 | */ |
1257 | bool init_power_on; |
1226 | bool init_power_on; |
1258 | bool initializing; |
1227 | bool initializing; |
1259 | int power_well_count; |
1228 | int power_well_count; |
1260 | 1229 | ||
1261 | struct mutex lock; |
1230 | struct mutex lock; |
1262 | int domain_use_count[POWER_DOMAIN_NUM]; |
1231 | int domain_use_count[POWER_DOMAIN_NUM]; |
1263 | struct i915_power_well *power_wells; |
1232 | struct i915_power_well *power_wells; |
1264 | }; |
1233 | }; |
1265 | 1234 | ||
1266 | #define MAX_L3_SLICES 2 |
1235 | #define MAX_L3_SLICES 2 |
1267 | struct intel_l3_parity { |
1236 | struct intel_l3_parity { |
1268 | u32 *remap_info[MAX_L3_SLICES]; |
1237 | u32 *remap_info[MAX_L3_SLICES]; |
1269 | struct work_struct error_work; |
1238 | struct work_struct error_work; |
1270 | int which_slice; |
1239 | int which_slice; |
1271 | }; |
1240 | }; |
1272 | 1241 | ||
1273 | struct i915_gem_mm { |
1242 | struct i915_gem_mm { |
1274 | /** Memory allocator for GTT stolen memory */ |
1243 | /** Memory allocator for GTT stolen memory */ |
1275 | struct drm_mm stolen; |
1244 | struct drm_mm stolen; |
1276 | /** Protects the usage of the GTT stolen memory allocator. This is |
1245 | /** Protects the usage of the GTT stolen memory allocator. This is |
1277 | * always the inner lock when overlapping with struct_mutex. */ |
1246 | * always the inner lock when overlapping with struct_mutex. */ |
1278 | struct mutex stolen_lock; |
1247 | struct mutex stolen_lock; |
1279 | 1248 | ||
1280 | /** List of all objects in gtt_space. Used to restore gtt |
1249 | /** List of all objects in gtt_space. Used to restore gtt |
1281 | * mappings on resume */ |
1250 | * mappings on resume */ |
1282 | struct list_head bound_list; |
1251 | struct list_head bound_list; |
1283 | /** |
1252 | /** |
1284 | * List of objects which are not bound to the GTT (thus |
1253 | * List of objects which are not bound to the GTT (thus |
1285 | * are idle and not used by the GPU) but still have |
1254 | * are idle and not used by the GPU) but still have |
1286 | * (presumably uncached) pages still attached. |
1255 | * (presumably uncached) pages still attached. |
1287 | */ |
1256 | */ |
1288 | struct list_head unbound_list; |
1257 | struct list_head unbound_list; |
1289 | 1258 | ||
1290 | /** Usable portion of the GTT for GEM */ |
1259 | /** Usable portion of the GTT for GEM */ |
1291 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
1260 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
1292 | 1261 | ||
1293 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1262 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1294 | struct i915_hw_ppgtt *aliasing_ppgtt; |
1263 | struct i915_hw_ppgtt *aliasing_ppgtt; |
- | 1264 | ||
1295 | 1265 | struct notifier_block oom_notifier; |
|
1296 | /** LRU list of objects with fence regs on them. */ |
1266 | /** LRU list of objects with fence regs on them. */ |
1297 | struct list_head fence_list; |
1267 | struct list_head fence_list; |
1298 | 1268 | ||
1299 | /** |
1269 | /** |
1300 | * We leave the user IRQ off as much as possible, |
1270 | * We leave the user IRQ off as much as possible, |
1301 | * but this means that requests will finish and never |
1271 | * but this means that requests will finish and never |
1302 | * be retired once the system goes idle. Set a timer to |
1272 | * be retired once the system goes idle. Set a timer to |
1303 | * fire periodically while the ring is running. When it |
1273 | * fire periodically while the ring is running. When it |
1304 | * fires, go retire requests. |
1274 | * fires, go retire requests. |
1305 | */ |
1275 | */ |
1306 | struct delayed_work retire_work; |
1276 | struct delayed_work retire_work; |
1307 | 1277 | ||
1308 | /** |
1278 | /** |
1309 | * When we detect an idle GPU, we want to turn on |
1279 | * When we detect an idle GPU, we want to turn on |
1310 | * powersaving features. So once we see that there |
1280 | * powersaving features. So once we see that there |
1311 | * are no more requests outstanding and no more |
1281 | * are no more requests outstanding and no more |
1312 | * arrive within a small period of time, we fire |
1282 | * arrive within a small period of time, we fire |
1313 | * off the idle_work. |
1283 | * off the idle_work. |
1314 | */ |
1284 | */ |
1315 | struct delayed_work idle_work; |
1285 | struct delayed_work idle_work; |
1316 | 1286 | ||
1317 | /** |
1287 | /** |
1318 | * Are we in a non-interruptible section of code like |
1288 | * Are we in a non-interruptible section of code like |
1319 | * modesetting? |
1289 | * modesetting? |
1320 | */ |
1290 | */ |
1321 | bool interruptible; |
1291 | bool interruptible; |
1322 | 1292 | ||
1323 | /** |
1293 | /** |
1324 | * Is the GPU currently considered idle, or busy executing userspace |
1294 | * Is the GPU currently considered idle, or busy executing userspace |
1325 | * requests? Whilst idle, we attempt to power down the hardware and |
1295 | * requests? Whilst idle, we attempt to power down the hardware and |
1326 | * display clocks. In order to reduce the effect on performance, there |
1296 | * display clocks. In order to reduce the effect on performance, there |
1327 | * is a slight delay before we do so. |
1297 | * is a slight delay before we do so. |
1328 | */ |
1298 | */ |
1329 | bool busy; |
1299 | bool busy; |
1330 | 1300 | ||
1331 | /* the indicator for dispatch video commands on two BSD rings */ |
1301 | /* the indicator for dispatch video commands on two BSD rings */ |
1332 | int bsd_ring_dispatch_index; |
1302 | int bsd_ring_dispatch_index; |
1333 | 1303 | ||
1334 | /** Bit 6 swizzling required for X tiling */ |
1304 | /** Bit 6 swizzling required for X tiling */ |
1335 | uint32_t bit_6_swizzle_x; |
1305 | uint32_t bit_6_swizzle_x; |
1336 | /** Bit 6 swizzling required for Y tiling */ |
1306 | /** Bit 6 swizzling required for Y tiling */ |
1337 | uint32_t bit_6_swizzle_y; |
1307 | uint32_t bit_6_swizzle_y; |
1338 | 1308 | ||
1339 | /* accounting, useful for userland debugging */ |
1309 | /* accounting, useful for userland debugging */ |
1340 | spinlock_t object_stat_lock; |
1310 | spinlock_t object_stat_lock; |
1341 | size_t object_memory; |
1311 | size_t object_memory; |
1342 | u32 object_count; |
1312 | u32 object_count; |
1343 | }; |
1313 | }; |
1344 | 1314 | ||
1345 | struct drm_i915_error_state_buf { |
1315 | struct drm_i915_error_state_buf { |
1346 | struct drm_i915_private *i915; |
1316 | struct drm_i915_private *i915; |
1347 | unsigned bytes; |
1317 | unsigned bytes; |
1348 | unsigned size; |
1318 | unsigned size; |
1349 | int err; |
1319 | int err; |
1350 | u8 *buf; |
1320 | u8 *buf; |
1351 | loff_t start; |
1321 | loff_t start; |
1352 | loff_t pos; |
1322 | loff_t pos; |
1353 | }; |
1323 | }; |
1354 | 1324 | ||
1355 | struct i915_error_state_file_priv { |
1325 | struct i915_error_state_file_priv { |
1356 | struct drm_device *dev; |
1326 | struct drm_device *dev; |
1357 | struct drm_i915_error_state *error; |
1327 | struct drm_i915_error_state *error; |
1358 | }; |
1328 | }; |
1359 | 1329 | ||
1360 | struct i915_gpu_error { |
1330 | struct i915_gpu_error { |
1361 | /* For hangcheck timer */ |
1331 | /* For hangcheck timer */ |
1362 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
1332 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
1363 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
1333 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
1364 | /* Hang gpu twice in this window and your context gets banned */ |
1334 | /* Hang gpu twice in this window and your context gets banned */ |
1365 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
1335 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
1366 | 1336 | ||
1367 | struct workqueue_struct *hangcheck_wq; |
1337 | struct workqueue_struct *hangcheck_wq; |
1368 | struct delayed_work hangcheck_work; |
1338 | struct delayed_work hangcheck_work; |
1369 | 1339 | ||
1370 | /* For reset and error_state handling. */ |
1340 | /* For reset and error_state handling. */ |
1371 | spinlock_t lock; |
1341 | spinlock_t lock; |
1372 | /* Protected by the above dev->gpu_error.lock. */ |
1342 | /* Protected by the above dev->gpu_error.lock. */ |
1373 | struct drm_i915_error_state *first_error; |
1343 | struct drm_i915_error_state *first_error; |
1374 | 1344 | ||
1375 | unsigned long missed_irq_rings; |
1345 | unsigned long missed_irq_rings; |
1376 | 1346 | ||
1377 | /** |
1347 | /** |
1378 | * State variable controlling the reset flow and count |
1348 | * State variable controlling the reset flow and count |
1379 | * |
1349 | * |
1380 | * This is a counter which gets incremented when reset is triggered, |
1350 | * This is a counter which gets incremented when reset is triggered, |
1381 | * and again when reset has been handled. So odd values (lowest bit set) |
1351 | * and again when reset has been handled. So odd values (lowest bit set) |
1382 | * means that reset is in progress and even values that |
1352 | * means that reset is in progress and even values that |
1383 | * (reset_counter >> 1):th reset was successfully completed. |
1353 | * (reset_counter >> 1):th reset was successfully completed. |
1384 | * |
1354 | * |
1385 | * If reset is not completed succesfully, the I915_WEDGE bit is |
1355 | * If reset is not completed succesfully, the I915_WEDGE bit is |
1386 | * set meaning that hardware is terminally sour and there is no |
1356 | * set meaning that hardware is terminally sour and there is no |
1387 | * recovery. All waiters on the reset_queue will be woken when |
1357 | * recovery. All waiters on the reset_queue will be woken when |
1388 | * that happens. |
1358 | * that happens. |
1389 | * |
1359 | * |
1390 | * This counter is used by the wait_seqno code to notice that reset |
1360 | * This counter is used by the wait_seqno code to notice that reset |
1391 | * event happened and it needs to restart the entire ioctl (since most |
1361 | * event happened and it needs to restart the entire ioctl (since most |
1392 | * likely the seqno it waited for won't ever signal anytime soon). |
1362 | * likely the seqno it waited for won't ever signal anytime soon). |
1393 | * |
1363 | * |
1394 | * This is important for lock-free wait paths, where no contended lock |
1364 | * This is important for lock-free wait paths, where no contended lock |
1395 | * naturally enforces the correct ordering between the bail-out of the |
1365 | * naturally enforces the correct ordering between the bail-out of the |
1396 | * waiter and the gpu reset work code. |
1366 | * waiter and the gpu reset work code. |
1397 | */ |
1367 | */ |
1398 | atomic_t reset_counter; |
1368 | atomic_t reset_counter; |
1399 | 1369 | ||
1400 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
1370 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
1401 | #define I915_WEDGED (1 << 31) |
1371 | #define I915_WEDGED (1 << 31) |
1402 | 1372 | ||
1403 | /** |
1373 | /** |
1404 | * Waitqueue to signal when the reset has completed. Used by clients |
1374 | * Waitqueue to signal when the reset has completed. Used by clients |
1405 | * that wait for dev_priv->mm.wedged to settle. |
1375 | * that wait for dev_priv->mm.wedged to settle. |
1406 | */ |
1376 | */ |
1407 | wait_queue_head_t reset_queue; |
1377 | wait_queue_head_t reset_queue; |
1408 | 1378 | ||
1409 | /* Userspace knobs for gpu hang simulation; |
1379 | /* Userspace knobs for gpu hang simulation; |
1410 | * combines both a ring mask, and extra flags |
1380 | * combines both a ring mask, and extra flags |
1411 | */ |
1381 | */ |
1412 | u32 stop_rings; |
1382 | u32 stop_rings; |
1413 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) |
1383 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) |
1414 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) |
1384 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) |
1415 | 1385 | ||
1416 | /* For missed irq/seqno simulation. */ |
1386 | /* For missed irq/seqno simulation. */ |
1417 | unsigned int test_irq_rings; |
1387 | unsigned int test_irq_rings; |
1418 | 1388 | ||
1419 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
1389 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ |
1420 | bool reload_in_reset; |
1390 | bool reload_in_reset; |
1421 | }; |
1391 | }; |
1422 | 1392 | ||
1423 | enum modeset_restore { |
1393 | enum modeset_restore { |
1424 | MODESET_ON_LID_OPEN, |
1394 | MODESET_ON_LID_OPEN, |
1425 | MODESET_DONE, |
1395 | MODESET_DONE, |
1426 | MODESET_SUSPENDED, |
1396 | MODESET_SUSPENDED, |
1427 | }; |
1397 | }; |
1428 | 1398 | ||
1429 | #define DP_AUX_A 0x40 |
1399 | #define DP_AUX_A 0x40 |
1430 | #define DP_AUX_B 0x10 |
1400 | #define DP_AUX_B 0x10 |
1431 | #define DP_AUX_C 0x20 |
1401 | #define DP_AUX_C 0x20 |
1432 | #define DP_AUX_D 0x30 |
1402 | #define DP_AUX_D 0x30 |
1433 | 1403 | ||
1434 | #define DDC_PIN_B 0x05 |
1404 | #define DDC_PIN_B 0x05 |
1435 | #define DDC_PIN_C 0x04 |
1405 | #define DDC_PIN_C 0x04 |
1436 | #define DDC_PIN_D 0x06 |
1406 | #define DDC_PIN_D 0x06 |
1437 | 1407 | ||
1438 | struct ddi_vbt_port_info { |
1408 | struct ddi_vbt_port_info { |
1439 | /* |
1409 | /* |
1440 | * This is an index in the HDMI/DVI DDI buffer translation table. |
1410 | * This is an index in the HDMI/DVI DDI buffer translation table. |
1441 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't |
1411 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't |
1442 | * populate this field. |
1412 | * populate this field. |
1443 | */ |
1413 | */ |
1444 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff |
1414 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff |
1445 | uint8_t hdmi_level_shift; |
1415 | uint8_t hdmi_level_shift; |
1446 | 1416 | ||
1447 | uint8_t supports_dvi:1; |
1417 | uint8_t supports_dvi:1; |
1448 | uint8_t supports_hdmi:1; |
1418 | uint8_t supports_hdmi:1; |
1449 | uint8_t supports_dp:1; |
1419 | uint8_t supports_dp:1; |
1450 | 1420 | ||
1451 | uint8_t alternate_aux_channel; |
1421 | uint8_t alternate_aux_channel; |
1452 | uint8_t alternate_ddc_pin; |
1422 | uint8_t alternate_ddc_pin; |
1453 | 1423 | ||
1454 | uint8_t dp_boost_level; |
1424 | uint8_t dp_boost_level; |
1455 | uint8_t hdmi_boost_level; |
1425 | uint8_t hdmi_boost_level; |
1456 | }; |
1426 | }; |
1457 | 1427 | ||
1458 | enum psr_lines_to_wait { |
1428 | enum psr_lines_to_wait { |
1459 | PSR_0_LINES_TO_WAIT = 0, |
1429 | PSR_0_LINES_TO_WAIT = 0, |
1460 | PSR_1_LINE_TO_WAIT, |
1430 | PSR_1_LINE_TO_WAIT, |
1461 | PSR_4_LINES_TO_WAIT, |
1431 | PSR_4_LINES_TO_WAIT, |
1462 | PSR_8_LINES_TO_WAIT |
1432 | PSR_8_LINES_TO_WAIT |
1463 | }; |
1433 | }; |
1464 | 1434 | ||
1465 | struct intel_vbt_data { |
1435 | struct intel_vbt_data { |
1466 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
1436 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
1467 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
1437 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
1468 | 1438 | ||
1469 | /* Feature bits */ |
1439 | /* Feature bits */ |
1470 | unsigned int int_tv_support:1; |
1440 | unsigned int int_tv_support:1; |
1471 | unsigned int lvds_dither:1; |
1441 | unsigned int lvds_dither:1; |
1472 | unsigned int lvds_vbt:1; |
1442 | unsigned int lvds_vbt:1; |
1473 | unsigned int int_crt_support:1; |
1443 | unsigned int int_crt_support:1; |
1474 | unsigned int lvds_use_ssc:1; |
1444 | unsigned int lvds_use_ssc:1; |
1475 | unsigned int display_clock_mode:1; |
1445 | unsigned int display_clock_mode:1; |
1476 | unsigned int fdi_rx_polarity_inverted:1; |
1446 | unsigned int fdi_rx_polarity_inverted:1; |
1477 | unsigned int has_mipi:1; |
1447 | unsigned int has_mipi:1; |
1478 | int lvds_ssc_freq; |
1448 | int lvds_ssc_freq; |
1479 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
1449 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
1480 | 1450 | ||
1481 | enum drrs_support_type drrs_type; |
1451 | enum drrs_support_type drrs_type; |
1482 | 1452 | ||
1483 | /* eDP */ |
1453 | /* eDP */ |
1484 | int edp_rate; |
1454 | int edp_rate; |
1485 | int edp_lanes; |
1455 | int edp_lanes; |
1486 | int edp_preemphasis; |
1456 | int edp_preemphasis; |
1487 | int edp_vswing; |
1457 | int edp_vswing; |
1488 | bool edp_initialized; |
1458 | bool edp_initialized; |
1489 | bool edp_support; |
1459 | bool edp_support; |
1490 | int edp_bpp; |
1460 | int edp_bpp; |
1491 | struct edp_power_seq edp_pps; |
1461 | struct edp_power_seq edp_pps; |
1492 | 1462 | ||
1493 | struct { |
1463 | struct { |
1494 | bool full_link; |
1464 | bool full_link; |
1495 | bool require_aux_wakeup; |
1465 | bool require_aux_wakeup; |
1496 | int idle_frames; |
1466 | int idle_frames; |
1497 | enum psr_lines_to_wait lines_to_wait; |
1467 | enum psr_lines_to_wait lines_to_wait; |
1498 | int tp1_wakeup_time; |
1468 | int tp1_wakeup_time; |
1499 | int tp2_tp3_wakeup_time; |
1469 | int tp2_tp3_wakeup_time; |
1500 | } psr; |
1470 | } psr; |
1501 | 1471 | ||
1502 | struct { |
1472 | struct { |
1503 | u16 pwm_freq_hz; |
1473 | u16 pwm_freq_hz; |
1504 | bool present; |
1474 | bool present; |
1505 | bool active_low_pwm; |
1475 | bool active_low_pwm; |
1506 | u8 min_brightness; /* min_brightness/255 of max */ |
1476 | u8 min_brightness; /* min_brightness/255 of max */ |
1507 | } backlight; |
1477 | } backlight; |
1508 | 1478 | ||
1509 | /* MIPI DSI */ |
1479 | /* MIPI DSI */ |
1510 | struct { |
1480 | struct { |
1511 | u16 port; |
1481 | u16 port; |
1512 | u16 panel_id; |
1482 | u16 panel_id; |
1513 | struct mipi_config *config; |
1483 | struct mipi_config *config; |
1514 | struct mipi_pps_data *pps; |
1484 | struct mipi_pps_data *pps; |
1515 | u8 seq_version; |
1485 | u8 seq_version; |
1516 | u32 size; |
1486 | u32 size; |
1517 | u8 *data; |
1487 | u8 *data; |
1518 | u8 *sequence[MIPI_SEQ_MAX]; |
1488 | u8 *sequence[MIPI_SEQ_MAX]; |
1519 | } dsi; |
1489 | } dsi; |
1520 | 1490 | ||
1521 | int crt_ddc_pin; |
1491 | int crt_ddc_pin; |
1522 | 1492 | ||
1523 | int child_dev_num; |
1493 | int child_dev_num; |
1524 | union child_device_config *child_dev; |
1494 | union child_device_config *child_dev; |
1525 | 1495 | ||
1526 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
1496 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
1527 | }; |
1497 | }; |
1528 | 1498 | ||
1529 | enum intel_ddb_partitioning { |
1499 | enum intel_ddb_partitioning { |
1530 | INTEL_DDB_PART_1_2, |
1500 | INTEL_DDB_PART_1_2, |
1531 | INTEL_DDB_PART_5_6, /* IVB+ */ |
1501 | INTEL_DDB_PART_5_6, /* IVB+ */ |
1532 | }; |
1502 | }; |
1533 | 1503 | ||
1534 | struct intel_wm_level { |
1504 | struct intel_wm_level { |
1535 | bool enable; |
1505 | bool enable; |
1536 | uint32_t pri_val; |
1506 | uint32_t pri_val; |
1537 | uint32_t spr_val; |
1507 | uint32_t spr_val; |
1538 | uint32_t cur_val; |
1508 | uint32_t cur_val; |
1539 | uint32_t fbc_val; |
1509 | uint32_t fbc_val; |
1540 | }; |
1510 | }; |
1541 | 1511 | ||
1542 | struct ilk_wm_values { |
1512 | struct ilk_wm_values { |
1543 | uint32_t wm_pipe[3]; |
1513 | uint32_t wm_pipe[3]; |
1544 | uint32_t wm_lp[3]; |
1514 | uint32_t wm_lp[3]; |
1545 | uint32_t wm_lp_spr[3]; |
1515 | uint32_t wm_lp_spr[3]; |
1546 | uint32_t wm_linetime[3]; |
1516 | uint32_t wm_linetime[3]; |
1547 | bool enable_fbc_wm; |
1517 | bool enable_fbc_wm; |
1548 | enum intel_ddb_partitioning partitioning; |
1518 | enum intel_ddb_partitioning partitioning; |
1549 | }; |
1519 | }; |
1550 | 1520 | ||
1551 | struct vlv_pipe_wm { |
1521 | struct vlv_pipe_wm { |
1552 | uint16_t primary; |
1522 | uint16_t primary; |
1553 | uint16_t sprite[2]; |
1523 | uint16_t sprite[2]; |
1554 | uint8_t cursor; |
1524 | uint8_t cursor; |
1555 | }; |
1525 | }; |
1556 | 1526 | ||
1557 | struct vlv_sr_wm { |
1527 | struct vlv_sr_wm { |
1558 | uint16_t plane; |
1528 | uint16_t plane; |
1559 | uint8_t cursor; |
1529 | uint8_t cursor; |
1560 | }; |
1530 | }; |
1561 | 1531 | ||
1562 | struct vlv_wm_values { |
1532 | struct vlv_wm_values { |
1563 | struct vlv_pipe_wm pipe[3]; |
1533 | struct vlv_pipe_wm pipe[3]; |
1564 | struct vlv_sr_wm sr; |
1534 | struct vlv_sr_wm sr; |
1565 | struct { |
1535 | struct { |
1566 | uint8_t cursor; |
1536 | uint8_t cursor; |
1567 | uint8_t sprite[2]; |
1537 | uint8_t sprite[2]; |
1568 | uint8_t primary; |
1538 | uint8_t primary; |
1569 | } ddl[3]; |
1539 | } ddl[3]; |
1570 | uint8_t level; |
1540 | uint8_t level; |
1571 | bool cxsr; |
1541 | bool cxsr; |
1572 | }; |
1542 | }; |
1573 | 1543 | ||
1574 | struct skl_ddb_entry { |
1544 | struct skl_ddb_entry { |
1575 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
1545 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
1576 | }; |
1546 | }; |
1577 | 1547 | ||
1578 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) |
1548 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) |
1579 | { |
1549 | { |
1580 | return entry->end - entry->start; |
1550 | return entry->end - entry->start; |
1581 | } |
1551 | } |
1582 | 1552 | ||
1583 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1553 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1584 | const struct skl_ddb_entry *e2) |
1554 | const struct skl_ddb_entry *e2) |
1585 | { |
1555 | { |
1586 | if (e1->start == e2->start && e1->end == e2->end) |
1556 | if (e1->start == e2->start && e1->end == e2->end) |
1587 | return true; |
1557 | return true; |
1588 | 1558 | ||
1589 | return false; |
1559 | return false; |
1590 | } |
1560 | } |
1591 | 1561 | ||
1592 | struct skl_ddb_allocation { |
1562 | struct skl_ddb_allocation { |
1593 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
1563 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
1594 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
1564 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
1595 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
1565 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
1596 | }; |
1566 | }; |
1597 | 1567 | ||
1598 | struct skl_wm_values { |
1568 | struct skl_wm_values { |
1599 | bool dirty[I915_MAX_PIPES]; |
1569 | bool dirty[I915_MAX_PIPES]; |
1600 | struct skl_ddb_allocation ddb; |
1570 | struct skl_ddb_allocation ddb; |
1601 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1571 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1602 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; |
1572 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; |
1603 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
1573 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
1604 | }; |
1574 | }; |
1605 | 1575 | ||
1606 | struct skl_wm_level { |
1576 | struct skl_wm_level { |
1607 | bool plane_en[I915_MAX_PLANES]; |
1577 | bool plane_en[I915_MAX_PLANES]; |
1608 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1578 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1609 | uint8_t plane_res_l[I915_MAX_PLANES]; |
1579 | uint8_t plane_res_l[I915_MAX_PLANES]; |
1610 | }; |
1580 | }; |
1611 | 1581 | ||
1612 | /* |
1582 | /* |
1613 | * This struct helps tracking the state needed for runtime PM, which puts the |
1583 | * This struct helps tracking the state needed for runtime PM, which puts the |
1614 | * device in PCI D3 state. Notice that when this happens, nothing on the |
1584 | * device in PCI D3 state. Notice that when this happens, nothing on the |
1615 | * graphics device works, even register access, so we don't get interrupts nor |
1585 | * graphics device works, even register access, so we don't get interrupts nor |
1616 | * anything else. |
1586 | * anything else. |
1617 | * |
1587 | * |
1618 | * Every piece of our code that needs to actually touch the hardware needs to |
1588 | * Every piece of our code that needs to actually touch the hardware needs to |
1619 | * either call intel_runtime_pm_get or call intel_display_power_get with the |
1589 | * either call intel_runtime_pm_get or call intel_display_power_get with the |
1620 | * appropriate power domain. |
1590 | * appropriate power domain. |
1621 | * |
1591 | * |
1622 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1592 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1623 | * suspend if we stay with zero refcount for a certain amount of time. The |
1593 | * suspend if we stay with zero refcount for a certain amount of time. The |
1624 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
1594 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
1625 | * it can be changed with the standard runtime PM files from sysfs. |
1595 | * it can be changed with the standard runtime PM files from sysfs. |
1626 | * |
1596 | * |
1627 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
1597 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
1628 | * goes back to false exactly before we reenable the IRQs. We use this variable |
1598 | * goes back to false exactly before we reenable the IRQs. We use this variable |
1629 | * to check if someone is trying to enable/disable IRQs while they're supposed |
1599 | * to check if someone is trying to enable/disable IRQs while they're supposed |
1630 | * to be disabled. This shouldn't happen and we'll print some error messages in |
1600 | * to be disabled. This shouldn't happen and we'll print some error messages in |
1631 | * case it happens. |
1601 | * case it happens. |
1632 | * |
1602 | * |
1633 | * For more, read the Documentation/power/runtime_pm.txt. |
1603 | * For more, read the Documentation/power/runtime_pm.txt. |
1634 | */ |
1604 | */ |
1635 | struct i915_runtime_pm { |
1605 | struct i915_runtime_pm { |
- | 1606 | atomic_t wakeref_count; |
|
- | 1607 | atomic_t atomic_seq; |
|
1636 | bool suspended; |
1608 | bool suspended; |
1637 | bool irqs_enabled; |
1609 | bool irqs_enabled; |
1638 | }; |
1610 | }; |
1639 | 1611 | ||
1640 | enum intel_pipe_crc_source { |
1612 | enum intel_pipe_crc_source { |
1641 | INTEL_PIPE_CRC_SOURCE_NONE, |
1613 | INTEL_PIPE_CRC_SOURCE_NONE, |
1642 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
1614 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
1643 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
1615 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
1644 | INTEL_PIPE_CRC_SOURCE_PF, |
1616 | INTEL_PIPE_CRC_SOURCE_PF, |
1645 | INTEL_PIPE_CRC_SOURCE_PIPE, |
1617 | INTEL_PIPE_CRC_SOURCE_PIPE, |
1646 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1618 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1647 | INTEL_PIPE_CRC_SOURCE_TV, |
1619 | INTEL_PIPE_CRC_SOURCE_TV, |
1648 | INTEL_PIPE_CRC_SOURCE_DP_B, |
1620 | INTEL_PIPE_CRC_SOURCE_DP_B, |
1649 | INTEL_PIPE_CRC_SOURCE_DP_C, |
1621 | INTEL_PIPE_CRC_SOURCE_DP_C, |
1650 | INTEL_PIPE_CRC_SOURCE_DP_D, |
1622 | INTEL_PIPE_CRC_SOURCE_DP_D, |
1651 | INTEL_PIPE_CRC_SOURCE_AUTO, |
1623 | INTEL_PIPE_CRC_SOURCE_AUTO, |
1652 | INTEL_PIPE_CRC_SOURCE_MAX, |
1624 | INTEL_PIPE_CRC_SOURCE_MAX, |
1653 | }; |
1625 | }; |
1654 | 1626 | ||
1655 | struct intel_pipe_crc_entry { |
1627 | struct intel_pipe_crc_entry { |
1656 | uint32_t frame; |
1628 | uint32_t frame; |
1657 | uint32_t crc[5]; |
1629 | uint32_t crc[5]; |
1658 | }; |
1630 | }; |
1659 | 1631 | ||
1660 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
1632 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
1661 | struct intel_pipe_crc { |
1633 | struct intel_pipe_crc { |
1662 | spinlock_t lock; |
1634 | spinlock_t lock; |
1663 | bool opened; /* exclusive access to the result file */ |
1635 | bool opened; /* exclusive access to the result file */ |
1664 | struct intel_pipe_crc_entry *entries; |
1636 | struct intel_pipe_crc_entry *entries; |
1665 | enum intel_pipe_crc_source source; |
1637 | enum intel_pipe_crc_source source; |
1666 | int head, tail; |
1638 | int head, tail; |
1667 | wait_queue_head_t wq; |
1639 | wait_queue_head_t wq; |
1668 | }; |
1640 | }; |
1669 | 1641 | ||
1670 | struct i915_frontbuffer_tracking { |
1642 | struct i915_frontbuffer_tracking { |
1671 | struct mutex lock; |
1643 | struct mutex lock; |
1672 | 1644 | ||
1673 | /* |
1645 | /* |
1674 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or |
1646 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or |
1675 | * scheduled flips. |
1647 | * scheduled flips. |
1676 | */ |
1648 | */ |
1677 | unsigned busy_bits; |
1649 | unsigned busy_bits; |
1678 | unsigned flip_bits; |
1650 | unsigned flip_bits; |
1679 | }; |
1651 | }; |
1680 | 1652 | ||
1681 | struct i915_wa_reg { |
1653 | struct i915_wa_reg { |
1682 | u32 addr; |
1654 | i915_reg_t addr; |
1683 | u32 value; |
1655 | u32 value; |
1684 | /* bitmask representing WA bits */ |
1656 | /* bitmask representing WA bits */ |
1685 | u32 mask; |
1657 | u32 mask; |
1686 | }; |
1658 | }; |
1687 | 1659 | ||
1688 | #define I915_MAX_WA_REGS 16 |
1660 | #define I915_MAX_WA_REGS 16 |
1689 | 1661 | ||
1690 | struct i915_workarounds { |
1662 | struct i915_workarounds { |
1691 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; |
1663 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; |
1692 | u32 count; |
1664 | u32 count; |
1693 | }; |
1665 | }; |
1694 | 1666 | ||
1695 | struct i915_virtual_gpu { |
1667 | struct i915_virtual_gpu { |
1696 | bool active; |
1668 | bool active; |
1697 | }; |
1669 | }; |
1698 | 1670 | ||
1699 | struct i915_execbuffer_params { |
1671 | struct i915_execbuffer_params { |
1700 | struct drm_device *dev; |
1672 | struct drm_device *dev; |
1701 | struct drm_file *file; |
1673 | struct drm_file *file; |
1702 | uint32_t dispatch_flags; |
1674 | uint32_t dispatch_flags; |
1703 | uint32_t args_batch_start_offset; |
1675 | uint32_t args_batch_start_offset; |
1704 | uint64_t batch_obj_vm_offset; |
1676 | uint64_t batch_obj_vm_offset; |
1705 | struct intel_engine_cs *ring; |
1677 | struct intel_engine_cs *ring; |
1706 | struct drm_i915_gem_object *batch_obj; |
1678 | struct drm_i915_gem_object *batch_obj; |
1707 | struct intel_context *ctx; |
1679 | struct intel_context *ctx; |
1708 | struct drm_i915_gem_request *request; |
1680 | struct drm_i915_gem_request *request; |
1709 | }; |
1681 | }; |
- | 1682 | ||
- | 1683 | /* used in computing the new watermarks state */ |
|
- | 1684 | struct intel_wm_config { |
|
- | 1685 | unsigned int num_pipes_active; |
|
- | 1686 | bool sprites_enabled; |
|
- | 1687 | bool sprites_scaled; |
|
- | 1688 | }; |
|
1710 | 1689 | ||
1711 | struct drm_i915_private { |
1690 | struct drm_i915_private { |
1712 | struct drm_device *dev; |
1691 | struct drm_device *dev; |
1713 | struct kmem_cache *objects; |
1692 | struct kmem_cache *objects; |
1714 | struct kmem_cache *vmas; |
1693 | struct kmem_cache *vmas; |
1715 | struct kmem_cache *requests; |
1694 | struct kmem_cache *requests; |
1716 | 1695 | ||
1717 | const struct intel_device_info info; |
1696 | const struct intel_device_info info; |
1718 | 1697 | ||
1719 | int relative_constants_mode; |
1698 | int relative_constants_mode; |
1720 | 1699 | ||
1721 | void __iomem *regs; |
1700 | void __iomem *regs; |
1722 | 1701 | ||
1723 | struct intel_uncore uncore; |
1702 | struct intel_uncore uncore; |
1724 | 1703 | ||
1725 | struct i915_virtual_gpu vgpu; |
1704 | struct i915_virtual_gpu vgpu; |
1726 | 1705 | ||
1727 | struct intel_guc guc; |
1706 | struct intel_guc guc; |
1728 | 1707 | ||
1729 | struct intel_csr csr; |
1708 | struct intel_csr csr; |
1730 | - | ||
1731 | /* Display CSR-related protection */ |
- | |
1732 | struct mutex csr_lock; |
- | |
1733 | 1709 | ||
1734 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
1710 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
1735 | 1711 | ||
1736 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1712 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1737 | * controller on different i2c buses. */ |
1713 | * controller on different i2c buses. */ |
1738 | struct mutex gmbus_mutex; |
1714 | struct mutex gmbus_mutex; |
1739 | 1715 | ||
1740 | /** |
1716 | /** |
1741 | * Base address of the gmbus and gpio block. |
1717 | * Base address of the gmbus and gpio block. |
1742 | */ |
1718 | */ |
1743 | uint32_t gpio_mmio_base; |
1719 | uint32_t gpio_mmio_base; |
1744 | 1720 | ||
1745 | /* MMIO base address for MIPI regs */ |
1721 | /* MMIO base address for MIPI regs */ |
1746 | uint32_t mipi_mmio_base; |
1722 | uint32_t mipi_mmio_base; |
- | 1723 | ||
- | 1724 | uint32_t psr_mmio_base; |
|
1747 | 1725 | ||
1748 | wait_queue_head_t gmbus_wait_queue; |
1726 | wait_queue_head_t gmbus_wait_queue; |
1749 | 1727 | ||
1750 | struct pci_dev *bridge_dev; |
1728 | struct pci_dev *bridge_dev; |
1751 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
1729 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
1752 | struct drm_i915_gem_object *semaphore_obj; |
1730 | struct drm_i915_gem_object *semaphore_obj; |
1753 | uint32_t last_seqno, next_seqno; |
1731 | uint32_t last_seqno, next_seqno; |
1754 | 1732 | ||
1755 | struct drm_dma_handle *status_page_dmah; |
1733 | struct drm_dma_handle *status_page_dmah; |
1756 | struct resource mch_res; |
1734 | struct resource mch_res; |
1757 | 1735 | ||
1758 | /* protects the irq masks */ |
1736 | /* protects the irq masks */ |
1759 | spinlock_t irq_lock; |
1737 | spinlock_t irq_lock; |
1760 | 1738 | ||
1761 | /* protects the mmio flip data */ |
1739 | /* protects the mmio flip data */ |
1762 | spinlock_t mmio_flip_lock; |
1740 | spinlock_t mmio_flip_lock; |
1763 | 1741 | ||
1764 | bool display_irqs_enabled; |
1742 | bool display_irqs_enabled; |
1765 | 1743 | ||
1766 | 1744 | ||
1767 | /* Sideband mailbox protection */ |
1745 | /* Sideband mailbox protection */ |
1768 | struct mutex sb_lock; |
1746 | struct mutex sb_lock; |
1769 | 1747 | ||
1770 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
1748 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
1771 | union { |
1749 | union { |
1772 | u32 irq_mask; |
1750 | u32 irq_mask; |
1773 | u32 de_irq_mask[I915_MAX_PIPES]; |
1751 | u32 de_irq_mask[I915_MAX_PIPES]; |
1774 | }; |
1752 | }; |
1775 | u32 gt_irq_mask; |
1753 | u32 gt_irq_mask; |
1776 | u32 pm_irq_mask; |
1754 | u32 pm_irq_mask; |
1777 | u32 pm_rps_events; |
1755 | u32 pm_rps_events; |
1778 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
1756 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
1779 | 1757 | ||
1780 | struct i915_hotplug hotplug; |
1758 | struct i915_hotplug hotplug; |
1781 | struct i915_fbc fbc; |
1759 | struct i915_fbc fbc; |
1782 | struct i915_drrs drrs; |
1760 | struct i915_drrs drrs; |
1783 | struct intel_opregion opregion; |
1761 | struct intel_opregion opregion; |
1784 | struct intel_vbt_data vbt; |
1762 | struct intel_vbt_data vbt; |
1785 | 1763 | ||
1786 | bool preserve_bios_swizzle; |
1764 | bool preserve_bios_swizzle; |
1787 | 1765 | ||
1788 | /* overlay */ |
1766 | /* overlay */ |
1789 | struct intel_overlay *overlay; |
1767 | struct intel_overlay *overlay; |
1790 | 1768 | ||
1791 | /* backlight registers and fields in struct intel_panel */ |
1769 | /* backlight registers and fields in struct intel_panel */ |
1792 | struct mutex backlight_lock; |
1770 | struct mutex backlight_lock; |
1793 | 1771 | ||
1794 | /* LVDS info */ |
1772 | /* LVDS info */ |
1795 | bool no_aux_handshake; |
1773 | bool no_aux_handshake; |
1796 | 1774 | ||
1797 | /* protects panel power sequencer state */ |
1775 | /* protects panel power sequencer state */ |
1798 | struct mutex pps_mutex; |
1776 | struct mutex pps_mutex; |
1799 | 1777 | ||
1800 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1778 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1801 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1779 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1802 | 1780 | ||
1803 | unsigned int fsb_freq, mem_freq, is_ddr3; |
1781 | unsigned int fsb_freq, mem_freq, is_ddr3; |
1804 | unsigned int skl_boot_cdclk; |
1782 | unsigned int skl_boot_cdclk; |
1805 | unsigned int cdclk_freq, max_cdclk_freq; |
1783 | unsigned int cdclk_freq, max_cdclk_freq; |
1806 | unsigned int max_dotclk_freq; |
1784 | unsigned int max_dotclk_freq; |
1807 | unsigned int hpll_freq; |
1785 | unsigned int hpll_freq; |
1808 | unsigned int czclk_freq; |
1786 | unsigned int czclk_freq; |
1809 | 1787 | ||
1810 | /** |
1788 | /** |
1811 | * wq - Driver workqueue for GEM. |
1789 | * wq - Driver workqueue for GEM. |
1812 | * |
1790 | * |
1813 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
1791 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
1814 | * locks, for otherwise the flushing done in the pageflip code will |
1792 | * locks, for otherwise the flushing done in the pageflip code will |
1815 | * result in deadlocks. |
1793 | * result in deadlocks. |
1816 | */ |
1794 | */ |
1817 | struct workqueue_struct *wq; |
1795 | struct workqueue_struct *wq; |
1818 | 1796 | ||
1819 | /* Display functions */ |
1797 | /* Display functions */ |
1820 | struct drm_i915_display_funcs display; |
1798 | struct drm_i915_display_funcs display; |
1821 | 1799 | ||
1822 | /* PCH chipset type */ |
1800 | /* PCH chipset type */ |
1823 | enum intel_pch pch_type; |
1801 | enum intel_pch pch_type; |
1824 | unsigned short pch_id; |
1802 | unsigned short pch_id; |
1825 | 1803 | ||
1826 | unsigned long quirks; |
1804 | unsigned long quirks; |
1827 | 1805 | ||
1828 | enum modeset_restore modeset_restore; |
1806 | enum modeset_restore modeset_restore; |
1829 | struct mutex modeset_restore_lock; |
1807 | struct mutex modeset_restore_lock; |
1830 | 1808 | ||
1831 | struct list_head vm_list; /* Global list of all address spaces */ |
1809 | struct list_head vm_list; /* Global list of all address spaces */ |
1832 | struct i915_gtt gtt; /* VM representing the global address space */ |
1810 | struct i915_gtt gtt; /* VM representing the global address space */ |
1833 | 1811 | ||
1834 | struct i915_gem_mm mm; |
1812 | struct i915_gem_mm mm; |
1835 | DECLARE_HASHTABLE(mm_structs, 7); |
1813 | DECLARE_HASHTABLE(mm_structs, 7); |
1836 | struct mutex mm_lock; |
1814 | struct mutex mm_lock; |
1837 | 1815 | ||
1838 | /* Kernel Modesetting */ |
1816 | /* Kernel Modesetting */ |
1839 | 1817 | ||
1840 | struct sdvo_device_mapping sdvo_mappings[2]; |
1818 | struct sdvo_device_mapping sdvo_mappings[2]; |
1841 | 1819 | ||
1842 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1820 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1843 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; |
1821 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; |
1844 | wait_queue_head_t pending_flip_queue; |
1822 | wait_queue_head_t pending_flip_queue; |
1845 | 1823 | ||
1846 | #ifdef CONFIG_DEBUG_FS |
1824 | #ifdef CONFIG_DEBUG_FS |
1847 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
1825 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
1848 | #endif |
1826 | #endif |
1849 | 1827 | ||
1850 | int num_shared_dpll; |
1828 | int num_shared_dpll; |
1851 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
1829 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
1852 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
1830 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
1853 | 1831 | ||
1854 | struct i915_workarounds workarounds; |
1832 | struct i915_workarounds workarounds; |
1855 | 1833 | ||
1856 | /* Reclocking support */ |
1834 | /* Reclocking support */ |
1857 | bool render_reclock_avail; |
1835 | bool render_reclock_avail; |
1858 | 1836 | ||
1859 | struct i915_frontbuffer_tracking fb_tracking; |
1837 | struct i915_frontbuffer_tracking fb_tracking; |
1860 | 1838 | ||
1861 | u16 orig_clock; |
1839 | u16 orig_clock; |
1862 | 1840 | ||
1863 | bool mchbar_need_disable; |
1841 | bool mchbar_need_disable; |
1864 | 1842 | ||
1865 | struct intel_l3_parity l3_parity; |
1843 | struct intel_l3_parity l3_parity; |
1866 | 1844 | ||
1867 | /* Cannot be determined by PCIID. You must always read a register. */ |
1845 | /* Cannot be determined by PCIID. You must always read a register. */ |
1868 | size_t ellc_size; |
1846 | size_t ellc_size; |
1869 | 1847 | ||
1870 | /* gen6+ rps state */ |
1848 | /* gen6+ rps state */ |
1871 | struct intel_gen6_power_mgmt rps; |
1849 | struct intel_gen6_power_mgmt rps; |
1872 | 1850 | ||
1873 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1851 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1874 | * mchdev_lock in intel_pm.c */ |
1852 | * mchdev_lock in intel_pm.c */ |
1875 | struct intel_ilk_power_mgmt ips; |
1853 | struct intel_ilk_power_mgmt ips; |
1876 | 1854 | ||
1877 | struct i915_power_domains power_domains; |
1855 | struct i915_power_domains power_domains; |
1878 | 1856 | ||
1879 | struct i915_psr psr; |
1857 | struct i915_psr psr; |
1880 | 1858 | ||
1881 | struct i915_gpu_error gpu_error; |
1859 | struct i915_gpu_error gpu_error; |
1882 | 1860 | ||
1883 | struct drm_i915_gem_object *vlv_pctx; |
1861 | struct drm_i915_gem_object *vlv_pctx; |
1884 | 1862 | ||
1885 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
1863 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
1886 | /* list of fbdev register on this device */ |
1864 | /* list of fbdev register on this device */ |
1887 | struct intel_fbdev *fbdev; |
1865 | struct intel_fbdev *fbdev; |
1888 | struct work_struct fbdev_suspend_work; |
1866 | struct work_struct fbdev_suspend_work; |
1889 | #endif |
1867 | #endif |
1890 | 1868 | ||
1891 | struct drm_property *broadcast_rgb_property; |
1869 | struct drm_property *broadcast_rgb_property; |
1892 | struct drm_property *force_audio_property; |
1870 | struct drm_property *force_audio_property; |
1893 | 1871 | ||
1894 | /* hda/i915 audio component */ |
1872 | /* hda/i915 audio component */ |
1895 | struct i915_audio_component *audio_component; |
1873 | struct i915_audio_component *audio_component; |
1896 | bool audio_component_registered; |
1874 | bool audio_component_registered; |
1897 | /** |
1875 | /** |
1898 | * av_mutex - mutex for audio/video sync |
1876 | * av_mutex - mutex for audio/video sync |
1899 | * |
1877 | * |
1900 | */ |
1878 | */ |
1901 | struct mutex av_mutex; |
1879 | struct mutex av_mutex; |
1902 | 1880 | ||
1903 | uint32_t hw_context_size; |
1881 | uint32_t hw_context_size; |
1904 | struct list_head context_list; |
1882 | struct list_head context_list; |
1905 | 1883 | ||
1906 | u32 fdi_rx_config; |
1884 | u32 fdi_rx_config; |
1907 | 1885 | ||
1908 | u32 chv_phy_control; |
1886 | u32 chv_phy_control; |
1909 | 1887 | ||
1910 | u32 suspend_count; |
1888 | u32 suspend_count; |
- | 1889 | bool suspended_to_idle; |
|
1911 | struct i915_suspend_saved_registers regfile; |
1890 | struct i915_suspend_saved_registers regfile; |
1912 | struct vlv_s0ix_state vlv_s0ix_state; |
1891 | struct vlv_s0ix_state vlv_s0ix_state; |
1913 | 1892 | ||
1914 | struct { |
1893 | struct { |
1915 | /* |
1894 | /* |
1916 | * Raw watermark latency values: |
1895 | * Raw watermark latency values: |
1917 | * in 0.1us units for WM0, |
1896 | * in 0.1us units for WM0, |
1918 | * in 0.5us units for WM1+. |
1897 | * in 0.5us units for WM1+. |
1919 | */ |
1898 | */ |
1920 | /* primary */ |
1899 | /* primary */ |
1921 | uint16_t pri_latency[5]; |
1900 | uint16_t pri_latency[5]; |
1922 | /* sprite */ |
1901 | /* sprite */ |
1923 | uint16_t spr_latency[5]; |
1902 | uint16_t spr_latency[5]; |
1924 | /* cursor */ |
1903 | /* cursor */ |
1925 | uint16_t cur_latency[5]; |
1904 | uint16_t cur_latency[5]; |
1926 | /* |
1905 | /* |
1927 | * Raw watermark memory latency values |
1906 | * Raw watermark memory latency values |
1928 | * for SKL for all 8 levels |
1907 | * for SKL for all 8 levels |
1929 | * in 1us units. |
1908 | * in 1us units. |
1930 | */ |
1909 | */ |
1931 | uint16_t skl_latency[8]; |
1910 | uint16_t skl_latency[8]; |
- | 1911 | ||
- | 1912 | /* Committed wm config */ |
|
- | 1913 | struct intel_wm_config config; |
|
1932 | 1914 | ||
1933 | /* |
1915 | /* |
1934 | * The skl_wm_values structure is a bit too big for stack |
1916 | * The skl_wm_values structure is a bit too big for stack |
1935 | * allocation, so we keep the staging struct where we store |
1917 | * allocation, so we keep the staging struct where we store |
1936 | * intermediate results here instead. |
1918 | * intermediate results here instead. |
1937 | */ |
1919 | */ |
1938 | struct skl_wm_values skl_results; |
1920 | struct skl_wm_values skl_results; |
1939 | 1921 | ||
1940 | /* current hardware state */ |
1922 | /* current hardware state */ |
1941 | union { |
1923 | union { |
1942 | struct ilk_wm_values hw; |
1924 | struct ilk_wm_values hw; |
1943 | struct skl_wm_values skl_hw; |
1925 | struct skl_wm_values skl_hw; |
1944 | struct vlv_wm_values vlv; |
1926 | struct vlv_wm_values vlv; |
1945 | }; |
1927 | }; |
1946 | 1928 | ||
1947 | uint8_t max_level; |
1929 | uint8_t max_level; |
1948 | } wm; |
1930 | } wm; |
1949 | 1931 | ||
1950 | struct i915_runtime_pm pm; |
1932 | struct i915_runtime_pm pm; |
1951 | 1933 | ||
1952 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1934 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1953 | struct { |
1935 | struct { |
1954 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
1936 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
1955 | struct drm_i915_gem_execbuffer2 *args, |
1937 | struct drm_i915_gem_execbuffer2 *args, |
1956 | struct list_head *vmas); |
1938 | struct list_head *vmas); |
1957 | int (*init_rings)(struct drm_device *dev); |
1939 | int (*init_rings)(struct drm_device *dev); |
1958 | void (*cleanup_ring)(struct intel_engine_cs *ring); |
1940 | void (*cleanup_ring)(struct intel_engine_cs *ring); |
1959 | void (*stop_ring)(struct intel_engine_cs *ring); |
1941 | void (*stop_ring)(struct intel_engine_cs *ring); |
1960 | } gt; |
1942 | } gt; |
1961 | 1943 | ||
1962 | bool edp_low_vswing; |
1944 | bool edp_low_vswing; |
1963 | 1945 | ||
1964 | /* perform PHY state sanity checks? */ |
1946 | /* perform PHY state sanity checks? */ |
1965 | bool chv_phy_assert[2]; |
1947 | bool chv_phy_assert[2]; |
- | 1948 | ||
- | 1949 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; |
|
1966 | 1950 | ||
1967 | /* |
1951 | /* |
1968 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
1952 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch |
1969 | * will be rejected. Instead look for a better place. |
1953 | * will be rejected. Instead look for a better place. |
1970 | */ |
1954 | */ |
1971 | }; |
1955 | }; |
1972 | 1956 | ||
1973 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1957 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1974 | { |
1958 | { |
1975 | return dev->dev_private; |
1959 | return dev->dev_private; |
1976 | } |
1960 | } |
1977 | 1961 | ||
1978 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1962 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1979 | { |
1963 | { |
1980 | return to_i915(dev_get_drvdata(dev)); |
1964 | return to_i915(dev_get_drvdata(dev)); |
1981 | } |
1965 | } |
1982 | 1966 | ||
1983 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1967 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1984 | { |
1968 | { |
1985 | return container_of(guc, struct drm_i915_private, guc); |
1969 | return container_of(guc, struct drm_i915_private, guc); |
1986 | } |
1970 | } |
1987 | 1971 | ||
1988 | /* Iterate over initialised rings */ |
1972 | /* Iterate over initialised rings */ |
1989 | #define for_each_ring(ring__, dev_priv__, i__) \ |
1973 | #define for_each_ring(ring__, dev_priv__, i__) \ |
1990 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
1974 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
1991 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
1975 | for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))) |
1992 | 1976 | ||
1993 | enum hdmi_force_audio { |
1977 | enum hdmi_force_audio { |
1994 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
1978 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
1995 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
1979 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
1996 | HDMI_AUDIO_AUTO, /* trust EDID */ |
1980 | HDMI_AUDIO_AUTO, /* trust EDID */ |
1997 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
1981 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
1998 | }; |
1982 | }; |
1999 | 1983 | ||
2000 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
1984 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
2001 | 1985 | ||
2002 | struct drm_i915_gem_object_ops { |
1986 | struct drm_i915_gem_object_ops { |
- | 1987 | unsigned int flags; |
|
- | 1988 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 |
|
- | 1989 | ||
2003 | /* Interface between the GEM object and its backing storage. |
1990 | /* Interface between the GEM object and its backing storage. |
2004 | * get_pages() is called once prior to the use of the associated set |
1991 | * get_pages() is called once prior to the use of the associated set |
2005 | * of pages before to binding them into the GTT, and put_pages() is |
1992 | * of pages before to binding them into the GTT, and put_pages() is |
2006 | * called after we no longer need them. As we expect there to be |
1993 | * called after we no longer need them. As we expect there to be |
2007 | * associated cost with migrating pages between the backing storage |
1994 | * associated cost with migrating pages between the backing storage |
2008 | * and making them available for the GPU (e.g. clflush), we may hold |
1995 | * and making them available for the GPU (e.g. clflush), we may hold |
2009 | * onto the pages after they are no longer referenced by the GPU |
1996 | * onto the pages after they are no longer referenced by the GPU |
2010 | * in case they may be used again shortly (for example migrating the |
1997 | * in case they may be used again shortly (for example migrating the |
2011 | * pages to a different memory domain within the GTT). put_pages() |
1998 | * pages to a different memory domain within the GTT). put_pages() |
2012 | * will therefore most likely be called when the object itself is |
1999 | * will therefore most likely be called when the object itself is |
2013 | * being released or under memory pressure (where we attempt to |
2000 | * being released or under memory pressure (where we attempt to |
2014 | * reap pages for the shrinker). |
2001 | * reap pages for the shrinker). |
2015 | */ |
2002 | */ |
2016 | int (*get_pages)(struct drm_i915_gem_object *); |
2003 | int (*get_pages)(struct drm_i915_gem_object *); |
2017 | void (*put_pages)(struct drm_i915_gem_object *); |
2004 | void (*put_pages)(struct drm_i915_gem_object *); |
- | 2005 | ||
2018 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2006 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2019 | void (*release)(struct drm_i915_gem_object *); |
2007 | void (*release)(struct drm_i915_gem_object *); |
2020 | }; |
2008 | }; |
2021 | 2009 | ||
2022 | /* |
2010 | /* |
2023 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is |
2011 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is |
2024 | * considered to be the frontbuffer for the given plane interface-wise. This |
2012 | * considered to be the frontbuffer for the given plane interface-wise. This |
2025 | * doesn't mean that the hw necessarily already scans it out, but that any |
2013 | * doesn't mean that the hw necessarily already scans it out, but that any |
2026 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. |
2014 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. |
2027 | * |
2015 | * |
2028 | * We have one bit per pipe and per scanout plane type. |
2016 | * We have one bit per pipe and per scanout plane type. |
2029 | */ |
2017 | */ |
2030 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2018 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2031 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 |
2019 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 |
2032 | #define INTEL_FRONTBUFFER_BITS \ |
2020 | #define INTEL_FRONTBUFFER_BITS \ |
2033 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) |
2021 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) |
2034 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2022 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2035 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
2023 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
2036 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ |
2024 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ |
2037 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2025 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2038 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ |
2026 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ |
2039 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2027 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2040 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
2028 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
2041 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2029 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2042 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
2030 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
2043 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
2031 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
2044 | 2032 | ||
2045 | struct drm_i915_gem_object { |
2033 | struct drm_i915_gem_object { |
2046 | struct drm_gem_object base; |
2034 | struct drm_gem_object base; |
2047 | 2035 | ||
2048 | const struct drm_i915_gem_object_ops *ops; |
2036 | const struct drm_i915_gem_object_ops *ops; |
2049 | 2037 | ||
2050 | /** List of VMAs backed by this object */ |
2038 | /** List of VMAs backed by this object */ |
2051 | struct list_head vma_list; |
2039 | struct list_head vma_list; |
2052 | 2040 | ||
2053 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2041 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2054 | struct drm_mm_node *stolen; |
2042 | struct drm_mm_node *stolen; |
2055 | struct list_head global_list; |
2043 | struct list_head global_list; |
2056 | 2044 | ||
2057 | struct list_head ring_list[I915_NUM_RINGS]; |
2045 | struct list_head ring_list[I915_NUM_RINGS]; |
2058 | /** Used in execbuf to temporarily hold a ref */ |
2046 | /** Used in execbuf to temporarily hold a ref */ |
2059 | struct list_head obj_exec_link; |
2047 | struct list_head obj_exec_link; |
2060 | 2048 | ||
2061 | struct list_head batch_pool_link; |
2049 | struct list_head batch_pool_link; |
2062 | 2050 | ||
2063 | /** |
2051 | /** |
2064 | * This is set if the object is on the active lists (has pending |
2052 | * This is set if the object is on the active lists (has pending |
2065 | * rendering and so a non-zero seqno), and is not set if it i s on |
2053 | * rendering and so a non-zero seqno), and is not set if it i s on |
2066 | * inactive (ready to be unbound) list. |
2054 | * inactive (ready to be unbound) list. |
2067 | */ |
2055 | */ |
2068 | unsigned int active:I915_NUM_RINGS; |
2056 | unsigned int active:I915_NUM_RINGS; |
2069 | 2057 | ||
2070 | /** |
2058 | /** |
2071 | * This is set if the object has been written to since last bound |
2059 | * This is set if the object has been written to since last bound |
2072 | * to the GTT |
2060 | * to the GTT |
2073 | */ |
2061 | */ |
2074 | unsigned int dirty:1; |
2062 | unsigned int dirty:1; |
2075 | 2063 | ||
2076 | /** |
2064 | /** |
2077 | * Fence register bits (if any) for this object. Will be set |
2065 | * Fence register bits (if any) for this object. Will be set |
2078 | * as needed when mapped into the GTT. |
2066 | * as needed when mapped into the GTT. |
2079 | * Protected by dev->struct_mutex. |
2067 | * Protected by dev->struct_mutex. |
2080 | */ |
2068 | */ |
2081 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
2069 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
2082 | 2070 | ||
2083 | /** |
2071 | /** |
2084 | * Advice: are the backing pages purgeable? |
2072 | * Advice: are the backing pages purgeable? |
2085 | */ |
2073 | */ |
2086 | unsigned int madv:2; |
2074 | unsigned int madv:2; |
2087 | 2075 | ||
2088 | /** |
2076 | /** |
2089 | * Current tiling mode for the object. |
2077 | * Current tiling mode for the object. |
2090 | */ |
2078 | */ |
2091 | unsigned int tiling_mode:2; |
2079 | unsigned int tiling_mode:2; |
2092 | /** |
2080 | /** |
2093 | * Whether the tiling parameters for the currently associated fence |
2081 | * Whether the tiling parameters for the currently associated fence |
2094 | * register have changed. Note that for the purposes of tracking |
2082 | * register have changed. Note that for the purposes of tracking |
2095 | * tiling changes we also treat the unfenced register, the register |
2083 | * tiling changes we also treat the unfenced register, the register |
2096 | * slot that the object occupies whilst it executes a fenced |
2084 | * slot that the object occupies whilst it executes a fenced |
2097 | * command (such as BLT on gen2/3), as a "fence". |
2085 | * command (such as BLT on gen2/3), as a "fence". |
2098 | */ |
2086 | */ |
2099 | unsigned int fence_dirty:1; |
2087 | unsigned int fence_dirty:1; |
2100 | 2088 | ||
2101 | /** |
2089 | /** |
2102 | * Is the object at the current location in the gtt mappable and |
2090 | * Is the object at the current location in the gtt mappable and |
2103 | * fenceable? Used to avoid costly recalculations. |
2091 | * fenceable? Used to avoid costly recalculations. |
2104 | */ |
2092 | */ |
2105 | unsigned int map_and_fenceable:1; |
2093 | unsigned int map_and_fenceable:1; |
2106 | 2094 | ||
2107 | /** |
2095 | /** |
2108 | * Whether the current gtt mapping needs to be mappable (and isn't just |
2096 | * Whether the current gtt mapping needs to be mappable (and isn't just |
2109 | * mappable by accident). Track pin and fault separate for a more |
2097 | * mappable by accident). Track pin and fault separate for a more |
2110 | * accurate mappable working set. |
2098 | * accurate mappable working set. |
2111 | */ |
2099 | */ |
2112 | unsigned int fault_mappable:1; |
2100 | unsigned int fault_mappable:1; |
2113 | 2101 | ||
2114 | /* |
2102 | /* |
2115 | * Is the object to be mapped as read-only to the GPU |
2103 | * Is the object to be mapped as read-only to the GPU |
2116 | * Only honoured if hardware has relevant pte bit |
2104 | * Only honoured if hardware has relevant pte bit |
2117 | */ |
2105 | */ |
2118 | unsigned long gt_ro:1; |
2106 | unsigned long gt_ro:1; |
2119 | unsigned int cache_level:3; |
2107 | unsigned int cache_level:3; |
2120 | unsigned int cache_dirty:1; |
2108 | unsigned int cache_dirty:1; |
2121 | 2109 | ||
2122 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2110 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2123 | 2111 | ||
2124 | unsigned int pin_display; |
2112 | unsigned int pin_display; |
2125 | 2113 | ||
2126 | struct sg_table *pages; |
2114 | struct sg_table *pages; |
2127 | int pages_pin_count; |
2115 | int pages_pin_count; |
2128 | struct get_page { |
2116 | struct get_page { |
2129 | struct scatterlist *sg; |
2117 | struct scatterlist *sg; |
2130 | int last; |
2118 | int last; |
2131 | } get_page; |
2119 | } get_page; |
2132 | 2120 | ||
2133 | /* prime dma-buf support */ |
2121 | /* prime dma-buf support */ |
2134 | void *dma_buf_vmapping; |
2122 | void *dma_buf_vmapping; |
2135 | int vmapping_count; |
2123 | int vmapping_count; |
2136 | 2124 | ||
2137 | /** Breadcrumb of last rendering to the buffer. |
2125 | /** Breadcrumb of last rendering to the buffer. |
2138 | * There can only be one writer, but we allow for multiple readers. |
2126 | * There can only be one writer, but we allow for multiple readers. |
2139 | * If there is a writer that necessarily implies that all other |
2127 | * If there is a writer that necessarily implies that all other |
2140 | * read requests are complete - but we may only be lazily clearing |
2128 | * read requests are complete - but we may only be lazily clearing |
2141 | * the read requests. A read request is naturally the most recent |
2129 | * the read requests. A read request is naturally the most recent |
2142 | * request on a ring, so we may have two different write and read |
2130 | * request on a ring, so we may have two different write and read |
2143 | * requests on one ring where the write request is older than the |
2131 | * requests on one ring where the write request is older than the |
2144 | * read request. This allows for the CPU to read from an active |
2132 | * read request. This allows for the CPU to read from an active |
2145 | * buffer by only waiting for the write to complete. |
2133 | * buffer by only waiting for the write to complete. |
2146 | * */ |
2134 | * */ |
2147 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; |
2135 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; |
2148 | struct drm_i915_gem_request *last_write_req; |
2136 | struct drm_i915_gem_request *last_write_req; |
2149 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
2137 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
2150 | struct drm_i915_gem_request *last_fenced_req; |
2138 | struct drm_i915_gem_request *last_fenced_req; |
2151 | 2139 | ||
2152 | /** Current tiling stride for the object, if it's tiled. */ |
2140 | /** Current tiling stride for the object, if it's tiled. */ |
2153 | uint32_t stride; |
2141 | uint32_t stride; |
2154 | 2142 | ||
2155 | /** References from framebuffers, locks out tiling changes. */ |
2143 | /** References from framebuffers, locks out tiling changes. */ |
2156 | unsigned long framebuffer_references; |
2144 | unsigned long framebuffer_references; |
2157 | 2145 | ||
2158 | /** Record of address bit 17 of each page at last unbind. */ |
2146 | /** Record of address bit 17 of each page at last unbind. */ |
2159 | unsigned long *bit_17; |
2147 | unsigned long *bit_17; |
- | 2148 | ||
- | 2149 | union { |
|
- | 2150 | /** for phy allocated objects */ |
|
- | 2151 | struct drm_dma_handle *phys_handle; |
|
2160 | 2152 | ||
2161 | struct i915_gem_userptr { |
2153 | struct i915_gem_userptr { |
2162 | uintptr_t ptr; |
2154 | uintptr_t ptr; |
2163 | unsigned read_only :1; |
2155 | unsigned read_only :1; |
2164 | unsigned workers :4; |
2156 | unsigned workers :4; |
2165 | #define I915_GEM_USERPTR_MAX_WORKERS 15 |
2157 | #define I915_GEM_USERPTR_MAX_WORKERS 15 |
2166 | 2158 | ||
2167 | struct i915_mm_struct *mm; |
2159 | struct i915_mm_struct *mm; |
2168 | struct i915_mmu_object *mmu_object; |
2160 | struct i915_mmu_object *mmu_object; |
2169 | struct work_struct *work; |
2161 | struct work_struct *work; |
2170 | } userptr; |
2162 | } userptr; |
2171 | 2163 | }; |
|
2172 | /** for phys allocated objects */ |
- | |
2173 | struct drm_dma_handle *phys_handle; |
- | |
2174 | }; |
2164 | }; |
2175 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
2165 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
2176 | 2166 | ||
2177 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2167 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2178 | struct drm_i915_gem_object *new, |
2168 | struct drm_i915_gem_object *new, |
2179 | unsigned frontbuffer_bits); |
2169 | unsigned frontbuffer_bits); |
2180 | 2170 | ||
2181 | /** |
2171 | /** |
2182 | * Request queue structure. |
2172 | * Request queue structure. |
2183 | * |
2173 | * |
2184 | * The request queue allows us to note sequence numbers that have been emitted |
2174 | * The request queue allows us to note sequence numbers that have been emitted |
2185 | * and may be associated with active buffers to be retired. |
2175 | * and may be associated with active buffers to be retired. |
2186 | * |
2176 | * |
2187 | * By keeping this list, we can avoid having to do questionable sequence |
2177 | * By keeping this list, we can avoid having to do questionable sequence |
2188 | * number comparisons on buffer last_read|write_seqno. It also allows an |
2178 | * number comparisons on buffer last_read|write_seqno. It also allows an |
2189 | * emission time to be associated with the request for tracking how far ahead |
2179 | * emission time to be associated with the request for tracking how far ahead |
2190 | * of the GPU the submission is. |
2180 | * of the GPU the submission is. |
2191 | * |
2181 | * |
2192 | * The requests are reference counted, so upon creation they should have an |
2182 | * The requests are reference counted, so upon creation they should have an |
2193 | * initial reference taken using kref_init |
2183 | * initial reference taken using kref_init |
2194 | */ |
2184 | */ |
2195 | struct drm_i915_gem_request { |
2185 | struct drm_i915_gem_request { |
2196 | struct kref ref; |
2186 | struct kref ref; |
2197 | 2187 | ||
2198 | /** On Which ring this request was generated */ |
2188 | /** On Which ring this request was generated */ |
2199 | struct drm_i915_private *i915; |
2189 | struct drm_i915_private *i915; |
2200 | struct intel_engine_cs *ring; |
2190 | struct intel_engine_cs *ring; |
2201 | 2191 | ||
2202 | /** GEM sequence number associated with the previous request, |
2192 | /** GEM sequence number associated with the previous request, |
2203 | * when the HWS breadcrumb is equal to this the GPU is processing |
2193 | * when the HWS breadcrumb is equal to this the GPU is processing |
2204 | * this request. |
2194 | * this request. |
2205 | */ |
2195 | */ |
2206 | u32 previous_seqno; |
2196 | u32 previous_seqno; |
2207 | 2197 | ||
2208 | /** GEM sequence number associated with this request, |
2198 | /** GEM sequence number associated with this request, |
2209 | * when the HWS breadcrumb is equal or greater than this the GPU |
2199 | * when the HWS breadcrumb is equal or greater than this the GPU |
2210 | * has finished processing this request. |
2200 | * has finished processing this request. |
2211 | */ |
2201 | */ |
2212 | u32 seqno; |
2202 | u32 seqno; |
2213 | 2203 | ||
2214 | /** Position in the ringbuffer of the start of the request */ |
2204 | /** Position in the ringbuffer of the start of the request */ |
2215 | u32 head; |
2205 | u32 head; |
2216 | 2206 | ||
2217 | /** |
2207 | /** |
2218 | * Position in the ringbuffer of the start of the postfix. |
2208 | * Position in the ringbuffer of the start of the postfix. |
2219 | * This is required to calculate the maximum available ringbuffer |
2209 | * This is required to calculate the maximum available ringbuffer |
2220 | * space without overwriting the postfix. |
2210 | * space without overwriting the postfix. |
2221 | */ |
2211 | */ |
2222 | u32 postfix; |
2212 | u32 postfix; |
2223 | 2213 | ||
2224 | /** Position in the ringbuffer of the end of the whole request */ |
2214 | /** Position in the ringbuffer of the end of the whole request */ |
2225 | u32 tail; |
2215 | u32 tail; |
2226 | 2216 | ||
2227 | /** |
2217 | /** |
2228 | * Context and ring buffer related to this request |
2218 | * Context and ring buffer related to this request |
2229 | * Contexts are refcounted, so when this request is associated with a |
2219 | * Contexts are refcounted, so when this request is associated with a |
2230 | * context, we must increment the context's refcount, to guarantee that |
2220 | * context, we must increment the context's refcount, to guarantee that |
2231 | * it persists while any request is linked to it. Requests themselves |
2221 | * it persists while any request is linked to it. Requests themselves |
2232 | * are also refcounted, so the request will only be freed when the last |
2222 | * are also refcounted, so the request will only be freed when the last |
2233 | * reference to it is dismissed, and the code in |
2223 | * reference to it is dismissed, and the code in |
2234 | * i915_gem_request_free() will then decrement the refcount on the |
2224 | * i915_gem_request_free() will then decrement the refcount on the |
2235 | * context. |
2225 | * context. |
2236 | */ |
2226 | */ |
2237 | struct intel_context *ctx; |
2227 | struct intel_context *ctx; |
2238 | struct intel_ringbuffer *ringbuf; |
2228 | struct intel_ringbuffer *ringbuf; |
2239 | 2229 | ||
2240 | /** Batch buffer related to this request if any (used for |
2230 | /** Batch buffer related to this request if any (used for |
2241 | error state dump only) */ |
2231 | error state dump only) */ |
2242 | struct drm_i915_gem_object *batch_obj; |
2232 | struct drm_i915_gem_object *batch_obj; |
2243 | 2233 | ||
2244 | /** Time at which this request was emitted, in jiffies. */ |
2234 | /** Time at which this request was emitted, in jiffies. */ |
2245 | unsigned long emitted_jiffies; |
2235 | unsigned long emitted_jiffies; |
2246 | 2236 | ||
2247 | /** global list entry for this request */ |
2237 | /** global list entry for this request */ |
2248 | struct list_head list; |
2238 | struct list_head list; |
2249 | 2239 | ||
2250 | struct drm_i915_file_private *file_priv; |
2240 | struct drm_i915_file_private *file_priv; |
2251 | /** file_priv list entry for this request */ |
2241 | /** file_priv list entry for this request */ |
2252 | struct list_head client_list; |
2242 | struct list_head client_list; |
2253 | 2243 | ||
2254 | /** process identifier submitting this request */ |
2244 | /** process identifier submitting this request */ |
2255 | struct pid *pid; |
2245 | struct pid *pid; |
2256 | 2246 | ||
2257 | /** |
2247 | /** |
2258 | * The ELSP only accepts two elements at a time, so we queue |
2248 | * The ELSP only accepts two elements at a time, so we queue |
2259 | * context/tail pairs on a given queue (ring->execlist_queue) until the |
2249 | * context/tail pairs on a given queue (ring->execlist_queue) until the |
2260 | * hardware is available. The queue serves a double purpose: we also use |
2250 | * hardware is available. The queue serves a double purpose: we also use |
2261 | * it to keep track of the up to 2 contexts currently in the hardware |
2251 | * it to keep track of the up to 2 contexts currently in the hardware |
2262 | * (usually one in execution and the other queued up by the GPU): We |
2252 | * (usually one in execution and the other queued up by the GPU): We |
2263 | * only remove elements from the head of the queue when the hardware |
2253 | * only remove elements from the head of the queue when the hardware |
2264 | * informs us that an element has been completed. |
2254 | * informs us that an element has been completed. |
2265 | * |
2255 | * |
2266 | * All accesses to the queue are mediated by a spinlock |
2256 | * All accesses to the queue are mediated by a spinlock |
2267 | * (ring->execlist_lock). |
2257 | * (ring->execlist_lock). |
2268 | */ |
2258 | */ |
2269 | 2259 | ||
2270 | /** Execlist link in the submission queue.*/ |
2260 | /** Execlist link in the submission queue.*/ |
2271 | struct list_head execlist_link; |
2261 | struct list_head execlist_link; |
2272 | 2262 | ||
2273 | /** Execlists no. of times this request has been sent to the ELSP */ |
2263 | /** Execlists no. of times this request has been sent to the ELSP */ |
2274 | int elsp_submitted; |
2264 | int elsp_submitted; |
2275 | 2265 | ||
2276 | }; |
2266 | }; |
2277 | 2267 | ||
2278 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
2268 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
2279 | struct intel_context *ctx, |
2269 | struct intel_context *ctx, |
2280 | struct drm_i915_gem_request **req_out); |
2270 | struct drm_i915_gem_request **req_out); |
2281 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
2271 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
2282 | void i915_gem_request_free(struct kref *req_ref); |
2272 | void i915_gem_request_free(struct kref *req_ref); |
2283 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2273 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2284 | struct drm_file *file); |
2274 | struct drm_file *file); |
2285 | 2275 | ||
2286 | static inline uint32_t |
2276 | static inline uint32_t |
2287 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) |
2277 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) |
2288 | { |
2278 | { |
2289 | return req ? req->seqno : 0; |
2279 | return req ? req->seqno : 0; |
2290 | } |
2280 | } |
2291 | 2281 | ||
2292 | static inline struct intel_engine_cs * |
2282 | static inline struct intel_engine_cs * |
2293 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) |
2283 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) |
2294 | { |
2284 | { |
2295 | return req ? req->ring : NULL; |
2285 | return req ? req->ring : NULL; |
2296 | } |
2286 | } |
2297 | 2287 | ||
2298 | static inline struct drm_i915_gem_request * |
2288 | static inline struct drm_i915_gem_request * |
2299 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2289 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2300 | { |
2290 | { |
2301 | if (req) |
2291 | if (req) |
2302 | kref_get(&req->ref); |
2292 | kref_get(&req->ref); |
2303 | return req; |
2293 | return req; |
2304 | } |
2294 | } |
2305 | 2295 | ||
2306 | static inline void |
2296 | static inline void |
2307 | i915_gem_request_unreference(struct drm_i915_gem_request *req) |
2297 | i915_gem_request_unreference(struct drm_i915_gem_request *req) |
2308 | { |
2298 | { |
2309 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
2299 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
2310 | kref_put(&req->ref, i915_gem_request_free); |
2300 | kref_put(&req->ref, i915_gem_request_free); |
2311 | } |
2301 | } |
2312 | 2302 | ||
2313 | static inline void |
2303 | static inline void |
2314 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) |
2304 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) |
2315 | { |
2305 | { |
2316 | struct drm_device *dev; |
2306 | struct drm_device *dev; |
2317 | 2307 | ||
2318 | if (!req) |
2308 | if (!req) |
2319 | return; |
2309 | return; |
2320 | 2310 | ||
2321 | dev = req->ring->dev; |
2311 | dev = req->ring->dev; |
2322 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) |
2312 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) |
2323 | mutex_unlock(&dev->struct_mutex); |
2313 | mutex_unlock(&dev->struct_mutex); |
2324 | } |
2314 | } |
2325 | 2315 | ||
2326 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2316 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2327 | struct drm_i915_gem_request *src) |
2317 | struct drm_i915_gem_request *src) |
2328 | { |
2318 | { |
2329 | if (src) |
2319 | if (src) |
2330 | i915_gem_request_reference(src); |
2320 | i915_gem_request_reference(src); |
2331 | 2321 | ||
2332 | if (*pdst) |
2322 | if (*pdst) |
2333 | i915_gem_request_unreference(*pdst); |
2323 | i915_gem_request_unreference(*pdst); |
2334 | 2324 | ||
2335 | *pdst = src; |
2325 | *pdst = src; |
2336 | } |
2326 | } |
2337 | 2327 | ||
2338 | /* |
2328 | /* |
2339 | * XXX: i915_gem_request_completed should be here but currently needs the |
2329 | * XXX: i915_gem_request_completed should be here but currently needs the |
2340 | * definition of i915_seqno_passed() which is below. It will be moved in |
2330 | * definition of i915_seqno_passed() which is below. It will be moved in |
2341 | * a later patch when the call to i915_seqno_passed() is obsoleted... |
2331 | * a later patch when the call to i915_seqno_passed() is obsoleted... |
2342 | */ |
2332 | */ |
2343 | 2333 | ||
2344 | /* |
2334 | /* |
2345 | * A command that requires special handling by the command parser. |
2335 | * A command that requires special handling by the command parser. |
2346 | */ |
2336 | */ |
2347 | struct drm_i915_cmd_descriptor { |
2337 | struct drm_i915_cmd_descriptor { |
2348 | /* |
2338 | /* |
2349 | * Flags describing how the command parser processes the command. |
2339 | * Flags describing how the command parser processes the command. |
2350 | * |
2340 | * |
2351 | * CMD_DESC_FIXED: The command has a fixed length if this is set, |
2341 | * CMD_DESC_FIXED: The command has a fixed length if this is set, |
2352 | * a length mask if not set |
2342 | * a length mask if not set |
2353 | * CMD_DESC_SKIP: The command is allowed but does not follow the |
2343 | * CMD_DESC_SKIP: The command is allowed but does not follow the |
2354 | * standard length encoding for the opcode range in |
2344 | * standard length encoding for the opcode range in |
2355 | * which it falls |
2345 | * which it falls |
2356 | * CMD_DESC_REJECT: The command is never allowed |
2346 | * CMD_DESC_REJECT: The command is never allowed |
2357 | * CMD_DESC_REGISTER: The command should be checked against the |
2347 | * CMD_DESC_REGISTER: The command should be checked against the |
2358 | * register whitelist for the appropriate ring |
2348 | * register whitelist for the appropriate ring |
2359 | * CMD_DESC_MASTER: The command is allowed if the submitting process |
2349 | * CMD_DESC_MASTER: The command is allowed if the submitting process |
2360 | * is the DRM master |
2350 | * is the DRM master |
2361 | */ |
2351 | */ |
2362 | u32 flags; |
2352 | u32 flags; |
2363 | #define CMD_DESC_FIXED (1<<0) |
2353 | #define CMD_DESC_FIXED (1<<0) |
2364 | #define CMD_DESC_SKIP (1<<1) |
2354 | #define CMD_DESC_SKIP (1<<1) |
2365 | #define CMD_DESC_REJECT (1<<2) |
2355 | #define CMD_DESC_REJECT (1<<2) |
2366 | #define CMD_DESC_REGISTER (1<<3) |
2356 | #define CMD_DESC_REGISTER (1<<3) |
2367 | #define CMD_DESC_BITMASK (1<<4) |
2357 | #define CMD_DESC_BITMASK (1<<4) |
2368 | #define CMD_DESC_MASTER (1<<5) |
2358 | #define CMD_DESC_MASTER (1<<5) |
2369 | 2359 | ||
2370 | /* |
2360 | /* |
2371 | * The command's unique identification bits and the bitmask to get them. |
2361 | * The command's unique identification bits and the bitmask to get them. |
2372 | * This isn't strictly the opcode field as defined in the spec and may |
2362 | * This isn't strictly the opcode field as defined in the spec and may |
2373 | * also include type, subtype, and/or subop fields. |
2363 | * also include type, subtype, and/or subop fields. |
2374 | */ |
2364 | */ |
2375 | struct { |
2365 | struct { |
2376 | u32 value; |
2366 | u32 value; |
2377 | u32 mask; |
2367 | u32 mask; |
2378 | } cmd; |
2368 | } cmd; |
2379 | 2369 | ||
2380 | /* |
2370 | /* |
2381 | * The command's length. The command is either fixed length (i.e. does |
2371 | * The command's length. The command is either fixed length (i.e. does |
2382 | * not include a length field) or has a length field mask. The flag |
2372 | * not include a length field) or has a length field mask. The flag |
2383 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has |
2373 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has |
2384 | * a length mask. All command entries in a command table must include |
2374 | * a length mask. All command entries in a command table must include |
2385 | * length information. |
2375 | * length information. |
2386 | */ |
2376 | */ |
2387 | union { |
2377 | union { |
2388 | u32 fixed; |
2378 | u32 fixed; |
2389 | u32 mask; |
2379 | u32 mask; |
2390 | } length; |
2380 | } length; |
2391 | 2381 | ||
2392 | /* |
2382 | /* |
2393 | * Describes where to find a register address in the command to check |
2383 | * Describes where to find a register address in the command to check |
2394 | * against the ring's register whitelist. Only valid if flags has the |
2384 | * against the ring's register whitelist. Only valid if flags has the |
2395 | * CMD_DESC_REGISTER bit set. |
2385 | * CMD_DESC_REGISTER bit set. |
2396 | * |
2386 | * |
2397 | * A non-zero step value implies that the command may access multiple |
2387 | * A non-zero step value implies that the command may access multiple |
2398 | * registers in sequence (e.g. LRI), in that case step gives the |
2388 | * registers in sequence (e.g. LRI), in that case step gives the |
2399 | * distance in dwords between individual offset fields. |
2389 | * distance in dwords between individual offset fields. |
2400 | */ |
2390 | */ |
2401 | struct { |
2391 | struct { |
2402 | u32 offset; |
2392 | u32 offset; |
2403 | u32 mask; |
2393 | u32 mask; |
2404 | u32 step; |
2394 | u32 step; |
2405 | } reg; |
2395 | } reg; |
2406 | 2396 | ||
2407 | #define MAX_CMD_DESC_BITMASKS 3 |
2397 | #define MAX_CMD_DESC_BITMASKS 3 |
2408 | /* |
2398 | /* |
2409 | * Describes command checks where a particular dword is masked and |
2399 | * Describes command checks where a particular dword is masked and |
2410 | * compared against an expected value. If the command does not match |
2400 | * compared against an expected value. If the command does not match |
2411 | * the expected value, the parser rejects it. Only valid if flags has |
2401 | * the expected value, the parser rejects it. Only valid if flags has |
2412 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero |
2402 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero |
2413 | * are valid. |
2403 | * are valid. |
2414 | * |
2404 | * |
2415 | * If the check specifies a non-zero condition_mask then the parser |
2405 | * If the check specifies a non-zero condition_mask then the parser |
2416 | * only performs the check when the bits specified by condition_mask |
2406 | * only performs the check when the bits specified by condition_mask |
2417 | * are non-zero. |
2407 | * are non-zero. |
2418 | */ |
2408 | */ |
2419 | struct { |
2409 | struct { |
2420 | u32 offset; |
2410 | u32 offset; |
2421 | u32 mask; |
2411 | u32 mask; |
2422 | u32 expected; |
2412 | u32 expected; |
2423 | u32 condition_offset; |
2413 | u32 condition_offset; |
2424 | u32 condition_mask; |
2414 | u32 condition_mask; |
2425 | } bits[MAX_CMD_DESC_BITMASKS]; |
2415 | } bits[MAX_CMD_DESC_BITMASKS]; |
2426 | }; |
2416 | }; |
2427 | 2417 | ||
2428 | /* |
2418 | /* |
2429 | * A table of commands requiring special handling by the command parser. |
2419 | * A table of commands requiring special handling by the command parser. |
2430 | * |
2420 | * |
2431 | * Each ring has an array of tables. Each table consists of an array of command |
2421 | * Each ring has an array of tables. Each table consists of an array of command |
2432 | * descriptors, which must be sorted with command opcodes in ascending order. |
2422 | * descriptors, which must be sorted with command opcodes in ascending order. |
2433 | */ |
2423 | */ |
2434 | struct drm_i915_cmd_table { |
2424 | struct drm_i915_cmd_table { |
2435 | const struct drm_i915_cmd_descriptor *table; |
2425 | const struct drm_i915_cmd_descriptor *table; |
2436 | int count; |
2426 | int count; |
2437 | }; |
2427 | }; |
2438 | 2428 | ||
2439 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
2429 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
2440 | #define __I915__(p) ({ \ |
2430 | #define __I915__(p) ({ \ |
2441 | struct drm_i915_private *__p; \ |
2431 | struct drm_i915_private *__p; \ |
2442 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ |
2432 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ |
2443 | __p = (struct drm_i915_private *)p; \ |
2433 | __p = (struct drm_i915_private *)p; \ |
2444 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ |
2434 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ |
2445 | __p = to_i915((struct drm_device *)p); \ |
2435 | __p = to_i915((struct drm_device *)p); \ |
2446 | else \ |
2436 | else \ |
2447 | BUILD_BUG(); \ |
2437 | BUILD_BUG(); \ |
2448 | __p; \ |
2438 | __p; \ |
2449 | }) |
2439 | }) |
2450 | #define INTEL_INFO(p) (&__I915__(p)->info) |
2440 | #define INTEL_INFO(p) (&__I915__(p)->info) |
2451 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
2441 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
2452 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
2442 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
- | 2443 | ||
- | 2444 | #define REVID_FOREVER 0xff |
|
- | 2445 | /* |
|
- | 2446 | * Return true if revision is in range [since,until] inclusive. |
|
- | 2447 | * |
|
- | 2448 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. |
|
- | 2449 | */ |
|
- | 2450 | #define IS_REVID(p, since, until) \ |
|
- | 2451 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) |
|
2453 | 2452 | ||
2454 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2453 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2455 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) |
2454 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) |
2456 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
2455 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
2457 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
2456 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
2458 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
2457 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
2459 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2458 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2460 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) |
2459 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) |
2461 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2460 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2462 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
2461 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
2463 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
2462 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
2464 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
2463 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
2465 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
2464 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
2466 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2465 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2467 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) |
2466 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) |
2468 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2467 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2469 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
2468 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
2470 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
2469 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
2471 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
2470 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
2472 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2471 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2473 | INTEL_DEVID(dev) == 0x0152 || \ |
2472 | INTEL_DEVID(dev) == 0x0152 || \ |
2474 | INTEL_DEVID(dev) == 0x015a) |
2473 | INTEL_DEVID(dev) == 0x015a) |
2475 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
2474 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
2476 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
2475 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) |
2477 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
2476 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
2478 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
2477 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev)) |
2479 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
2478 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
2480 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
2479 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) |
- | 2480 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) |
|
2481 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
2481 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
2482 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
2482 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
2483 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
2483 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
2484 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
2484 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
2485 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
2485 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
2486 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
2486 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
2487 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
2487 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
2488 | /* ULX machines are also considered ULT. */ |
2488 | /* ULX machines are also considered ULT. */ |
2489 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ |
2489 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ |
2490 | (INTEL_DEVID(dev) & 0xf) == 0xe) |
2490 | (INTEL_DEVID(dev) & 0xf) == 0xe) |
2491 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2491 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2492 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2492 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2493 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
2493 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
2494 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
2494 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
2495 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
2495 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
2496 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2496 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2497 | /* ULX machines are also considered ULT. */ |
2497 | /* ULX machines are also considered ULT. */ |
2498 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2498 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2499 | INTEL_DEVID(dev) == 0x0A1E) |
2499 | INTEL_DEVID(dev) == 0x0A1E) |
2500 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2500 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2501 | INTEL_DEVID(dev) == 0x1913 || \ |
2501 | INTEL_DEVID(dev) == 0x1913 || \ |
2502 | INTEL_DEVID(dev) == 0x1916 || \ |
2502 | INTEL_DEVID(dev) == 0x1916 || \ |
2503 | INTEL_DEVID(dev) == 0x1921 || \ |
2503 | INTEL_DEVID(dev) == 0x1921 || \ |
2504 | INTEL_DEVID(dev) == 0x1926) |
2504 | INTEL_DEVID(dev) == 0x1926) |
2505 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ |
2505 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ |
2506 | INTEL_DEVID(dev) == 0x1915 || \ |
2506 | INTEL_DEVID(dev) == 0x1915 || \ |
2507 | INTEL_DEVID(dev) == 0x191E) |
2507 | INTEL_DEVID(dev) == 0x191E) |
- | 2508 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ |
|
- | 2509 | INTEL_DEVID(dev) == 0x5913 || \ |
|
- | 2510 | INTEL_DEVID(dev) == 0x5916 || \ |
|
- | 2511 | INTEL_DEVID(dev) == 0x5921 || \ |
|
- | 2512 | INTEL_DEVID(dev) == 0x5926) |
|
- | 2513 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ |
|
- | 2514 | INTEL_DEVID(dev) == 0x5915 || \ |
|
- | 2515 | INTEL_DEVID(dev) == 0x591E) |
|
2508 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2516 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2509 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2517 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
2510 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ |
2518 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ |
2511 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) |
2519 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) |
2512 | 2520 | ||
2513 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
2521 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
2514 | 2522 | ||
2515 | #define SKL_REVID_A0 (0x0) |
2523 | #define SKL_REVID_A0 0x0 |
2516 | #define SKL_REVID_B0 (0x1) |
2524 | #define SKL_REVID_B0 0x1 |
2517 | #define SKL_REVID_C0 (0x2) |
2525 | #define SKL_REVID_C0 0x2 |
2518 | #define SKL_REVID_D0 (0x3) |
2526 | #define SKL_REVID_D0 0x3 |
2519 | #define SKL_REVID_E0 (0x4) |
2527 | #define SKL_REVID_E0 0x4 |
- | 2528 | #define SKL_REVID_F0 0x5 |
|
- | 2529 | ||
2520 | #define SKL_REVID_F0 (0x5) |
2530 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2521 | 2531 | ||
- | 2532 | #define BXT_REVID_A0 0x0 |
|
2522 | #define BXT_REVID_A0 (0x0) |
2533 | #define BXT_REVID_A1 0x1 |
2523 | #define BXT_REVID_B0 (0x3) |
2534 | #define BXT_REVID_B0 0x3 |
- | 2535 | #define BXT_REVID_C0 0x9 |
|
- | 2536 | ||
2524 | #define BXT_REVID_C0 (0x9) |
2537 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) |
2525 | 2538 | ||
2526 | /* |
2539 | /* |
2527 | * The genX designation typically refers to the render engine, so render |
2540 | * The genX designation typically refers to the render engine, so render |
2528 | * capability related checks should use IS_GEN, while display and other checks |
2541 | * capability related checks should use IS_GEN, while display and other checks |
2529 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
2542 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
2530 | * chips, etc.). |
2543 | * chips, etc.). |
2531 | */ |
2544 | */ |
2532 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2545 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2533 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
2546 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
2534 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
2547 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
2535 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
2548 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
2536 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
2549 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
2537 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
2550 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
2538 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
2551 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
2539 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
2552 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
2540 | 2553 | ||
2541 | #define RENDER_RING (1< |
2554 | #define RENDER_RING (1< |
2542 | #define BSD_RING (1< |
2555 | #define BSD_RING (1< |
2543 | #define BLT_RING (1< |
2556 | #define BLT_RING (1< |
2544 | #define VEBOX_RING (1< |
2557 | #define VEBOX_RING (1< |
2545 | #define BSD2_RING (1< |
2558 | #define BSD2_RING (1< |
2546 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
2559 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
2547 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
2560 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
2548 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2561 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2549 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
2562 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
2550 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
2563 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
2551 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
2564 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ |
2552 | __I915__(dev)->ellc_size) |
2565 | __I915__(dev)->ellc_size) |
2553 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2566 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2554 | 2567 | ||
2555 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
2568 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
2556 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
2569 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
2557 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2570 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2558 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2571 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2559 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) |
2572 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) |
2560 | 2573 | ||
2561 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
2574 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
2562 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2575 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2563 | 2576 | ||
2564 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2577 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2565 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
2578 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
2566 | /* |
2579 | /* |
2567 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts |
2580 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts |
2568 | * even when in MSI mode. This results in spurious interrupt warnings if the |
2581 | * even when in MSI mode. This results in spurious interrupt warnings if the |
2569 | * legacy irq no. is shared with another device. The kernel then disables that |
2582 | * legacy irq no. is shared with another device. The kernel then disables that |
2570 | * interrupt source and so prevents the other device from working properly. |
2583 | * interrupt source and so prevents the other device from working properly. |
2571 | */ |
2584 | */ |
2572 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
2585 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
2573 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
2586 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
2574 | 2587 | ||
2575 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2588 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2576 | * rows, which changed the alignment requirements and fence programming. |
2589 | * rows, which changed the alignment requirements and fence programming. |
2577 | */ |
2590 | */ |
2578 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
2591 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
2579 | IS_I915GM(dev))) |
2592 | IS_I915GM(dev))) |
2580 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2593 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2581 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
2594 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
2582 | 2595 | ||
2583 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
2596 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
2584 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
2597 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
2585 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
2598 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
2586 | 2599 | ||
2587 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
2600 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
2588 | 2601 | ||
2589 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2602 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2590 | INTEL_INFO(dev)->gen >= 9) |
2603 | INTEL_INFO(dev)->gen >= 9) |
2591 | 2604 | ||
2592 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
2605 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
2593 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
2606 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
2594 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2607 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2595 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2608 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2596 | IS_SKYLAKE(dev)) |
2609 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
2597 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
2610 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
2598 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2611 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
- | 2612 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ |
|
2599 | IS_SKYLAKE(dev)) |
2613 | IS_KABYLAKE(dev)) |
2600 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2614 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2601 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
2615 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
2602 | 2616 | ||
2603 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
2617 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
2604 | 2618 | ||
2605 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) |
2619 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2606 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) |
2620 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev)) |
2607 | 2621 | ||
2608 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2622 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2609 | INTEL_INFO(dev)->gen >= 8) |
2623 | INTEL_INFO(dev)->gen >= 8) |
2610 | 2624 | ||
2611 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
2625 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
2612 | !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
2626 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ |
- | 2627 | !IS_BROXTON(dev)) |
|
2613 | 2628 | ||
2614 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2629 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2615 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
2630 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
2616 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
2631 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
2617 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
2632 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
2618 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
2633 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
2619 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
2634 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
2620 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2635 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2621 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 |
2636 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 |
2622 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
2637 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
2623 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
2638 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
2624 | 2639 | ||
2625 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
2640 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
2626 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
2641 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
2627 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2642 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
2628 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
2643 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
- | 2644 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) |
|
2629 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2645 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2630 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
2646 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
2631 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
2647 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
2632 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2648 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
2633 | 2649 | ||
- | 2650 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ |
|
2634 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2651 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
2635 | 2652 | ||
2636 | /* DPF == dynamic parity feature */ |
2653 | /* DPF == dynamic parity feature */ |
2637 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
2654 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
2638 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
2655 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
2639 | 2656 | ||
2640 | #define GT_FREQUENCY_MULTIPLIER 50 |
2657 | #define GT_FREQUENCY_MULTIPLIER 50 |
2641 | #define GEN9_FREQ_SCALER 3 |
2658 | #define GEN9_FREQ_SCALER 3 |
2642 | 2659 | ||
2643 | #include "i915_trace.h" |
2660 | #include "i915_trace.h" |
2644 | 2661 | ||
2645 | extern const struct drm_ioctl_desc i915_ioctls[]; |
2662 | extern const struct drm_ioctl_desc i915_ioctls[]; |
2646 | extern int i915_max_ioctl; |
2663 | extern int i915_max_ioctl; |
2647 | 2664 | ||
2648 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2665 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2649 | extern int i915_resume_switcheroo(struct drm_device *dev); |
2666 | extern int i915_resume_switcheroo(struct drm_device *dev); |
2650 | 2667 | ||
2651 | /* i915_params.c */ |
2668 | /* i915_params.c */ |
2652 | struct i915_params { |
2669 | struct i915_params { |
2653 | int modeset; |
2670 | int modeset; |
2654 | int panel_ignore_lid; |
2671 | int panel_ignore_lid; |
2655 | int semaphores; |
2672 | int semaphores; |
2656 | int lvds_channel_mode; |
2673 | int lvds_channel_mode; |
2657 | int panel_use_ssc; |
2674 | int panel_use_ssc; |
2658 | int vbt_sdvo_panel_type; |
2675 | int vbt_sdvo_panel_type; |
2659 | int enable_rc6; |
2676 | int enable_rc6; |
- | 2677 | int enable_dc; |
|
2660 | int enable_fbc; |
2678 | int enable_fbc; |
2661 | int enable_ppgtt; |
2679 | int enable_ppgtt; |
2662 | int enable_execlists; |
2680 | int enable_execlists; |
2663 | int enable_psr; |
2681 | int enable_psr; |
2664 | unsigned int preliminary_hw_support; |
2682 | unsigned int preliminary_hw_support; |
2665 | int disable_power_well; |
2683 | int disable_power_well; |
2666 | int enable_ips; |
2684 | int enable_ips; |
2667 | int invert_brightness; |
2685 | int invert_brightness; |
2668 | int enable_cmd_parser; |
2686 | int enable_cmd_parser; |
2669 | /* leave bools at the end to not create holes */ |
2687 | /* leave bools at the end to not create holes */ |
2670 | bool enable_hangcheck; |
2688 | bool enable_hangcheck; |
2671 | bool fastboot; |
2689 | bool fastboot; |
2672 | bool prefault_disable; |
2690 | bool prefault_disable; |
2673 | bool load_detect_test; |
2691 | bool load_detect_test; |
2674 | bool reset; |
2692 | bool reset; |
2675 | bool disable_display; |
2693 | bool disable_display; |
2676 | bool disable_vtd_wa; |
2694 | bool disable_vtd_wa; |
2677 | bool enable_guc_submission; |
2695 | bool enable_guc_submission; |
2678 | int guc_log_level; |
2696 | int guc_log_level; |
2679 | int use_mmio_flip; |
2697 | int use_mmio_flip; |
2680 | int mmio_debug; |
2698 | int mmio_debug; |
2681 | bool verbose_state_checks; |
2699 | bool verbose_state_checks; |
2682 | bool nuclear_pageflip; |
2700 | bool nuclear_pageflip; |
2683 | int edp_vswing; |
2701 | int edp_vswing; |
2684 | /* Kolibri related */ |
2702 | /* Kolibri related */ |
2685 | char *log_file; |
2703 | char *log_file; |
2686 | char *cmdline_mode; |
2704 | char *cmdline_mode; |
2687 | }; |
2705 | }; |
2688 | extern struct i915_params i915 __read_mostly; |
2706 | extern struct i915_params i915 __read_mostly; |
2689 | 2707 | ||
2690 | /* i915_dma.c */ |
2708 | /* i915_dma.c */ |
2691 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
2709 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
2692 | extern int i915_driver_unload(struct drm_device *); |
2710 | extern int i915_driver_unload(struct drm_device *); |
2693 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
2711 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
2694 | extern void i915_driver_lastclose(struct drm_device * dev); |
2712 | extern void i915_driver_lastclose(struct drm_device * dev); |
2695 | extern void i915_driver_preclose(struct drm_device *dev, |
2713 | extern void i915_driver_preclose(struct drm_device *dev, |
2696 | struct drm_file *file); |
2714 | struct drm_file *file); |
2697 | extern void i915_driver_postclose(struct drm_device *dev, |
2715 | extern void i915_driver_postclose(struct drm_device *dev, |
2698 | struct drm_file *file); |
2716 | struct drm_file *file); |
2699 | #ifdef CONFIG_COMPAT |
2717 | #ifdef CONFIG_COMPAT |
2700 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2718 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2701 | unsigned long arg); |
2719 | unsigned long arg); |
2702 | #endif |
2720 | #endif |
2703 | extern int intel_gpu_reset(struct drm_device *dev); |
2721 | extern int intel_gpu_reset(struct drm_device *dev); |
2704 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
2722 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
2705 | extern int i915_reset(struct drm_device *dev); |
2723 | extern int i915_reset(struct drm_device *dev); |
2706 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2724 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2707 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
2725 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
2708 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
2726 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
2709 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
2727 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
2710 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
2728 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
2711 | void i915_firmware_load_error_print(const char *fw_path, int err); |
- | |
2712 | 2729 | ||
2713 | /* intel_hotplug.c */ |
2730 | /* intel_hotplug.c */ |
2714 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); |
2731 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); |
2715 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2732 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2716 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); |
2733 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); |
2717 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
2734 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
2718 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
2735 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
2719 | 2736 | ||
2720 | /* i915_irq.c */ |
2737 | /* i915_irq.c */ |
2721 | void i915_queue_hangcheck(struct drm_device *dev); |
2738 | void i915_queue_hangcheck(struct drm_device *dev); |
2722 | __printf(3, 4) |
2739 | __printf(3, 4) |
2723 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2740 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2724 | const char *fmt, ...); |
2741 | const char *fmt, ...); |
2725 | 2742 | ||
2726 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2743 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2727 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2744 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2728 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); |
2745 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); |
2729 | 2746 | ||
2730 | extern void intel_uncore_sanitize(struct drm_device *dev); |
2747 | extern void intel_uncore_sanitize(struct drm_device *dev); |
2731 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2748 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2732 | bool restore_forcewake); |
2749 | bool restore_forcewake); |
2733 | extern void intel_uncore_init(struct drm_device *dev); |
2750 | extern void intel_uncore_init(struct drm_device *dev); |
2734 | extern void intel_uncore_check_errors(struct drm_device *dev); |
2751 | extern void intel_uncore_check_errors(struct drm_device *dev); |
2735 | extern void intel_uncore_fini(struct drm_device *dev); |
2752 | extern void intel_uncore_fini(struct drm_device *dev); |
2736 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
2753 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
2737 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
2754 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
2738 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
2755 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
2739 | enum forcewake_domains domains); |
2756 | enum forcewake_domains domains); |
2740 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
2757 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
2741 | enum forcewake_domains domains); |
2758 | enum forcewake_domains domains); |
2742 | /* Like above but the caller must manage the uncore.lock itself. |
2759 | /* Like above but the caller must manage the uncore.lock itself. |
2743 | * Must be used with I915_READ_FW and friends. |
2760 | * Must be used with I915_READ_FW and friends. |
2744 | */ |
2761 | */ |
2745 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
2762 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
2746 | enum forcewake_domains domains); |
2763 | enum forcewake_domains domains); |
2747 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, |
2764 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, |
2748 | enum forcewake_domains domains); |
2765 | enum forcewake_domains domains); |
2749 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
2766 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
2750 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2767 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2751 | { |
2768 | { |
2752 | return to_i915(dev)->vgpu.active; |
2769 | return to_i915(dev)->vgpu.active; |
2753 | } |
2770 | } |
2754 | 2771 | ||
2755 | void |
2772 | void |
2756 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
2773 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
2757 | u32 status_mask); |
2774 | u32 status_mask); |
2758 | 2775 | ||
2759 | void |
2776 | void |
2760 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
2777 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
2761 | u32 status_mask); |
2778 | u32 status_mask); |
2762 | 2779 | ||
2763 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2780 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2764 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
2781 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
2765 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2782 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2766 | uint32_t mask, |
2783 | uint32_t mask, |
2767 | uint32_t bits); |
2784 | uint32_t bits); |
- | 2785 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
|
- | 2786 | uint32_t interrupt_mask, |
|
- | 2787 | uint32_t enabled_irq_mask); |
|
2768 | void |
2788 | static inline void |
2769 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
2789 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2790 | { |
|
- | 2791 | ilk_update_display_irq(dev_priv, bits, bits); |
|
2770 | void |
2792 | } |
- | 2793 | static inline void |
|
2771 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); |
2794 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2795 | { |
|
- | 2796 | ilk_update_display_irq(dev_priv, bits, 0); |
|
- | 2797 | } |
|
- | 2798 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2799 | enum pipe pipe, |
|
- | 2800 | uint32_t interrupt_mask, |
|
- | 2801 | uint32_t enabled_irq_mask); |
|
- | 2802 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2803 | enum pipe pipe, uint32_t bits) |
|
- | 2804 | { |
|
- | 2805 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); |
|
- | 2806 | } |
|
- | 2807 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, |
|
- | 2808 | enum pipe pipe, uint32_t bits) |
|
- | 2809 | { |
|
- | 2810 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); |
|
- | 2811 | } |
|
2772 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2812 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2773 | uint32_t interrupt_mask, |
2813 | uint32_t interrupt_mask, |
2774 | uint32_t enabled_irq_mask); |
2814 | uint32_t enabled_irq_mask); |
- | 2815 | static inline void |
|
2775 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
2816 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2817 | { |
|
2776 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
2818 | ibx_display_interrupt_update(dev_priv, bits, bits); |
- | 2819 | } |
|
- | 2820 | static inline void |
|
2777 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
2821 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) |
- | 2822 | { |
|
2778 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
2823 | ibx_display_interrupt_update(dev_priv, bits, 0); |
- | 2824 | } |
|
- | 2825 | ||
2779 | 2826 | ||
2780 | /* i915_gem.c */ |
2827 | /* i915_gem.c */ |
2781 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2828 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2782 | struct drm_file *file_priv); |
2829 | struct drm_file *file_priv); |
2783 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
2830 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
2784 | struct drm_file *file_priv); |
2831 | struct drm_file *file_priv); |
2785 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
2832 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
2786 | struct drm_file *file_priv); |
2833 | struct drm_file *file_priv); |
2787 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
2834 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
2788 | struct drm_file *file_priv); |
2835 | struct drm_file *file_priv); |
2789 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2836 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2790 | struct drm_file *file_priv); |
2837 | struct drm_file *file_priv); |
2791 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2838 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2792 | struct drm_file *file_priv); |
2839 | struct drm_file *file_priv); |
2793 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
2840 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
2794 | struct drm_file *file_priv); |
2841 | struct drm_file *file_priv); |
2795 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2842 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2796 | struct drm_i915_gem_request *req); |
2843 | struct drm_i915_gem_request *req); |
2797 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
2844 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
2798 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
2845 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
2799 | struct drm_i915_gem_execbuffer2 *args, |
2846 | struct drm_i915_gem_execbuffer2 *args, |
2800 | struct list_head *vmas); |
2847 | struct list_head *vmas); |
2801 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2848 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2802 | struct drm_file *file_priv); |
2849 | struct drm_file *file_priv); |
2803 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2850 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2804 | struct drm_file *file_priv); |
2851 | struct drm_file *file_priv); |
2805 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2852 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2806 | struct drm_file *file_priv); |
2853 | struct drm_file *file_priv); |
2807 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2854 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2808 | struct drm_file *file); |
2855 | struct drm_file *file); |
2809 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
2856 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
2810 | struct drm_file *file); |
2857 | struct drm_file *file); |
2811 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2858 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2812 | struct drm_file *file_priv); |
2859 | struct drm_file *file_priv); |
2813 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2860 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2814 | struct drm_file *file_priv); |
2861 | struct drm_file *file_priv); |
2815 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2862 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2816 | struct drm_file *file_priv); |
2863 | struct drm_file *file_priv); |
2817 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
2864 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
2818 | struct drm_file *file_priv); |
2865 | struct drm_file *file_priv); |
2819 | int i915_gem_init_userptr(struct drm_device *dev); |
2866 | int i915_gem_init_userptr(struct drm_device *dev); |
2820 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2867 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2821 | struct drm_file *file); |
2868 | struct drm_file *file); |
2822 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2869 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2823 | struct drm_file *file_priv); |
2870 | struct drm_file *file_priv); |
2824 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2871 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2825 | struct drm_file *file_priv); |
2872 | struct drm_file *file_priv); |
2826 | void i915_gem_load(struct drm_device *dev); |
2873 | void i915_gem_load(struct drm_device *dev); |
2827 | void *i915_gem_object_alloc(struct drm_device *dev); |
2874 | void *i915_gem_object_alloc(struct drm_device *dev); |
2828 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
2875 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
2829 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2876 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2830 | const struct drm_i915_gem_object_ops *ops); |
2877 | const struct drm_i915_gem_object_ops *ops); |
2831 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2878 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2832 | size_t size); |
2879 | size_t size); |
2833 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2880 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2834 | struct drm_device *dev, const void *data, size_t size); |
2881 | struct drm_device *dev, const void *data, size_t size); |
2835 | void i915_gem_free_object(struct drm_gem_object *obj); |
2882 | void i915_gem_free_object(struct drm_gem_object *obj); |
2836 | void i915_gem_vma_destroy(struct i915_vma *vma); |
2883 | void i915_gem_vma_destroy(struct i915_vma *vma); |
2837 | 2884 | ||
2838 | /* Flags used by pin/bind&friends. */ |
2885 | /* Flags used by pin/bind&friends. */ |
2839 | #define PIN_MAPPABLE (1<<0) |
2886 | #define PIN_MAPPABLE (1<<0) |
2840 | #define PIN_NONBLOCK (1<<1) |
2887 | #define PIN_NONBLOCK (1<<1) |
2841 | #define PIN_GLOBAL (1<<2) |
2888 | #define PIN_GLOBAL (1<<2) |
2842 | #define PIN_OFFSET_BIAS (1<<3) |
2889 | #define PIN_OFFSET_BIAS (1<<3) |
2843 | #define PIN_USER (1<<4) |
2890 | #define PIN_USER (1<<4) |
2844 | #define PIN_UPDATE (1<<5) |
2891 | #define PIN_UPDATE (1<<5) |
2845 | #define PIN_ZONE_4G (1<<6) |
2892 | #define PIN_ZONE_4G (1<<6) |
2846 | #define PIN_HIGH (1<<7) |
2893 | #define PIN_HIGH (1<<7) |
- | 2894 | #define PIN_OFFSET_FIXED (1<<8) |
|
2847 | #define PIN_OFFSET_MASK (~4095) |
2895 | #define PIN_OFFSET_MASK (~4095) |
2848 | int __must_check |
2896 | int __must_check |
2849 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
2897 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
2850 | struct i915_address_space *vm, |
2898 | struct i915_address_space *vm, |
2851 | uint32_t alignment, |
2899 | uint32_t alignment, |
2852 | uint64_t flags); |
2900 | uint64_t flags); |
2853 | int __must_check |
2901 | int __must_check |
2854 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
2902 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
2855 | const struct i915_ggtt_view *view, |
2903 | const struct i915_ggtt_view *view, |
2856 | uint32_t alignment, |
2904 | uint32_t alignment, |
2857 | uint64_t flags); |
2905 | uint64_t flags); |
2858 | 2906 | ||
2859 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, |
2907 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, |
2860 | u32 flags); |
2908 | u32 flags); |
2861 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
2909 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); |
2862 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
2910 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
2863 | /* |
2911 | /* |
2864 | * BEWARE: Do not use the function below unless you can _absolutely_ |
2912 | * BEWARE: Do not use the function below unless you can _absolutely_ |
2865 | * _guarantee_ VMA in question is _not in use_ anywhere. |
2913 | * _guarantee_ VMA in question is _not in use_ anywhere. |
2866 | */ |
2914 | */ |
2867 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); |
2915 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); |
2868 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
2916 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
2869 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
2917 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
2870 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
2918 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
2871 | 2919 | ||
2872 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2920 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2873 | int *needs_clflush); |
2921 | int *needs_clflush); |
2874 | 2922 | ||
2875 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
2923 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
2876 | 2924 | ||
2877 | static inline int __sg_page_count(struct scatterlist *sg) |
2925 | static inline int __sg_page_count(struct scatterlist *sg) |
2878 | { |
2926 | { |
2879 | return sg->length >> PAGE_SHIFT; |
2927 | return sg->length >> PAGE_SHIFT; |
2880 | } |
2928 | } |
- | 2929 | ||
- | 2930 | struct page * |
|
- | 2931 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); |
|
2881 | 2932 | ||
2882 | static inline struct page * |
2933 | static inline struct page * |
2883 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2934 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2884 | { |
2935 | { |
2885 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2936 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2886 | return NULL; |
2937 | return NULL; |
2887 | 2938 | ||
2888 | if (n < obj->get_page.last) { |
2939 | if (n < obj->get_page.last) { |
2889 | obj->get_page.sg = obj->pages->sgl; |
2940 | obj->get_page.sg = obj->pages->sgl; |
2890 | obj->get_page.last = 0; |
2941 | obj->get_page.last = 0; |
2891 | } |
2942 | } |
2892 | 2943 | ||
2893 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2944 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2894 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); |
2945 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); |
2895 | if (unlikely(sg_is_chain(obj->get_page.sg))) |
2946 | if (unlikely(sg_is_chain(obj->get_page.sg))) |
2896 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); |
2947 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); |
2897 | } |
2948 | } |
2898 | 2949 | ||
2899 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
2950 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
2900 | } |
2951 | } |
2901 | 2952 | ||
2902 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2953 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2903 | { |
2954 | { |
2904 | BUG_ON(obj->pages == NULL); |
2955 | BUG_ON(obj->pages == NULL); |
2905 | obj->pages_pin_count++; |
2956 | obj->pages_pin_count++; |
2906 | } |
2957 | } |
2907 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
2958 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
2908 | { |
2959 | { |
2909 | BUG_ON(obj->pages_pin_count == 0); |
2960 | BUG_ON(obj->pages_pin_count == 0); |
2910 | obj->pages_pin_count--; |
2961 | obj->pages_pin_count--; |
2911 | } |
2962 | } |
2912 | 2963 | ||
2913 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2964 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2914 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2965 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2915 | struct intel_engine_cs *to, |
2966 | struct intel_engine_cs *to, |
2916 | struct drm_i915_gem_request **to_req); |
2967 | struct drm_i915_gem_request **to_req); |
2917 | void i915_vma_move_to_active(struct i915_vma *vma, |
2968 | void i915_vma_move_to_active(struct i915_vma *vma, |
2918 | struct drm_i915_gem_request *req); |
2969 | struct drm_i915_gem_request *req); |
2919 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2970 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2920 | struct drm_device *dev, |
2971 | struct drm_device *dev, |
2921 | struct drm_mode_create_dumb *args); |
2972 | struct drm_mode_create_dumb *args); |
2922 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2973 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2923 | uint32_t handle, uint64_t *offset); |
2974 | uint32_t handle, uint64_t *offset); |
2924 | /** |
2975 | /** |
2925 | * Returns true if seq1 is later than seq2. |
2976 | * Returns true if seq1 is later than seq2. |
2926 | */ |
2977 | */ |
2927 | static inline bool |
2978 | static inline bool |
2928 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
2979 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
2929 | { |
2980 | { |
2930 | return (int32_t)(seq1 - seq2) >= 0; |
2981 | return (int32_t)(seq1 - seq2) >= 0; |
2931 | } |
2982 | } |
2932 | 2983 | ||
2933 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
2984 | static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, |
2934 | bool lazy_coherency) |
2985 | bool lazy_coherency) |
2935 | { |
2986 | { |
2936 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
2987 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
2937 | return i915_seqno_passed(seqno, req->previous_seqno); |
2988 | return i915_seqno_passed(seqno, req->previous_seqno); |
2938 | } |
2989 | } |
2939 | 2990 | ||
2940 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2991 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2941 | bool lazy_coherency) |
2992 | bool lazy_coherency) |
2942 | { |
2993 | { |
2943 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
2994 | u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); |
2944 | return i915_seqno_passed(seqno, req->seqno); |
2995 | return i915_seqno_passed(seqno, req->seqno); |
2945 | } |
2996 | } |
2946 | 2997 | ||
2947 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2998 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2948 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
2999 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
2949 | 3000 | ||
2950 | struct drm_i915_gem_request * |
3001 | struct drm_i915_gem_request * |
2951 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
3002 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
2952 | 3003 | ||
2953 | bool i915_gem_retire_requests(struct drm_device *dev); |
3004 | bool i915_gem_retire_requests(struct drm_device *dev); |
2954 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
3005 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
2955 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
3006 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
2956 | bool interruptible); |
3007 | bool interruptible); |
2957 | 3008 | ||
2958 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
3009 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2959 | { |
3010 | { |
2960 | return unlikely(atomic_read(&error->reset_counter) |
3011 | return unlikely(atomic_read(&error->reset_counter) |
2961 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
3012 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
2962 | } |
3013 | } |
2963 | 3014 | ||
2964 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
3015 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
2965 | { |
3016 | { |
2966 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
3017 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2967 | } |
3018 | } |
2968 | 3019 | ||
2969 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
3020 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
2970 | { |
3021 | { |
2971 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
3022 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
2972 | } |
3023 | } |
2973 | 3024 | ||
2974 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
3025 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2975 | { |
3026 | { |
2976 | return dev_priv->gpu_error.stop_rings == 0 || |
3027 | return dev_priv->gpu_error.stop_rings == 0 || |
2977 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; |
3028 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; |
2978 | } |
3029 | } |
2979 | 3030 | ||
2980 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) |
3031 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) |
2981 | { |
3032 | { |
2982 | return dev_priv->gpu_error.stop_rings == 0 || |
3033 | return dev_priv->gpu_error.stop_rings == 0 || |
2983 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; |
3034 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; |
2984 | } |
3035 | } |
2985 | 3036 | ||
2986 | void i915_gem_reset(struct drm_device *dev); |
3037 | void i915_gem_reset(struct drm_device *dev); |
2987 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
3038 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
2988 | int __must_check i915_gem_init(struct drm_device *dev); |
3039 | int __must_check i915_gem_init(struct drm_device *dev); |
2989 | int i915_gem_init_rings(struct drm_device *dev); |
3040 | int i915_gem_init_rings(struct drm_device *dev); |
2990 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
3041 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
2991 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
3042 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
2992 | void i915_gem_init_swizzling(struct drm_device *dev); |
3043 | void i915_gem_init_swizzling(struct drm_device *dev); |
2993 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
3044 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2994 | int __must_check i915_gpu_idle(struct drm_device *dev); |
3045 | int __must_check i915_gpu_idle(struct drm_device *dev); |
2995 | int __must_check i915_gem_suspend(struct drm_device *dev); |
3046 | int __must_check i915_gem_suspend(struct drm_device *dev); |
2996 | void __i915_add_request(struct drm_i915_gem_request *req, |
3047 | void __i915_add_request(struct drm_i915_gem_request *req, |
2997 | struct drm_i915_gem_object *batch_obj, |
3048 | struct drm_i915_gem_object *batch_obj, |
2998 | bool flush_caches); |
3049 | bool flush_caches); |
2999 | #define i915_add_request(req) \ |
3050 | #define i915_add_request(req) \ |
3000 | __i915_add_request(req, NULL, true) |
3051 | __i915_add_request(req, NULL, true) |
3001 | #define i915_add_request_no_flush(req) \ |
3052 | #define i915_add_request_no_flush(req) \ |
3002 | __i915_add_request(req, NULL, false) |
3053 | __i915_add_request(req, NULL, false) |
3003 | int __i915_wait_request(struct drm_i915_gem_request *req, |
3054 | int __i915_wait_request(struct drm_i915_gem_request *req, |
3004 | unsigned reset_counter, |
3055 | unsigned reset_counter, |
3005 | bool interruptible, |
3056 | bool interruptible, |
3006 | s64 *timeout, |
3057 | s64 *timeout, |
3007 | struct intel_rps_client *rps); |
3058 | struct intel_rps_client *rps); |
3008 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
3059 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
3009 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
3060 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
3010 | int __must_check |
3061 | int __must_check |
3011 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3062 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
3012 | bool readonly); |
3063 | bool readonly); |
3013 | int __must_check |
3064 | int __must_check |
3014 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3065 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
3015 | bool write); |
3066 | bool write); |
3016 | int __must_check |
3067 | int __must_check |
3017 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3068 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
3018 | int __must_check |
3069 | int __must_check |
3019 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3070 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3020 | u32 alignment, |
3071 | u32 alignment, |
3021 | struct intel_engine_cs *pipelined, |
- | |
3022 | struct drm_i915_gem_request **pipelined_request, |
- | |
3023 | const struct i915_ggtt_view *view); |
3072 | const struct i915_ggtt_view *view); |
3024 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3073 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3025 | const struct i915_ggtt_view *view); |
3074 | const struct i915_ggtt_view *view); |
3026 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
3075 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
3027 | int align); |
3076 | int align); |
3028 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
3077 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
3029 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
3078 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
3030 | 3079 | ||
3031 | uint32_t |
3080 | uint32_t |
3032 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
3081 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
3033 | uint32_t |
3082 | uint32_t |
3034 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3083 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3035 | int tiling_mode, bool fenced); |
3084 | int tiling_mode, bool fenced); |
3036 | 3085 | ||
3037 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3086 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3038 | enum i915_cache_level cache_level); |
3087 | enum i915_cache_level cache_level); |
3039 | 3088 | ||
3040 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3089 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3041 | struct dma_buf *dma_buf); |
3090 | struct dma_buf *dma_buf); |
3042 | 3091 | ||
3043 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
3092 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
3044 | struct drm_gem_object *gem_obj, int flags); |
3093 | struct drm_gem_object *gem_obj, int flags); |
3045 | 3094 | ||
3046 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3095 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3047 | const struct i915_ggtt_view *view); |
3096 | const struct i915_ggtt_view *view); |
3048 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
3097 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
3049 | struct i915_address_space *vm); |
3098 | struct i915_address_space *vm); |
3050 | static inline u64 |
3099 | static inline u64 |
3051 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
3100 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
3052 | { |
3101 | { |
3053 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
3102 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
3054 | } |
3103 | } |
3055 | 3104 | ||
3056 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
3105 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
3057 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
3106 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
3058 | const struct i915_ggtt_view *view); |
3107 | const struct i915_ggtt_view *view); |
3059 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
3108 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
3060 | struct i915_address_space *vm); |
3109 | struct i915_address_space *vm); |
3061 | 3110 | ||
3062 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3111 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3063 | struct i915_address_space *vm); |
3112 | struct i915_address_space *vm); |
3064 | struct i915_vma * |
3113 | struct i915_vma * |
3065 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3114 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3066 | struct i915_address_space *vm); |
3115 | struct i915_address_space *vm); |
3067 | struct i915_vma * |
3116 | struct i915_vma * |
3068 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
3117 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
3069 | const struct i915_ggtt_view *view); |
3118 | const struct i915_ggtt_view *view); |
3070 | 3119 | ||
3071 | struct i915_vma * |
3120 | struct i915_vma * |
3072 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3121 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3073 | struct i915_address_space *vm); |
3122 | struct i915_address_space *vm); |
3074 | struct i915_vma * |
3123 | struct i915_vma * |
3075 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, |
3124 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, |
3076 | const struct i915_ggtt_view *view); |
3125 | const struct i915_ggtt_view *view); |
3077 | 3126 | ||
3078 | static inline struct i915_vma * |
3127 | static inline struct i915_vma * |
3079 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
3128 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
3080 | { |
3129 | { |
3081 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); |
3130 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); |
3082 | } |
3131 | } |
3083 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
3132 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
3084 | 3133 | ||
3085 | /* Some GGTT VM helpers */ |
3134 | /* Some GGTT VM helpers */ |
3086 | #define i915_obj_to_ggtt(obj) \ |
3135 | #define i915_obj_to_ggtt(obj) \ |
3087 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3136 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3088 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
3137 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
3089 | { |
3138 | { |
3090 | struct i915_address_space *ggtt = |
3139 | struct i915_address_space *ggtt = |
3091 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
3140 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
3092 | return vm == ggtt; |
3141 | return vm == ggtt; |
3093 | } |
3142 | } |
3094 | 3143 | ||
3095 | static inline struct i915_hw_ppgtt * |
3144 | static inline struct i915_hw_ppgtt * |
3096 | i915_vm_to_ppgtt(struct i915_address_space *vm) |
3145 | i915_vm_to_ppgtt(struct i915_address_space *vm) |
3097 | { |
3146 | { |
3098 | WARN_ON(i915_is_ggtt(vm)); |
3147 | WARN_ON(i915_is_ggtt(vm)); |
3099 | 3148 | ||
3100 | return container_of(vm, struct i915_hw_ppgtt, base); |
3149 | return container_of(vm, struct i915_hw_ppgtt, base); |
3101 | } |
3150 | } |
3102 | 3151 | ||
3103 | 3152 | ||
3104 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3153 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3105 | { |
3154 | { |
3106 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
3155 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
3107 | } |
3156 | } |
3108 | 3157 | ||
3109 | static inline unsigned long |
3158 | static inline unsigned long |
3110 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
3159 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
3111 | { |
3160 | { |
3112 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
3161 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
3113 | } |
3162 | } |
3114 | 3163 | ||
3115 | static inline int __must_check |
3164 | static inline int __must_check |
3116 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
3165 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
3117 | uint32_t alignment, |
3166 | uint32_t alignment, |
3118 | unsigned flags) |
3167 | unsigned flags) |
3119 | { |
3168 | { |
3120 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3169 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3121 | alignment, flags | PIN_GLOBAL); |
3170 | alignment, flags | PIN_GLOBAL); |
3122 | } |
3171 | } |
3123 | 3172 | ||
3124 | static inline int |
3173 | static inline int |
3125 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
3174 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
3126 | { |
3175 | { |
3127 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); |
3176 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); |
3128 | } |
3177 | } |
3129 | 3178 | ||
3130 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3179 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3131 | const struct i915_ggtt_view *view); |
3180 | const struct i915_ggtt_view *view); |
3132 | static inline void |
3181 | static inline void |
3133 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
3182 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
3134 | { |
3183 | { |
3135 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); |
3184 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); |
3136 | } |
3185 | } |
3137 | 3186 | ||
3138 | /* i915_gem_fence.c */ |
3187 | /* i915_gem_fence.c */ |
3139 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
3188 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
3140 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
3189 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
3141 | 3190 | ||
3142 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
3191 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
3143 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); |
3192 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); |
3144 | 3193 | ||
3145 | void i915_gem_restore_fences(struct drm_device *dev); |
3194 | void i915_gem_restore_fences(struct drm_device *dev); |
3146 | 3195 | ||
3147 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3196 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3148 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3197 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3149 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3198 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3150 | 3199 | ||
3151 | /* i915_gem_context.c */ |
3200 | /* i915_gem_context.c */ |
3152 | int __must_check i915_gem_context_init(struct drm_device *dev); |
3201 | int __must_check i915_gem_context_init(struct drm_device *dev); |
3153 | void i915_gem_context_fini(struct drm_device *dev); |
3202 | void i915_gem_context_fini(struct drm_device *dev); |
3154 | void i915_gem_context_reset(struct drm_device *dev); |
3203 | void i915_gem_context_reset(struct drm_device *dev); |
3155 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
3204 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
3156 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
3205 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
3157 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
3206 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
3158 | int i915_switch_context(struct drm_i915_gem_request *req); |
3207 | int i915_switch_context(struct drm_i915_gem_request *req); |
3159 | struct intel_context * |
3208 | struct intel_context * |
3160 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
3209 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
3161 | void i915_gem_context_free(struct kref *ctx_ref); |
3210 | void i915_gem_context_free(struct kref *ctx_ref); |
3162 | struct drm_i915_gem_object * |
3211 | struct drm_i915_gem_object * |
3163 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); |
3212 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); |
3164 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
3213 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
3165 | { |
3214 | { |
3166 | kref_get(&ctx->ref); |
3215 | kref_get(&ctx->ref); |
3167 | } |
3216 | } |
3168 | 3217 | ||
3169 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
3218 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
3170 | { |
3219 | { |
3171 | kref_put(&ctx->ref, i915_gem_context_free); |
3220 | kref_put(&ctx->ref, i915_gem_context_free); |
3172 | } |
3221 | } |
3173 | 3222 | ||
3174 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3223 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3175 | { |
3224 | { |
3176 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3225 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3177 | } |
3226 | } |
3178 | 3227 | ||
3179 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3228 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3180 | struct drm_file *file); |
3229 | struct drm_file *file); |
3181 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
3230 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
3182 | struct drm_file *file); |
3231 | struct drm_file *file); |
3183 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3232 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3184 | struct drm_file *file_priv); |
3233 | struct drm_file *file_priv); |
3185 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
3234 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
3186 | struct drm_file *file_priv); |
3235 | struct drm_file *file_priv); |
3187 | 3236 | ||
3188 | /* i915_gem_evict.c */ |
3237 | /* i915_gem_evict.c */ |
3189 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
3238 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
3190 | struct i915_address_space *vm, |
3239 | struct i915_address_space *vm, |
3191 | int min_size, |
3240 | int min_size, |
3192 | unsigned alignment, |
3241 | unsigned alignment, |
3193 | unsigned cache_level, |
3242 | unsigned cache_level, |
3194 | unsigned long start, |
3243 | unsigned long start, |
3195 | unsigned long end, |
3244 | unsigned long end, |
3196 | unsigned flags); |
3245 | unsigned flags); |
- | 3246 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); |
|
3197 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3247 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3198 | 3248 | ||
3199 | /* belongs in i915_gem_gtt.h */ |
3249 | /* belongs in i915_gem_gtt.h */ |
3200 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
3250 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
3201 | { |
3251 | { |
3202 | if (INTEL_INFO(dev)->gen < 6) |
3252 | if (INTEL_INFO(dev)->gen < 6) |
3203 | intel_gtt_chipset_flush(); |
3253 | intel_gtt_chipset_flush(); |
3204 | } |
3254 | } |
3205 | 3255 | ||
3206 | /* i915_gem_stolen.c */ |
3256 | /* i915_gem_stolen.c */ |
3207 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3257 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3208 | struct drm_mm_node *node, u64 size, |
3258 | struct drm_mm_node *node, u64 size, |
3209 | unsigned alignment); |
3259 | unsigned alignment); |
3210 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3260 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3211 | struct drm_mm_node *node, u64 size, |
3261 | struct drm_mm_node *node, u64 size, |
3212 | unsigned alignment, u64 start, |
3262 | unsigned alignment, u64 start, |
3213 | u64 end); |
3263 | u64 end); |
3214 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3264 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3215 | struct drm_mm_node *node); |
3265 | struct drm_mm_node *node); |
3216 | int i915_gem_init_stolen(struct drm_device *dev); |
3266 | int i915_gem_init_stolen(struct drm_device *dev); |
3217 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
3267 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
3218 | struct drm_i915_gem_object * |
3268 | struct drm_i915_gem_object * |
3219 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
3269 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
3220 | struct drm_i915_gem_object * |
3270 | struct drm_i915_gem_object * |
3221 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
3271 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
3222 | u32 stolen_offset, |
3272 | u32 stolen_offset, |
3223 | u32 gtt_offset, |
3273 | u32 gtt_offset, |
3224 | u32 size); |
3274 | u32 size); |
3225 | 3275 | ||
3226 | /* i915_gem_shrinker.c */ |
3276 | /* i915_gem_shrinker.c */ |
3227 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, |
3277 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, |
3228 | unsigned long target, |
3278 | unsigned long target, |
3229 | unsigned flags); |
3279 | unsigned flags); |
3230 | #define I915_SHRINK_PURGEABLE 0x1 |
3280 | #define I915_SHRINK_PURGEABLE 0x1 |
3231 | #define I915_SHRINK_UNBOUND 0x2 |
3281 | #define I915_SHRINK_UNBOUND 0x2 |
3232 | #define I915_SHRINK_BOUND 0x4 |
3282 | #define I915_SHRINK_BOUND 0x4 |
3233 | #define I915_SHRINK_ACTIVE 0x8 |
3283 | #define I915_SHRINK_ACTIVE 0x8 |
3234 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3284 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3235 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); |
3285 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); |
3236 | 3286 | ||
3237 | 3287 | ||
3238 | /* i915_gem_tiling.c */ |
3288 | /* i915_gem_tiling.c */ |
3239 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
3289 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
3240 | { |
3290 | { |
3241 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3291 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3242 | 3292 | ||
3243 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
3293 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
3244 | obj->tiling_mode != I915_TILING_NONE; |
3294 | obj->tiling_mode != I915_TILING_NONE; |
3245 | } |
3295 | } |
3246 | 3296 | ||
3247 | /* i915_gem_debug.c */ |
3297 | /* i915_gem_debug.c */ |
3248 | #if WATCH_LISTS |
3298 | #if WATCH_LISTS |
3249 | int i915_verify_lists(struct drm_device *dev); |
3299 | int i915_verify_lists(struct drm_device *dev); |
3250 | #else |
3300 | #else |
3251 | #define i915_verify_lists(dev) 0 |
3301 | #define i915_verify_lists(dev) 0 |
3252 | #endif |
3302 | #endif |
3253 | 3303 | ||
3254 | /* i915_debugfs.c */ |
3304 | /* i915_debugfs.c */ |
3255 | int i915_debugfs_init(struct drm_minor *minor); |
3305 | int i915_debugfs_init(struct drm_minor *minor); |
3256 | void i915_debugfs_cleanup(struct drm_minor *minor); |
3306 | void i915_debugfs_cleanup(struct drm_minor *minor); |
3257 | #ifdef CONFIG_DEBUG_FS |
3307 | #ifdef CONFIG_DEBUG_FS |
3258 | int i915_debugfs_connector_add(struct drm_connector *connector); |
3308 | int i915_debugfs_connector_add(struct drm_connector *connector); |
3259 | void intel_display_crc_init(struct drm_device *dev); |
3309 | void intel_display_crc_init(struct drm_device *dev); |
3260 | #else |
3310 | #else |
3261 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3311 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3262 | { return 0; } |
3312 | { return 0; } |
3263 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
3313 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
3264 | #endif |
3314 | #endif |
3265 | 3315 | ||
3266 | /* i915_gpu_error.c */ |
3316 | /* i915_gpu_error.c */ |
3267 | __printf(2, 3) |
3317 | __printf(2, 3) |
3268 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
3318 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
3269 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3319 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3270 | const struct i915_error_state_file_priv *error); |
3320 | const struct i915_error_state_file_priv *error); |
3271 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
3321 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
3272 | struct drm_i915_private *i915, |
3322 | struct drm_i915_private *i915, |
3273 | size_t count, loff_t pos); |
3323 | size_t count, loff_t pos); |
3274 | static inline void i915_error_state_buf_release( |
3324 | static inline void i915_error_state_buf_release( |
3275 | struct drm_i915_error_state_buf *eb) |
3325 | struct drm_i915_error_state_buf *eb) |
3276 | { |
3326 | { |
3277 | kfree(eb->buf); |
3327 | kfree(eb->buf); |
3278 | } |
3328 | } |
3279 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3329 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3280 | const char *error_msg); |
3330 | const char *error_msg); |
3281 | void i915_error_state_get(struct drm_device *dev, |
3331 | void i915_error_state_get(struct drm_device *dev, |
3282 | struct i915_error_state_file_priv *error_priv); |
3332 | struct i915_error_state_file_priv *error_priv); |
3283 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
3333 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
3284 | void i915_destroy_error_state(struct drm_device *dev); |
3334 | void i915_destroy_error_state(struct drm_device *dev); |
3285 | 3335 | ||
3286 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
3336 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
3287 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
3337 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
3288 | 3338 | ||
3289 | /* i915_cmd_parser.c */ |
3339 | /* i915_cmd_parser.c */ |
3290 | int i915_cmd_parser_get_version(void); |
3340 | int i915_cmd_parser_get_version(void); |
3291 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3341 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3292 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); |
3342 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); |
3293 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); |
3343 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); |
3294 | int i915_parse_cmds(struct intel_engine_cs *ring, |
3344 | int i915_parse_cmds(struct intel_engine_cs *ring, |
3295 | struct drm_i915_gem_object *batch_obj, |
3345 | struct drm_i915_gem_object *batch_obj, |
3296 | struct drm_i915_gem_object *shadow_batch_obj, |
3346 | struct drm_i915_gem_object *shadow_batch_obj, |
3297 | u32 batch_start_offset, |
3347 | u32 batch_start_offset, |
3298 | u32 batch_len, |
3348 | u32 batch_len, |
3299 | bool is_master); |
3349 | bool is_master); |
3300 | 3350 | ||
3301 | /* i915_suspend.c */ |
3351 | /* i915_suspend.c */ |
3302 | extern int i915_save_state(struct drm_device *dev); |
3352 | extern int i915_save_state(struct drm_device *dev); |
3303 | extern int i915_restore_state(struct drm_device *dev); |
3353 | extern int i915_restore_state(struct drm_device *dev); |
3304 | 3354 | ||
3305 | /* i915_sysfs.c */ |
3355 | /* i915_sysfs.c */ |
3306 | void i915_setup_sysfs(struct drm_device *dev_priv); |
3356 | void i915_setup_sysfs(struct drm_device *dev_priv); |
3307 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
3357 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
3308 | 3358 | ||
3309 | /* intel_i2c.c */ |
3359 | /* intel_i2c.c */ |
3310 | extern int intel_setup_gmbus(struct drm_device *dev); |
3360 | extern int intel_setup_gmbus(struct drm_device *dev); |
3311 | extern void intel_teardown_gmbus(struct drm_device *dev); |
3361 | extern void intel_teardown_gmbus(struct drm_device *dev); |
3312 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3362 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3313 | unsigned int pin); |
3363 | unsigned int pin); |
3314 | 3364 | ||
3315 | extern struct i2c_adapter * |
3365 | extern struct i2c_adapter * |
3316 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); |
3366 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); |
3317 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3367 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3318 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
3368 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
3319 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
3369 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
3320 | { |
3370 | { |
3321 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
3371 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
3322 | } |
3372 | } |
3323 | extern void intel_i2c_reset(struct drm_device *dev); |
3373 | extern void intel_i2c_reset(struct drm_device *dev); |
3324 | 3374 | ||
3325 | /* intel_bios.c */ |
3375 | /* intel_bios.c */ |
3326 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
3376 | int intel_bios_init(struct drm_i915_private *dev_priv); |
- | 3377 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
|
3327 | 3378 | ||
3328 | /* intel_opregion.c */ |
3379 | /* intel_opregion.c */ |
3329 | #ifdef CONFIG_ACPI |
3380 | #ifdef CONFIG_ACPI |
3330 | extern int intel_opregion_setup(struct drm_device *dev); |
3381 | extern int intel_opregion_setup(struct drm_device *dev); |
3331 | extern void intel_opregion_init(struct drm_device *dev); |
3382 | extern void intel_opregion_init(struct drm_device *dev); |
3332 | extern void intel_opregion_fini(struct drm_device *dev); |
3383 | extern void intel_opregion_fini(struct drm_device *dev); |
3333 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
3384 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
3334 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3385 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3335 | bool enable); |
3386 | bool enable); |
3336 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3387 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3337 | pci_power_t state); |
3388 | pci_power_t state); |
3338 | #else |
3389 | #else |
3339 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
3390 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
3340 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3391 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3341 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
3392 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
3342 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
3393 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
3343 | static inline int |
3394 | static inline int |
3344 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
3395 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
3345 | { |
3396 | { |
3346 | return 0; |
3397 | return 0; |
3347 | } |
3398 | } |
3348 | static inline int |
3399 | static inline int |
3349 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
3400 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
3350 | { |
3401 | { |
3351 | return 0; |
3402 | return 0; |
3352 | } |
3403 | } |
3353 | #endif |
3404 | #endif |
3354 | 3405 | ||
3355 | /* intel_acpi.c */ |
3406 | /* intel_acpi.c */ |
3356 | #ifdef CONFIG_ACPI |
3407 | #ifdef CONFIG_ACPI |
3357 | extern void intel_register_dsm_handler(void); |
3408 | extern void intel_register_dsm_handler(void); |
3358 | extern void intel_unregister_dsm_handler(void); |
3409 | extern void intel_unregister_dsm_handler(void); |
3359 | #else |
3410 | #else |
3360 | static inline void intel_register_dsm_handler(void) { return; } |
3411 | static inline void intel_register_dsm_handler(void) { return; } |
3361 | static inline void intel_unregister_dsm_handler(void) { return; } |
3412 | static inline void intel_unregister_dsm_handler(void) { return; } |
3362 | #endif /* CONFIG_ACPI */ |
3413 | #endif /* CONFIG_ACPI */ |
3363 | 3414 | ||
3364 | /* modesetting */ |
3415 | /* modesetting */ |
3365 | extern void intel_modeset_init_hw(struct drm_device *dev); |
3416 | extern void intel_modeset_init_hw(struct drm_device *dev); |
3366 | extern void intel_modeset_init(struct drm_device *dev); |
3417 | extern void intel_modeset_init(struct drm_device *dev); |
3367 | extern void intel_modeset_gem_init(struct drm_device *dev); |
3418 | extern void intel_modeset_gem_init(struct drm_device *dev); |
3368 | extern void intel_modeset_cleanup(struct drm_device *dev); |
3419 | extern void intel_modeset_cleanup(struct drm_device *dev); |
3369 | extern void intel_connector_unregister(struct intel_connector *); |
3420 | extern void intel_connector_unregister(struct intel_connector *); |
3370 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
3421 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
3371 | extern void intel_display_resume(struct drm_device *dev); |
3422 | extern void intel_display_resume(struct drm_device *dev); |
3372 | extern void i915_redisable_vga(struct drm_device *dev); |
3423 | extern void i915_redisable_vga(struct drm_device *dev); |
3373 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
3424 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
3374 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3425 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
3375 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3426 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3376 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
3427 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
3377 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3428 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3378 | bool enable); |
3429 | bool enable); |
3379 | extern void intel_detect_pch(struct drm_device *dev); |
3430 | extern void intel_detect_pch(struct drm_device *dev); |
3380 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
- | |
3381 | extern int intel_enable_rc6(const struct drm_device *dev); |
3431 | extern int intel_enable_rc6(const struct drm_device *dev); |
3382 | 3432 | ||
3383 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
3433 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
3384 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3434 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3385 | struct drm_file *file); |
3435 | struct drm_file *file); |
3386 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3436 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3387 | struct drm_file *file); |
3437 | struct drm_file *file); |
3388 | 3438 | ||
3389 | /* overlay */ |
3439 | /* overlay */ |
3390 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
3440 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
3391 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3441 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3392 | struct intel_overlay_error_state *error); |
3442 | struct intel_overlay_error_state *error); |
3393 | 3443 | ||
3394 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
3444 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
3395 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
3445 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
3396 | struct drm_device *dev, |
3446 | struct drm_device *dev, |
3397 | struct intel_display_error_state *error); |
3447 | struct intel_display_error_state *error); |
3398 | 3448 | ||
3399 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3449 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3400 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); |
3450 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); |
3401 | 3451 | ||
3402 | /* intel_sideband.c */ |
3452 | /* intel_sideband.c */ |
3403 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3453 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3404 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
3454 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
3405 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
3455 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
3406 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3456 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3407 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3457 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3408 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3458 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3409 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3459 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3410 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
3460 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
3411 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3461 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3412 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3462 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3413 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3463 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3414 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3464 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3415 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3465 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3416 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3466 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3417 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
3467 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
3418 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3468 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3419 | enum intel_sbi_destination destination); |
3469 | enum intel_sbi_destination destination); |
3420 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
3470 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
3421 | enum intel_sbi_destination destination); |
3471 | enum intel_sbi_destination destination); |
3422 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3472 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3423 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3473 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
3424 | 3474 | ||
3425 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3475 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3426 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); |
3476 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); |
3427 | 3477 | ||
3428 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3478 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3429 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
3479 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
3430 | 3480 | ||
3431 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
3481 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
3432 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
3482 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
3433 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
3483 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
3434 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
3484 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
3435 | 3485 | ||
3436 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
3486 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
3437 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
3487 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
3438 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
3488 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
3439 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
3489 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
3440 | 3490 | ||
3441 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3491 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3442 | * will be implemented using 2 32-bit writes in an arbitrary order with |
3492 | * will be implemented using 2 32-bit writes in an arbitrary order with |
3443 | * an arbitrary delay between them. This can cause the hardware to |
3493 | * an arbitrary delay between them. This can cause the hardware to |
3444 | * act upon the intermediate value, possibly leading to corruption and |
3494 | * act upon the intermediate value, possibly leading to corruption and |
3445 | * machine death. You have been warned. |
3495 | * machine death. You have been warned. |
3446 | */ |
3496 | */ |
3447 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3497 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3448 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
3498 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
3449 | 3499 | ||
3450 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3500 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3451 | u32 upper, lower, old_upper, loop = 0; \ |
3501 | u32 upper, lower, old_upper, loop = 0; \ |
3452 | upper = I915_READ(upper_reg); \ |
3502 | upper = I915_READ(upper_reg); \ |
3453 | do { \ |
3503 | do { \ |
3454 | old_upper = upper; \ |
3504 | old_upper = upper; \ |
3455 | lower = I915_READ(lower_reg); \ |
3505 | lower = I915_READ(lower_reg); \ |
3456 | upper = I915_READ(upper_reg); \ |
3506 | upper = I915_READ(upper_reg); \ |
3457 | } while (upper != old_upper && loop++ < 2); \ |
3507 | } while (upper != old_upper && loop++ < 2); \ |
3458 | (u64)upper << 32 | lower; }) |
3508 | (u64)upper << 32 | lower; }) |
3459 | 3509 | ||
3460 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3510 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3461 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
3511 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
- | 3512 | ||
- | 3513 | #define __raw_read(x, s) \ |
|
- | 3514 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ |
|
- | 3515 | i915_reg_t reg) \ |
|
- | 3516 | { \ |
|
- | 3517 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
|
- | 3518 | } |
|
- | 3519 | ||
- | 3520 | #define __raw_write(x, s) \ |
|
- | 3521 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ |
|
- | 3522 | i915_reg_t reg, uint##x##_t val) \ |
|
- | 3523 | { \ |
|
- | 3524 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
|
- | 3525 | } |
|
- | 3526 | __raw_read(8, b) |
|
- | 3527 | __raw_read(16, w) |
|
- | 3528 | __raw_read(32, l) |
|
- | 3529 | __raw_read(64, q) |
|
- | 3530 | ||
- | 3531 | __raw_write(8, b) |
|
- | 3532 | __raw_write(16, w) |
|
- | 3533 | __raw_write(32, l) |
|
- | 3534 | __raw_write(64, q) |
|
- | 3535 | ||
- | 3536 | #undef __raw_read |
|
- | 3537 | #undef __raw_write |
|
3462 | 3538 | ||
3463 | /* These are untraced mmio-accessors that are only valid to be used inside |
3539 | /* These are untraced mmio-accessors that are only valid to be used inside |
3464 | * criticial sections inside IRQ handlers where forcewake is explicitly |
3540 | * criticial sections inside IRQ handlers where forcewake is explicitly |
3465 | * controlled. |
3541 | * controlled. |
3466 | * Think twice, and think again, before using these. |
3542 | * Think twice, and think again, before using these. |
3467 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and |
3543 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and |
3468 | * intel_uncore_forcewake_irqunlock(). |
3544 | * intel_uncore_forcewake_irqunlock(). |
3469 | */ |
3545 | */ |
3470 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) |
3546 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3471 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) |
3547 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) |
3472 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3548 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3473 | 3549 | ||
3474 | /* "Broadcast RGB" property */ |
3550 | /* "Broadcast RGB" property */ |
3475 | #define INTEL_BROADCAST_RGB_AUTO 0 |
3551 | #define INTEL_BROADCAST_RGB_AUTO 0 |
3476 | #define INTEL_BROADCAST_RGB_FULL 1 |
3552 | #define INTEL_BROADCAST_RGB_FULL 1 |
3477 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
3553 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
3478 | 3554 | ||
3479 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3555 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) |
3480 | { |
3556 | { |
3481 | if (IS_VALLEYVIEW(dev)) |
3557 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
3482 | return VLV_VGACNTRL; |
3558 | return VLV_VGACNTRL; |
3483 | else if (INTEL_INFO(dev)->gen >= 5) |
3559 | else if (INTEL_INFO(dev)->gen >= 5) |
3484 | return CPU_VGACNTRL; |
3560 | return CPU_VGACNTRL; |
3485 | else |
3561 | else |
3486 | return VGACNTRL; |
3562 | return VGACNTRL; |
3487 | } |
3563 | } |
3488 | 3564 | ||
3489 | static inline void __user *to_user_ptr(u64 address) |
3565 | static inline void __user *to_user_ptr(u64 address) |
3490 | { |
3566 | { |
3491 | return (void __user *)(uintptr_t)address; |
3567 | return (void __user *)(uintptr_t)address; |
3492 | } |
3568 | } |
3493 | 3569 | ||
3494 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3570 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3495 | { |
3571 | { |
3496 | unsigned long j = msecs_to_jiffies(m); |
3572 | unsigned long j = msecs_to_jiffies(m); |
3497 | 3573 | ||
3498 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
3574 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
3499 | } |
3575 | } |
3500 | 3576 | ||
3501 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3577 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3502 | { |
3578 | { |
3503 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
3579 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
3504 | } |
3580 | } |
3505 | 3581 | ||
3506 | static inline unsigned long |
3582 | static inline unsigned long |
3507 | timespec_to_jiffies_timeout(const struct timespec *value) |
3583 | timespec_to_jiffies_timeout(const struct timespec *value) |
3508 | { |
3584 | { |
3509 | unsigned long j = timespec_to_jiffies(value); |
3585 | unsigned long j = timespec_to_jiffies(value); |
3510 | 3586 | ||
3511 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
3587 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
3512 | } |
3588 | } |
3513 | 3589 | ||
3514 | /* |
3590 | /* |
3515 | * If you need to wait X milliseconds between events A and B, but event B |
3591 | * If you need to wait X milliseconds between events A and B, but event B |
3516 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of |
3592 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of |
3517 | * when event A happened, then just before event B you call this function and |
3593 | * when event A happened, then just before event B you call this function and |
3518 | * pass the timestamp as the first argument, and X as the second argument. |
3594 | * pass the timestamp as the first argument, and X as the second argument. |
3519 | */ |
3595 | */ |
3520 | static inline void |
3596 | static inline void |
3521 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) |
3597 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) |
3522 | { |
3598 | { |
3523 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
3599 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
3524 | 3600 | ||
3525 | /* |
3601 | /* |
3526 | * Don't re-read the value of "jiffies" every time since it may change |
3602 | * Don't re-read the value of "jiffies" every time since it may change |
3527 | * behind our back and break the math. |
3603 | * behind our back and break the math. |
3528 | */ |
3604 | */ |
3529 | tmp_jiffies = jiffies; |
3605 | tmp_jiffies = jiffies; |
3530 | target_jiffies = timestamp_jiffies + |
3606 | target_jiffies = timestamp_jiffies + |
3531 | msecs_to_jiffies_timeout(to_wait_ms); |
3607 | msecs_to_jiffies_timeout(to_wait_ms); |
3532 | 3608 | ||
3533 | if (time_after(target_jiffies, tmp_jiffies)) { |
3609 | if (time_after(target_jiffies, tmp_jiffies)) { |
3534 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3610 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3535 | delay(remaining_jiffies); |
3611 | delay(remaining_jiffies); |
3536 | } |
3612 | } |
3537 | } |
3613 | } |
3538 | 3614 | ||
3539 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3615 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3540 | struct drm_i915_gem_request *req) |
3616 | struct drm_i915_gem_request *req) |
3541 | { |
3617 | { |
3542 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) |
3618 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) |
3543 | i915_gem_request_assign(&ring->trace_irq_req, req); |
3619 | i915_gem_request_assign(&ring->trace_irq_req, req); |
3544 | } |
3620 | } |
- | 3621 | ||
- | 3622 | #include "intel_drv.h" |
|
3545 | 3623 | ||
3546 | #endif><>>>=>>7) |
3624 | #endif><>>>=>>8) |
3547 | #define><7) |
3625 | #define><8) |
3548 | #define>6) |
3626 | #define>7) |
3549 | #define><6) |
3627 | #define><7) |
3550 | #define>5) |
3628 | #define>6) |
3551 | #define><5) |
3629 | #define><6) |
3552 | #define>4) |
3630 | #define>5) |
3553 | #define><4) |
3631 | #define><5) |
3554 | #define>3) |
3632 | #define>4) |
3555 | #define><3) |
3633 | #define><4) |
3556 | #define>2) |
3634 | #define>3) |
3557 | #define><2) |
3635 | #define><3) |
3558 | #define>1) |
3636 | #define>2) |
3559 | #define><1) |
3637 | #define><2) |
3560 | #define>0) |
3638 | #define>1) |
3561 | #define><0) |
3639 | #define><1) |
3562 | #define>> |
3640 | #define>0) |
3563 | #define> |
3641 | #define><0) |
3564 | #define> |
3642 | #define>> |
3565 | #define> |
3643 | #define> |
3566 | #define> |
3644 | #define> |
3567 | #define> |
3645 | #define> |
3568 | #define> |
3646 | #define> |
3569 | #define> |
3647 | #define> |
3570 | #define> |
3648 | #define> |
3571 | #define> |
3649 | #define> |
3572 | #define>5) |
3650 | #define> |
3573 | 3651 | #define> |
|
3574 | ><5) |
3652 | #define>=>5) |
3575 | 3653 | ||
3576 | >4) |
3654 | ><5) |
3577 | #define><4) |
3655 | |
3578 | #define>3) |
3656 | >4) |
3579 | #define><3) |
3657 | #define><4) |
3580 | #define>2) |
3658 | #define>3) |
3581 | #define><2) |
3659 | #define><3) |
3582 | #define>1) |
3660 | #define>2) |
3583 | #define><1) |
3661 | #define><2) |
3584 | #define>0) |
3662 | #define>1) |
3585 | #define><0) |
3663 | #define><1) |
3586 | #define>><>><>><>><>><>>><>><>><>5) |
3664 | #define>0) |
3587 | 3665 | #define><0) |
|
3588 | struct><5) |
3666 | #define>><>><>><>><>><>>><>><>><>5) |
3589 | 3667 | ||
3590 | struct>4) |
3668 | struct><5) |
3591 | #define><4) |
3669 | |
3592 | #define>3) |
3670 | struct>4) |
3593 | #define><3) |
3671 | #define><4) |
3594 | #define>2) |
3672 | #define>3) |
3595 | #define><2) |
3673 | #define><3) |
3596 | #define>1) |
3674 | #define>2) |
3597 | #define><1) |
3675 | #define><2) |
3598 | #define>0) |
3676 | #define>1) |
3599 | #define><0) |
3677 | #define><1) |
3600 | #define>0) |
3678 | #define>0) |
3601 | /** |
3679 | #define><0) |
3602 | ><0) |
3680 | #define>0) |
3603 | /** |
3681 | /** |
3604 | >><>>><>><>><>><>>>>>> |
3682 | ><0) |
- | 3683 | /** |
|
- | 3684 | >><>><>>><>><>><>><>>>>>> |