Rev 6082 | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6082 | Rev 6936 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright © 2008 Keith Packard |
2 | * Copyright © 2008 Keith Packard |
3 | * |
3 | * |
4 | * Permission to use, copy, modify, distribute, and sell this software and its |
4 | * Permission to use, copy, modify, distribute, and sell this software and its |
5 | * documentation for any purpose is hereby granted without fee, provided that |
5 | * documentation for any purpose is hereby granted without fee, provided that |
6 | * the above copyright notice appear in all copies and that both that copyright |
6 | * the above copyright notice appear in all copies and that both that copyright |
7 | * notice and this permission notice appear in supporting documentation, and |
7 | * notice and this permission notice appear in supporting documentation, and |
8 | * that the name of the copyright holders not be used in advertising or |
8 | * that the name of the copyright holders not be used in advertising or |
9 | * publicity pertaining to distribution of the software without specific, |
9 | * publicity pertaining to distribution of the software without specific, |
10 | * written prior permission. The copyright holders make no representations |
10 | * written prior permission. The copyright holders make no representations |
11 | * about the suitability of this software for any purpose. It is provided "as |
11 | * about the suitability of this software for any purpose. It is provided "as |
12 | * is" without express or implied warranty. |
12 | * is" without express or implied warranty. |
13 | * |
13 | * |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
20 | * OF THIS SOFTWARE. |
20 | * OF THIS SOFTWARE. |
21 | */ |
21 | */ |
22 | 22 | ||
23 | #ifndef _DRM_DP_HELPER_H_ |
23 | #ifndef _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ |
25 | 25 | ||
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include |
28 | #include |
29 | 29 | ||
30 | /* |
30 | /* |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
33 | * 1.0 devices basically don't exist in the wild. |
33 | * 1.0 devices basically don't exist in the wild. |
34 | * |
34 | * |
35 | * Abbreviations, in chronological order: |
35 | * Abbreviations, in chronological order: |
36 | * |
36 | * |
37 | * eDP: Embedded DisplayPort version 1 |
37 | * eDP: Embedded DisplayPort version 1 |
38 | * DPI: DisplayPort Interoperability Guideline v1.1a |
38 | * DPI: DisplayPort Interoperability Guideline v1.1a |
39 | * 1.2: DisplayPort 1.2 |
39 | * 1.2: DisplayPort 1.2 |
40 | * MST: Multistream Transport - part of DP 1.2a |
40 | * MST: Multistream Transport - part of DP 1.2a |
41 | * |
41 | * |
42 | * 1.2 formally includes both eDP and DPI definitions. |
42 | * 1.2 formally includes both eDP and DPI definitions. |
43 | */ |
43 | */ |
44 | 44 | ||
45 | #define DP_AUX_MAX_PAYLOAD_BYTES 16 |
45 | #define DP_AUX_MAX_PAYLOAD_BYTES 16 |
46 | 46 | ||
47 | #define DP_AUX_I2C_WRITE 0x0 |
47 | #define DP_AUX_I2C_WRITE 0x0 |
48 | #define DP_AUX_I2C_READ 0x1 |
48 | #define DP_AUX_I2C_READ 0x1 |
49 | #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 |
49 | #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 |
50 | #define DP_AUX_I2C_MOT 0x4 |
50 | #define DP_AUX_I2C_MOT 0x4 |
51 | #define DP_AUX_NATIVE_WRITE 0x8 |
51 | #define DP_AUX_NATIVE_WRITE 0x8 |
52 | #define DP_AUX_NATIVE_READ 0x9 |
52 | #define DP_AUX_NATIVE_READ 0x9 |
53 | 53 | ||
54 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
54 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
55 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
55 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
56 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
56 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
57 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
57 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
58 | 58 | ||
59 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
59 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
60 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
60 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
61 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
61 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
62 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
62 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
63 | 63 | ||
64 | /* AUX CH addresses */ |
64 | /* AUX CH addresses */ |
65 | /* DPCD */ |
65 | /* DPCD */ |
66 | #define DP_DPCD_REV 0x000 |
66 | #define DP_DPCD_REV 0x000 |
67 | 67 | ||
68 | #define DP_MAX_LINK_RATE 0x001 |
68 | #define DP_MAX_LINK_RATE 0x001 |
69 | 69 | ||
70 | #define DP_MAX_LANE_COUNT 0x002 |
70 | #define DP_MAX_LANE_COUNT 0x002 |
71 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
71 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
72 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
72 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
73 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
73 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
74 | 74 | ||
75 | #define DP_MAX_DOWNSPREAD 0x003 |
75 | #define DP_MAX_DOWNSPREAD 0x003 |
76 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
76 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
77 | 77 | ||
78 | #define DP_NORP 0x004 |
78 | #define DP_NORP 0x004 |
79 | 79 | ||
80 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
80 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
81 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
81 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
82 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
82 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
83 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
83 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
84 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
84 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
85 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
85 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
86 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
86 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
87 | # define DP_FORMAT_CONVERSION (1 << 3) |
87 | # define DP_FORMAT_CONVERSION (1 << 3) |
88 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
88 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
89 | 89 | ||
90 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
90 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
91 | 91 | ||
92 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
92 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
93 | # define DP_PORT_COUNT_MASK 0x0f |
93 | # define DP_PORT_COUNT_MASK 0x0f |
94 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
94 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
95 | # define DP_OUI_SUPPORT (1 << 7) |
95 | # define DP_OUI_SUPPORT (1 << 7) |
96 | 96 | ||
97 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
97 | #define DP_RECEIVE_PORT_0_CAP_0 0x008 |
98 | # define DP_LOCAL_EDID_PRESENT (1 << 1) |
98 | # define DP_LOCAL_EDID_PRESENT (1 << 1) |
99 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) |
99 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) |
100 | 100 | ||
101 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 |
101 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 |
102 | 102 | ||
103 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a |
103 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a |
104 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b |
104 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b |
105 | 105 | ||
106 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
106 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
107 | # define DP_I2C_SPEED_1K 0x01 |
107 | # define DP_I2C_SPEED_1K 0x01 |
108 | # define DP_I2C_SPEED_5K 0x02 |
108 | # define DP_I2C_SPEED_5K 0x02 |
109 | # define DP_I2C_SPEED_10K 0x04 |
109 | # define DP_I2C_SPEED_10K 0x04 |
110 | # define DP_I2C_SPEED_100K 0x08 |
110 | # define DP_I2C_SPEED_100K 0x08 |
111 | # define DP_I2C_SPEED_400K 0x10 |
111 | # define DP_I2C_SPEED_400K 0x10 |
112 | # define DP_I2C_SPEED_1M 0x20 |
112 | # define DP_I2C_SPEED_1M 0x20 |
113 | 113 | ||
114 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
114 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
115 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
115 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) |
116 | # define DP_FRAMING_CHANGE_CAP (1 << 1) |
116 | # define DP_FRAMING_CHANGE_CAP (1 << 1) |
117 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
117 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ |
118 | 118 | ||
119 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
119 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
120 | 120 | ||
121 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
121 | #define DP_ADAPTER_CAP 0x00f /* 1.2 */ |
122 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) |
122 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) |
123 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) |
123 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) |
124 | 124 | ||
125 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
125 | #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ |
126 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ |
126 | # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ |
127 | 127 | ||
128 | /* Multiple stream transport */ |
128 | /* Multiple stream transport */ |
129 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
129 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
130 | # define DP_FAUX_CAP_1 (1 << 0) |
130 | # define DP_FAUX_CAP_1 (1 << 0) |
131 | 131 | ||
132 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
132 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
133 | # define DP_MST_CAP (1 << 0) |
133 | # define DP_MST_CAP (1 << 0) |
134 | 134 | ||
135 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
135 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ |
136 | 136 | ||
137 | /* AV_SYNC_DATA_BLOCK 1.2 */ |
137 | /* AV_SYNC_DATA_BLOCK 1.2 */ |
138 | #define DP_AV_GRANULARITY 0x023 |
138 | #define DP_AV_GRANULARITY 0x023 |
139 | # define DP_AG_FACTOR_MASK (0xf << 0) |
139 | # define DP_AG_FACTOR_MASK (0xf << 0) |
140 | # define DP_AG_FACTOR_3MS (0 << 0) |
140 | # define DP_AG_FACTOR_3MS (0 << 0) |
141 | # define DP_AG_FACTOR_2MS (1 << 0) |
141 | # define DP_AG_FACTOR_2MS (1 << 0) |
142 | # define DP_AG_FACTOR_1MS (2 << 0) |
142 | # define DP_AG_FACTOR_1MS (2 << 0) |
143 | # define DP_AG_FACTOR_500US (3 << 0) |
143 | # define DP_AG_FACTOR_500US (3 << 0) |
144 | # define DP_AG_FACTOR_200US (4 << 0) |
144 | # define DP_AG_FACTOR_200US (4 << 0) |
145 | # define DP_AG_FACTOR_100US (5 << 0) |
145 | # define DP_AG_FACTOR_100US (5 << 0) |
146 | # define DP_AG_FACTOR_10US (6 << 0) |
146 | # define DP_AG_FACTOR_10US (6 << 0) |
147 | # define DP_AG_FACTOR_1US (7 << 0) |
147 | # define DP_AG_FACTOR_1US (7 << 0) |
148 | # define DP_VG_FACTOR_MASK (0xf << 4) |
148 | # define DP_VG_FACTOR_MASK (0xf << 4) |
149 | # define DP_VG_FACTOR_3MS (0 << 4) |
149 | # define DP_VG_FACTOR_3MS (0 << 4) |
150 | # define DP_VG_FACTOR_2MS (1 << 4) |
150 | # define DP_VG_FACTOR_2MS (1 << 4) |
151 | # define DP_VG_FACTOR_1MS (2 << 4) |
151 | # define DP_VG_FACTOR_1MS (2 << 4) |
152 | # define DP_VG_FACTOR_500US (3 << 4) |
152 | # define DP_VG_FACTOR_500US (3 << 4) |
153 | # define DP_VG_FACTOR_200US (4 << 4) |
153 | # define DP_VG_FACTOR_200US (4 << 4) |
154 | # define DP_VG_FACTOR_100US (5 << 4) |
154 | # define DP_VG_FACTOR_100US (5 << 4) |
155 | 155 | ||
156 | #define DP_AUD_DEC_LAT0 0x024 |
156 | #define DP_AUD_DEC_LAT0 0x024 |
157 | #define DP_AUD_DEC_LAT1 0x025 |
157 | #define DP_AUD_DEC_LAT1 0x025 |
158 | 158 | ||
159 | #define DP_AUD_PP_LAT0 0x026 |
159 | #define DP_AUD_PP_LAT0 0x026 |
160 | #define DP_AUD_PP_LAT1 0x027 |
160 | #define DP_AUD_PP_LAT1 0x027 |
161 | 161 | ||
162 | #define DP_VID_INTER_LAT 0x028 |
162 | #define DP_VID_INTER_LAT 0x028 |
163 | 163 | ||
164 | #define DP_VID_PROG_LAT 0x029 |
164 | #define DP_VID_PROG_LAT 0x029 |
165 | 165 | ||
166 | #define DP_REP_LAT 0x02a |
166 | #define DP_REP_LAT 0x02a |
167 | 167 | ||
168 | #define DP_AUD_DEL_INS0 0x02b |
168 | #define DP_AUD_DEL_INS0 0x02b |
169 | #define DP_AUD_DEL_INS1 0x02c |
169 | #define DP_AUD_DEL_INS1 0x02c |
170 | #define DP_AUD_DEL_INS2 0x02d |
170 | #define DP_AUD_DEL_INS2 0x02d |
171 | /* End of AV_SYNC_DATA_BLOCK */ |
171 | /* End of AV_SYNC_DATA_BLOCK */ |
172 | 172 | ||
173 | #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ |
173 | #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ |
174 | # define DP_ALPM_CAP (1 << 0) |
174 | # define DP_ALPM_CAP (1 << 0) |
175 | 175 | ||
176 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ |
176 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ |
177 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0) |
177 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0) |
178 | 178 | ||
179 | #define DP_GUID 0x030 /* 1.2 */ |
179 | #define DP_GUID 0x030 /* 1.2 */ |
180 | 180 | ||
181 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
181 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
182 | # define DP_PSR_IS_SUPPORTED 1 |
182 | # define DP_PSR_IS_SUPPORTED 1 |
183 | # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ |
183 | # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ |
184 | 184 | ||
185 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
185 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
186 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
186 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
187 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
187 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
188 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
188 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
189 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
189 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
190 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
190 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
191 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
191 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
192 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
192 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
193 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
193 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
194 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
194 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
195 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
195 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
196 | 196 | ||
197 | /* |
197 | /* |
198 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
198 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
199 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
199 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
200 | * each port's descriptor is one byte wide. If it was set, each port's is |
200 | * each port's descriptor is one byte wide. If it was set, each port's is |
201 | * four bytes wide, starting with the one byte from the base info. As of |
201 | * four bytes wide, starting with the one byte from the base info. As of |
202 | * DP interop v1.1a only VGA defines additional detail. |
202 | * DP interop v1.1a only VGA defines additional detail. |
203 | */ |
203 | */ |
204 | 204 | ||
205 | /* offset 0 */ |
205 | /* offset 0 */ |
206 | #define DP_DOWNSTREAM_PORT_0 0x80 |
206 | #define DP_DOWNSTREAM_PORT_0 0x80 |
207 | # define DP_DS_PORT_TYPE_MASK (7 << 0) |
207 | # define DP_DS_PORT_TYPE_MASK (7 << 0) |
208 | # define DP_DS_PORT_TYPE_DP 0 |
208 | # define DP_DS_PORT_TYPE_DP 0 |
209 | # define DP_DS_PORT_TYPE_VGA 1 |
209 | # define DP_DS_PORT_TYPE_VGA 1 |
210 | # define DP_DS_PORT_TYPE_DVI 2 |
210 | # define DP_DS_PORT_TYPE_DVI 2 |
211 | # define DP_DS_PORT_TYPE_HDMI 3 |
211 | # define DP_DS_PORT_TYPE_HDMI 3 |
212 | # define DP_DS_PORT_TYPE_NON_EDID 4 |
212 | # define DP_DS_PORT_TYPE_NON_EDID 4 |
213 | # define DP_DS_PORT_HPD (1 << 3) |
213 | # define DP_DS_PORT_HPD (1 << 3) |
214 | /* offset 1 for VGA is maximum megapixels per second / 8 */ |
214 | /* offset 1 for VGA is maximum megapixels per second / 8 */ |
215 | /* offset 2 */ |
215 | /* offset 2 */ |
216 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
216 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
217 | # define DP_DS_VGA_8BPC 0 |
217 | # define DP_DS_VGA_8BPC 0 |
218 | # define DP_DS_VGA_10BPC 1 |
218 | # define DP_DS_VGA_10BPC 1 |
219 | # define DP_DS_VGA_12BPC 2 |
219 | # define DP_DS_VGA_12BPC 2 |
220 | # define DP_DS_VGA_16BPC 3 |
220 | # define DP_DS_VGA_16BPC 3 |
221 | 221 | ||
222 | /* link configuration */ |
222 | /* link configuration */ |
223 | #define DP_LINK_BW_SET 0x100 |
223 | #define DP_LINK_BW_SET 0x100 |
224 | # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ |
224 | # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ |
225 | # define DP_LINK_BW_1_62 0x06 |
225 | # define DP_LINK_BW_1_62 0x06 |
226 | # define DP_LINK_BW_2_7 0x0a |
226 | # define DP_LINK_BW_2_7 0x0a |
227 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
227 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
228 | 228 | ||
229 | #define DP_LANE_COUNT_SET 0x101 |
229 | #define DP_LANE_COUNT_SET 0x101 |
230 | # define DP_LANE_COUNT_MASK 0x0f |
230 | # define DP_LANE_COUNT_MASK 0x0f |
231 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
231 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
232 | 232 | ||
233 | #define DP_TRAINING_PATTERN_SET 0x102 |
233 | #define DP_TRAINING_PATTERN_SET 0x102 |
234 | # define DP_TRAINING_PATTERN_DISABLE 0 |
234 | # define DP_TRAINING_PATTERN_DISABLE 0 |
235 | # define DP_TRAINING_PATTERN_1 1 |
235 | # define DP_TRAINING_PATTERN_1 1 |
236 | # define DP_TRAINING_PATTERN_2 2 |
236 | # define DP_TRAINING_PATTERN_2 2 |
237 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
237 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
238 | # define DP_TRAINING_PATTERN_MASK 0x3 |
238 | # define DP_TRAINING_PATTERN_MASK 0x3 |
239 | 239 | ||
240 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
240 | /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ |
241 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) |
241 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) |
242 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) |
242 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) |
243 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) |
243 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) |
244 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) |
244 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) |
245 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) |
245 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) |
246 | 246 | ||
247 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
247 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
248 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
248 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
249 | 249 | ||
250 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
250 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
251 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
251 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
252 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
252 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
253 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
253 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
254 | 254 | ||
255 | #define DP_TRAINING_LANE0_SET 0x103 |
255 | #define DP_TRAINING_LANE0_SET 0x103 |
256 | #define DP_TRAINING_LANE1_SET 0x104 |
256 | #define DP_TRAINING_LANE1_SET 0x104 |
257 | #define DP_TRAINING_LANE2_SET 0x105 |
257 | #define DP_TRAINING_LANE2_SET 0x105 |
258 | #define DP_TRAINING_LANE3_SET 0x106 |
258 | #define DP_TRAINING_LANE3_SET 0x106 |
259 | 259 | ||
260 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
260 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
261 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
261 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
262 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
262 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
263 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
263 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
264 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
264 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
265 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
265 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
266 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
266 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
267 | 267 | ||
268 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
268 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
269 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
269 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
270 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
270 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
271 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
271 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
272 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
272 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
273 | 273 | ||
274 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
274 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
275 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
275 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
276 | 276 | ||
277 | #define DP_DOWNSPREAD_CTRL 0x107 |
277 | #define DP_DOWNSPREAD_CTRL 0x107 |
278 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
278 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
279 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
279 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
280 | 280 | ||
281 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
281 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
282 | # define DP_SET_ANSI_8B10B (1 << 0) |
282 | # define DP_SET_ANSI_8B10B (1 << 0) |
283 | 283 | ||
284 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
284 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
285 | /* bitmask as for DP_I2C_SPEED_CAP */ |
285 | /* bitmask as for DP_I2C_SPEED_CAP */ |
286 | 286 | ||
287 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
287 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
288 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
288 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) |
289 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) |
289 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1) |
290 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) |
290 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) |
291 | 291 | ||
292 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ |
292 | #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ |
293 | #define DP_LINK_QUAL_LANE1_SET 0x10c |
293 | #define DP_LINK_QUAL_LANE1_SET 0x10c |
294 | #define DP_LINK_QUAL_LANE2_SET 0x10d |
294 | #define DP_LINK_QUAL_LANE2_SET 0x10d |
295 | #define DP_LINK_QUAL_LANE3_SET 0x10e |
295 | #define DP_LINK_QUAL_LANE3_SET 0x10e |
296 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 |
296 | # define DP_LINK_QUAL_PATTERN_DISABLE 0 |
297 | # define DP_LINK_QUAL_PATTERN_D10_2 1 |
297 | # define DP_LINK_QUAL_PATTERN_D10_2 1 |
298 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 |
298 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 |
299 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 |
299 | # define DP_LINK_QUAL_PATTERN_PRBS7 3 |
300 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 |
300 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 |
301 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 |
301 | # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 |
302 | # define DP_LINK_QUAL_PATTERN_MASK 7 |
302 | # define DP_LINK_QUAL_PATTERN_MASK 7 |
303 | 303 | ||
304 | #define DP_TRAINING_LANE0_1_SET2 0x10f |
304 | #define DP_TRAINING_LANE0_1_SET2 0x10f |
305 | #define DP_TRAINING_LANE2_3_SET2 0x110 |
305 | #define DP_TRAINING_LANE2_3_SET2 0x110 |
306 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) |
306 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) |
307 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) |
307 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) |
308 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) |
308 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) |
309 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) |
309 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) |
310 | 310 | ||
311 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
311 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
312 | # define DP_MST_EN (1 << 0) |
312 | # define DP_MST_EN (1 << 0) |
313 | # define DP_UP_REQ_EN (1 << 1) |
313 | # define DP_UP_REQ_EN (1 << 1) |
314 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
314 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
315 | 315 | ||
316 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
316 | #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ |
317 | #define DP_AUDIO_DELAY1 0x113 |
317 | #define DP_AUDIO_DELAY1 0x113 |
318 | #define DP_AUDIO_DELAY2 0x114 |
318 | #define DP_AUDIO_DELAY2 0x114 |
319 | 319 | ||
320 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
320 | #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ |
321 | # define DP_LINK_RATE_SET_SHIFT 0 |
321 | # define DP_LINK_RATE_SET_SHIFT 0 |
322 | # define DP_LINK_RATE_SET_MASK (7 << 0) |
322 | # define DP_LINK_RATE_SET_MASK (7 << 0) |
323 | 323 | ||
324 | #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ |
324 | #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ |
325 | # define DP_ALPM_ENABLE (1 << 0) |
325 | # define DP_ALPM_ENABLE (1 << 0) |
326 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) |
326 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) |
327 | 327 | ||
328 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ |
328 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ |
329 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) |
329 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) |
330 | # define DP_IRQ_HPD_ENABLE (1 << 1) |
330 | # define DP_IRQ_HPD_ENABLE (1 << 1) |
331 | 331 | ||
332 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
332 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ |
333 | # define DP_PWR_NOT_NEEDED (1 << 0) |
333 | # define DP_PWR_NOT_NEEDED (1 << 0) |
334 | 334 | ||
335 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ |
335 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ |
336 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0) |
336 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0) |
337 | 337 | ||
338 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
338 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
339 | # define DP_PSR_ENABLE (1 << 0) |
339 | # define DP_PSR_ENABLE (1 << 0) |
340 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
340 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
341 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
341 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
342 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
342 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
343 | # define DP_PSR_SELECTIVE_UPDATE (1 << 4) |
343 | # define DP_PSR_SELECTIVE_UPDATE (1 << 4) |
344 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) |
344 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) |
345 | 345 | ||
346 | #define DP_ADAPTER_CTRL 0x1a0 |
346 | #define DP_ADAPTER_CTRL 0x1a0 |
347 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) |
347 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) |
348 | 348 | ||
349 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 |
349 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 |
350 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) |
350 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) |
351 | 351 | ||
352 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 |
352 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 |
353 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 |
353 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 |
354 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 |
354 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 |
355 | 355 | ||
356 | #define DP_SINK_COUNT 0x200 |
356 | #define DP_SINK_COUNT 0x200 |
357 | /* prior to 1.2 bit 7 was reserved mbz */ |
357 | /* prior to 1.2 bit 7 was reserved mbz */ |
358 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
358 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
359 | # define DP_SINK_CP_READY (1 << 6) |
359 | # define DP_SINK_CP_READY (1 << 6) |
360 | 360 | ||
361 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
361 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
362 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
362 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
363 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
363 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
364 | # define DP_CP_IRQ (1 << 2) |
364 | # define DP_CP_IRQ (1 << 2) |
365 | # define DP_MCCS_IRQ (1 << 3) |
365 | # define DP_MCCS_IRQ (1 << 3) |
366 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ |
366 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ |
367 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ |
367 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ |
368 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
368 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
369 | 369 | ||
370 | #define DP_LANE0_1_STATUS 0x202 |
370 | #define DP_LANE0_1_STATUS 0x202 |
371 | #define DP_LANE2_3_STATUS 0x203 |
371 | #define DP_LANE2_3_STATUS 0x203 |
372 | # define DP_LANE_CR_DONE (1 << 0) |
372 | # define DP_LANE_CR_DONE (1 << 0) |
373 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
373 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
374 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
374 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
375 | 375 | ||
376 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
376 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
377 | DP_LANE_CHANNEL_EQ_DONE | \ |
377 | DP_LANE_CHANNEL_EQ_DONE | \ |
378 | DP_LANE_SYMBOL_LOCKED) |
378 | DP_LANE_SYMBOL_LOCKED) |
379 | 379 | ||
380 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
380 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
381 | 381 | ||
382 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
382 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
383 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
383 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
384 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
384 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
385 | 385 | ||
386 | #define DP_SINK_STATUS 0x205 |
386 | #define DP_SINK_STATUS 0x205 |
387 | 387 | ||
388 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
388 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
389 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
389 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
390 | 390 | ||
391 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
391 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
392 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
392 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
393 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
393 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
394 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
394 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
395 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
395 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
396 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
396 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
397 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
397 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
398 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
398 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
399 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
399 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
400 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
400 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
401 | 401 | ||
402 | #define DP_TEST_REQUEST 0x218 |
402 | #define DP_TEST_REQUEST 0x218 |
403 | # define DP_TEST_LINK_TRAINING (1 << 0) |
403 | # define DP_TEST_LINK_TRAINING (1 << 0) |
404 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
404 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
405 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
405 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
406 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
406 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
407 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
407 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
408 | 408 | ||
409 | #define DP_TEST_LINK_RATE 0x219 |
409 | #define DP_TEST_LINK_RATE 0x219 |
410 | # define DP_LINK_RATE_162 (0x6) |
410 | # define DP_LINK_RATE_162 (0x6) |
411 | # define DP_LINK_RATE_27 (0xa) |
411 | # define DP_LINK_RATE_27 (0xa) |
412 | 412 | ||
413 | #define DP_TEST_LANE_COUNT 0x220 |
413 | #define DP_TEST_LANE_COUNT 0x220 |
414 | 414 | ||
415 | #define DP_TEST_PATTERN 0x221 |
415 | #define DP_TEST_PATTERN 0x221 |
416 | 416 | ||
417 | #define DP_TEST_CRC_R_CR 0x240 |
417 | #define DP_TEST_CRC_R_CR 0x240 |
418 | #define DP_TEST_CRC_G_Y 0x242 |
418 | #define DP_TEST_CRC_G_Y 0x242 |
419 | #define DP_TEST_CRC_B_CB 0x244 |
419 | #define DP_TEST_CRC_B_CB 0x244 |
420 | 420 | ||
421 | #define DP_TEST_SINK_MISC 0x246 |
421 | #define DP_TEST_SINK_MISC 0x246 |
422 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
422 | # define DP_TEST_CRC_SUPPORTED (1 << 5) |
423 | # define DP_TEST_COUNT_MASK 0xf |
423 | # define DP_TEST_COUNT_MASK 0xf |
424 | 424 | ||
425 | #define DP_TEST_RESPONSE 0x260 |
425 | #define DP_TEST_RESPONSE 0x260 |
426 | # define DP_TEST_ACK (1 << 0) |
426 | # define DP_TEST_ACK (1 << 0) |
427 | # define DP_TEST_NAK (1 << 1) |
427 | # define DP_TEST_NAK (1 << 1) |
428 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
428 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
429 | 429 | ||
430 | #define DP_TEST_EDID_CHECKSUM 0x261 |
430 | #define DP_TEST_EDID_CHECKSUM 0x261 |
431 | 431 | ||
432 | #define DP_TEST_SINK 0x270 |
432 | #define DP_TEST_SINK 0x270 |
433 | # define DP_TEST_SINK_START (1 << 0) |
433 | # define DP_TEST_SINK_START (1 << 0) |
434 | 434 | ||
435 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
435 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
436 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) |
436 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) |
437 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) |
437 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) |
438 | 438 | ||
439 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ |
439 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ |
440 | /* up to ID_SLOT_63 at 0x2ff */ |
440 | /* up to ID_SLOT_63 at 0x2ff */ |
441 | 441 | ||
442 | #define DP_SOURCE_OUI 0x300 |
442 | #define DP_SOURCE_OUI 0x300 |
443 | #define DP_SINK_OUI 0x400 |
443 | #define DP_SINK_OUI 0x400 |
444 | #define DP_BRANCH_OUI 0x500 |
444 | #define DP_BRANCH_OUI 0x500 |
445 | 445 | ||
446 | #define DP_SET_POWER 0x600 |
446 | #define DP_SET_POWER 0x600 |
447 | # define DP_SET_POWER_D0 0x1 |
447 | # define DP_SET_POWER_D0 0x1 |
448 | # define DP_SET_POWER_D3 0x2 |
448 | # define DP_SET_POWER_D3 0x2 |
449 | # define DP_SET_POWER_MASK 0x3 |
449 | # define DP_SET_POWER_MASK 0x3 |
450 | 450 | ||
451 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
451 | #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ |
452 | # define DP_EDP_11 0x00 |
452 | # define DP_EDP_11 0x00 |
453 | # define DP_EDP_12 0x01 |
453 | # define DP_EDP_12 0x01 |
454 | # define DP_EDP_13 0x02 |
454 | # define DP_EDP_13 0x02 |
455 | # define DP_EDP_14 0x03 |
455 | # define DP_EDP_14 0x03 |
456 | 456 | ||
457 | #define DP_EDP_GENERAL_CAP_1 0x701 |
457 | #define DP_EDP_GENERAL_CAP_1 0x701 |
- | 458 | # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) |
|
- | 459 | # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) |
|
- | 460 | # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) |
|
- | 461 | # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) |
|
- | 462 | # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) |
|
- | 463 | # define DP_EDP_FRC_ENABLE_CAP (1 << 5) |
|
- | 464 | # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) |
|
- | 465 | # define DP_EDP_SET_POWER_CAP (1 << 7) |
|
458 | 466 | ||
- | 467 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 |
|
- | 468 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) |
|
- | 469 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) |
|
- | 470 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) |
|
- | 471 | # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) |
|
- | 472 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) |
|
- | 473 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) |
|
- | 474 | # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) |
|
459 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 |
475 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) |
- | 476 | ||
460 | 477 | #define DP_EDP_GENERAL_CAP_2 0x703 |
|
- | 478 | # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) |
|
- | 479 | ||
- | 480 | #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ |
|
- | 481 | # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) |
|
461 | #define DP_EDP_GENERAL_CAP_2 0x703 |
482 | # define DP_EDP_X_REGION_CAP_SHIFT 0 |
- | 483 | # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) |
|
- | 484 | # define DP_EDP_Y_REGION_CAP_SHIFT 4 |
|
- | 485 | ||
- | 486 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 |
|
- | 487 | # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) |
|
462 | 488 | # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) |
|
- | 489 | # define DP_EDP_FRC_ENABLE (1 << 2) |
|
- | 490 | # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) |
|
- | 491 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) |
|
- | 492 | ||
- | 493 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 |
|
- | 494 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) |
|
- | 495 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) |
|
- | 496 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) |
|
- | 497 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) |
|
- | 498 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) |
|
463 | #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ |
499 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) |
464 | 500 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) |
|
465 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 |
501 | # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) |
466 | 502 | # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) |
|
467 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 |
503 | # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ |
468 | 504 | ||
469 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 |
505 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 |
470 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 |
506 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 |
471 | 507 | ||
472 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 |
508 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724 |
473 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 |
509 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 |
474 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 |
510 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 |
475 | 511 | ||
476 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 |
512 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 |
477 | 513 | ||
478 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 |
514 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 |
479 | 515 | ||
480 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a |
516 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a |
481 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b |
517 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b |
482 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c |
518 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c |
483 | 519 | ||
484 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d |
520 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d |
485 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e |
521 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e |
486 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f |
522 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f |
487 | 523 | ||
488 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 |
524 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 |
489 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 |
525 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 |
490 | 526 | ||
491 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ |
527 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ |
492 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ |
528 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ |
493 | 529 | ||
494 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
530 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
495 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
531 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
496 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
532 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
497 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ |
533 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ |
498 | 534 | ||
499 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ |
535 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ |
500 | /* 0-5 sink count */ |
536 | /* 0-5 sink count */ |
501 | # define DP_SINK_COUNT_CP_READY (1 << 6) |
537 | # define DP_SINK_COUNT_CP_READY (1 << 6) |
502 | 538 | ||
503 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ |
539 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ |
504 | 540 | ||
505 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ |
541 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ |
506 | 542 | ||
507 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ |
543 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ |
508 | 544 | ||
509 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
545 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
510 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
546 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
511 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
547 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
512 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ |
548 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ |
513 | 549 | ||
514 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
550 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
515 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
551 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
516 | 552 | ||
517 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
553 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
518 | # define DP_PSR_SINK_INACTIVE 0 |
554 | # define DP_PSR_SINK_INACTIVE 0 |
519 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
555 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
520 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
556 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
521 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
557 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
522 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
558 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
523 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
559 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
524 | # define DP_PSR_SINK_STATE_MASK 0x07 |
560 | # define DP_PSR_SINK_STATE_MASK 0x07 |
525 | 561 | ||
526 | #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ |
562 | #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ |
527 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) |
563 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) |
528 | 564 | ||
529 | /* DP 1.2 Sideband message defines */ |
565 | /* DP 1.2 Sideband message defines */ |
530 | /* peer device type - DP 1.2a Table 2-92 */ |
566 | /* peer device type - DP 1.2a Table 2-92 */ |
531 | #define DP_PEER_DEVICE_NONE 0x0 |
567 | #define DP_PEER_DEVICE_NONE 0x0 |
532 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 |
568 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 |
533 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 |
569 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 |
534 | #define DP_PEER_DEVICE_SST_SINK 0x3 |
570 | #define DP_PEER_DEVICE_SST_SINK 0x3 |
535 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 |
571 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 |
536 | 572 | ||
537 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ |
573 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ |
538 | #define DP_LINK_ADDRESS 0x01 |
574 | #define DP_LINK_ADDRESS 0x01 |
539 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 |
575 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 |
540 | #define DP_ENUM_PATH_RESOURCES 0x10 |
576 | #define DP_ENUM_PATH_RESOURCES 0x10 |
541 | #define DP_ALLOCATE_PAYLOAD 0x11 |
577 | #define DP_ALLOCATE_PAYLOAD 0x11 |
542 | #define DP_QUERY_PAYLOAD 0x12 |
578 | #define DP_QUERY_PAYLOAD 0x12 |
543 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 |
579 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 |
544 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 |
580 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 |
545 | #define DP_REMOTE_DPCD_READ 0x20 |
581 | #define DP_REMOTE_DPCD_READ 0x20 |
546 | #define DP_REMOTE_DPCD_WRITE 0x21 |
582 | #define DP_REMOTE_DPCD_WRITE 0x21 |
547 | #define DP_REMOTE_I2C_READ 0x22 |
583 | #define DP_REMOTE_I2C_READ 0x22 |
548 | #define DP_REMOTE_I2C_WRITE 0x23 |
584 | #define DP_REMOTE_I2C_WRITE 0x23 |
549 | #define DP_POWER_UP_PHY 0x24 |
585 | #define DP_POWER_UP_PHY 0x24 |
550 | #define DP_POWER_DOWN_PHY 0x25 |
586 | #define DP_POWER_DOWN_PHY 0x25 |
551 | #define DP_SINK_EVENT_NOTIFY 0x30 |
587 | #define DP_SINK_EVENT_NOTIFY 0x30 |
552 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 |
588 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 |
553 | 589 | ||
554 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ |
590 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ |
555 | #define DP_NAK_WRITE_FAILURE 0x01 |
591 | #define DP_NAK_WRITE_FAILURE 0x01 |
556 | #define DP_NAK_INVALID_READ 0x02 |
592 | #define DP_NAK_INVALID_READ 0x02 |
557 | #define DP_NAK_CRC_FAILURE 0x03 |
593 | #define DP_NAK_CRC_FAILURE 0x03 |
558 | #define DP_NAK_BAD_PARAM 0x04 |
594 | #define DP_NAK_BAD_PARAM 0x04 |
559 | #define DP_NAK_DEFER 0x05 |
595 | #define DP_NAK_DEFER 0x05 |
560 | #define DP_NAK_LINK_FAILURE 0x06 |
596 | #define DP_NAK_LINK_FAILURE 0x06 |
561 | #define DP_NAK_NO_RESOURCES 0x07 |
597 | #define DP_NAK_NO_RESOURCES 0x07 |
562 | #define DP_NAK_DPCD_FAIL 0x08 |
598 | #define DP_NAK_DPCD_FAIL 0x08 |
563 | #define DP_NAK_I2C_NAK 0x09 |
599 | #define DP_NAK_I2C_NAK 0x09 |
564 | #define DP_NAK_ALLOCATE_FAIL 0x0a |
600 | #define DP_NAK_ALLOCATE_FAIL 0x0a |
565 | 601 | ||
566 | #define MODE_I2C_START 1 |
602 | #define MODE_I2C_START 1 |
567 | #define MODE_I2C_WRITE 2 |
603 | #define MODE_I2C_WRITE 2 |
568 | #define MODE_I2C_READ 4 |
604 | #define MODE_I2C_READ 4 |
569 | #define MODE_I2C_STOP 8 |
605 | #define MODE_I2C_STOP 8 |
570 | 606 | ||
571 | /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ |
607 | /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ |
572 | #define DP_MST_PHYSICAL_PORT_0 0 |
608 | #define DP_MST_PHYSICAL_PORT_0 0 |
573 | #define DP_MST_LOGICAL_PORT_0 8 |
609 | #define DP_MST_LOGICAL_PORT_0 8 |
574 | 610 | ||
575 | #define DP_LINK_STATUS_SIZE 6 |
611 | #define DP_LINK_STATUS_SIZE 6 |
576 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
612 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
577 | int lane_count); |
613 | int lane_count); |
578 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
614 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
579 | int lane_count); |
615 | int lane_count); |
580 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
616 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
581 | int lane); |
617 | int lane); |
582 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
618 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
583 | int lane); |
619 | int lane); |
584 | 620 | ||
585 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc |
621 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc |
586 | #define DP_RECEIVER_CAP_SIZE 0xf |
622 | #define DP_RECEIVER_CAP_SIZE 0xf |
587 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
623 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
588 | 624 | ||
589 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
625 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
590 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
626 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
591 | 627 | ||
592 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
628 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
593 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
629 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
594 | 630 | ||
595 | struct edp_sdp_header { |
631 | struct edp_sdp_header { |
596 | u8 HB0; /* Secondary Data Packet ID */ |
632 | u8 HB0; /* Secondary Data Packet ID */ |
597 | u8 HB1; /* Secondary Data Packet Type */ |
633 | u8 HB1; /* Secondary Data Packet Type */ |
598 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
634 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
599 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
635 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
600 | } __packed; |
636 | } __packed; |
601 | 637 | ||
602 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
638 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
603 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
639 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
604 | 640 | ||
605 | struct edp_vsc_psr { |
641 | struct edp_vsc_psr { |
606 | struct edp_sdp_header sdp_header; |
642 | struct edp_sdp_header sdp_header; |
607 | u8 DB0; /* Stereo Interface */ |
643 | u8 DB0; /* Stereo Interface */ |
608 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
644 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
609 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
645 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
610 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
646 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
611 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
647 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
612 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
648 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
613 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
649 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
614 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
650 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
615 | u8 DB8_31[24]; /* Reserved */ |
651 | u8 DB8_31[24]; /* Reserved */ |
616 | } __packed; |
652 | } __packed; |
617 | 653 | ||
618 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
654 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
619 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
655 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
620 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
656 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
621 | 657 | ||
622 | static inline int |
658 | static inline int |
623 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
659 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
624 | { |
660 | { |
625 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
661 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
626 | } |
662 | } |
627 | 663 | ||
628 | static inline u8 |
664 | static inline u8 |
629 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
665 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
630 | { |
666 | { |
631 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
667 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
632 | } |
668 | } |
633 | 669 | ||
634 | static inline bool |
670 | static inline bool |
635 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
671 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
636 | { |
672 | { |
637 | return dpcd[DP_DPCD_REV] >= 0x11 && |
673 | return dpcd[DP_DPCD_REV] >= 0x11 && |
638 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
674 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
639 | } |
675 | } |
640 | 676 | ||
641 | static inline bool |
677 | static inline bool |
642 | drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
678 | drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
643 | { |
679 | { |
644 | return dpcd[DP_DPCD_REV] >= 0x12 && |
680 | return dpcd[DP_DPCD_REV] >= 0x12 && |
645 | dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; |
681 | dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; |
646 | } |
682 | } |
647 | 683 | ||
648 | /* |
684 | /* |
649 | * DisplayPort AUX channel |
685 | * DisplayPort AUX channel |
650 | */ |
686 | */ |
651 | 687 | ||
652 | /** |
688 | /** |
653 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction |
689 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction |
654 | * @address: address of the (first) register to access |
690 | * @address: address of the (first) register to access |
655 | * @request: contains the type of transaction (see DP_AUX_* macros) |
691 | * @request: contains the type of transaction (see DP_AUX_* macros) |
656 | * @reply: upon completion, contains the reply type of the transaction |
692 | * @reply: upon completion, contains the reply type of the transaction |
657 | * @buffer: pointer to a transmission or reception buffer |
693 | * @buffer: pointer to a transmission or reception buffer |
658 | * @size: size of @buffer |
694 | * @size: size of @buffer |
659 | */ |
695 | */ |
660 | struct drm_dp_aux_msg { |
696 | struct drm_dp_aux_msg { |
661 | unsigned int address; |
697 | unsigned int address; |
662 | u8 request; |
698 | u8 request; |
663 | u8 reply; |
699 | u8 reply; |
664 | void *buffer; |
700 | void *buffer; |
665 | size_t size; |
701 | size_t size; |
666 | }; |
702 | }; |
667 | 703 | ||
668 | /** |
704 | /** |
669 | * struct drm_dp_aux - DisplayPort AUX channel |
705 | * struct drm_dp_aux - DisplayPort AUX channel |
670 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
706 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
671 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
707 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
672 | * @dev: pointer to struct device that is the parent for this AUX channel |
708 | * @dev: pointer to struct device that is the parent for this AUX channel |
673 | * @hw_mutex: internal mutex used for locking transfers |
709 | * @hw_mutex: internal mutex used for locking transfers |
674 | * @transfer: transfers a message representing a single AUX transaction |
710 | * @transfer: transfers a message representing a single AUX transaction |
675 | * |
711 | * |
676 | * The .dev field should be set to a pointer to the device that implements |
712 | * The .dev field should be set to a pointer to the device that implements |
677 | * the AUX channel. |
713 | * the AUX channel. |
678 | * |
714 | * |
679 | * The .name field may be used to specify the name of the I2C adapter. If set to |
715 | * The .name field may be used to specify the name of the I2C adapter. If set to |
680 | * NULL, dev_name() of .dev will be used. |
716 | * NULL, dev_name() of .dev will be used. |
681 | * |
717 | * |
682 | * Drivers provide a hardware-specific implementation of how transactions |
718 | * Drivers provide a hardware-specific implementation of how transactions |
683 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg |
719 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg |
684 | * structure describing the transaction is passed into this function. Upon |
720 | * structure describing the transaction is passed into this function. Upon |
685 | * success, the implementation should return the number of payload bytes |
721 | * success, the implementation should return the number of payload bytes |
686 | * that were transferred, or a negative error-code on failure. Helpers |
722 | * that were transferred, or a negative error-code on failure. Helpers |
687 | * propagate errors from the .transfer() function, with the exception of |
723 | * propagate errors from the .transfer() function, with the exception of |
688 | * the -EBUSY error, which causes a transaction to be retried. On a short, |
724 | * the -EBUSY error, which causes a transaction to be retried. On a short, |
689 | * helpers will return -EPROTO to make it simpler to check for failure. |
725 | * helpers will return -EPROTO to make it simpler to check for failure. |
690 | * |
726 | * |
691 | * An AUX channel can also be used to transport I2C messages to a sink. A |
727 | * An AUX channel can also be used to transport I2C messages to a sink. A |
692 | * typical application of that is to access an EDID that's present in the |
728 | * typical application of that is to access an EDID that's present in the |
693 | * sink device. The .transfer() function can also be used to execute such |
729 | * sink device. The .transfer() function can also be used to execute such |
694 | * transactions. The drm_dp_aux_register() function registers an I2C |
730 | * transactions. The drm_dp_aux_register() function registers an I2C |
695 | * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers |
731 | * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers |
696 | * should call drm_dp_aux_unregister() to remove the I2C adapter. |
732 | * should call drm_dp_aux_unregister() to remove the I2C adapter. |
697 | * The I2C adapter uses long transfers by default; if a partial response is |
733 | * The I2C adapter uses long transfers by default; if a partial response is |
698 | * received, the adapter will drop down to the size given by the partial |
734 | * received, the adapter will drop down to the size given by the partial |
699 | * response for this transaction only. |
735 | * response for this transaction only. |
700 | * |
736 | * |
701 | * Note that the aux helper code assumes that the .transfer() function |
737 | * Note that the aux helper code assumes that the .transfer() function |
702 | * only modifies the reply field of the drm_dp_aux_msg structure. The |
738 | * only modifies the reply field of the drm_dp_aux_msg structure. The |
703 | * retry logic and i2c helpers assume this is the case. |
739 | * retry logic and i2c helpers assume this is the case. |
704 | */ |
740 | */ |
705 | struct drm_dp_aux { |
741 | struct drm_dp_aux { |
706 | const char *name; |
742 | const char *name; |
707 | struct i2c_adapter ddc; |
743 | struct i2c_adapter ddc; |
708 | struct device *dev; |
744 | struct device *dev; |
709 | struct mutex hw_mutex; |
745 | struct mutex hw_mutex; |
710 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
746 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
711 | struct drm_dp_aux_msg *msg); |
747 | struct drm_dp_aux_msg *msg); |
712 | unsigned i2c_nack_count, i2c_defer_count; |
748 | unsigned i2c_nack_count, i2c_defer_count; |
713 | }; |
749 | }; |
714 | 750 | ||
715 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
751 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
716 | void *buffer, size_t size); |
752 | void *buffer, size_t size); |
717 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, |
753 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, |
718 | void *buffer, size_t size); |
754 | void *buffer, size_t size); |
719 | 755 | ||
720 | /** |
756 | /** |
721 | * drm_dp_dpcd_readb() - read a single byte from the DPCD |
757 | * drm_dp_dpcd_readb() - read a single byte from the DPCD |
722 | * @aux: DisplayPort AUX channel |
758 | * @aux: DisplayPort AUX channel |
723 | * @offset: address of the register to read |
759 | * @offset: address of the register to read |
724 | * @valuep: location where the value of the register will be stored |
760 | * @valuep: location where the value of the register will be stored |
725 | * |
761 | * |
726 | * Returns the number of bytes transferred (1) on success, or a negative |
762 | * Returns the number of bytes transferred (1) on success, or a negative |
727 | * error code on failure. |
763 | * error code on failure. |
728 | */ |
764 | */ |
729 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, |
765 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, |
730 | unsigned int offset, u8 *valuep) |
766 | unsigned int offset, u8 *valuep) |
731 | { |
767 | { |
732 | return drm_dp_dpcd_read(aux, offset, valuep, 1); |
768 | return drm_dp_dpcd_read(aux, offset, valuep, 1); |
733 | } |
769 | } |
734 | 770 | ||
735 | /** |
771 | /** |
736 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD |
772 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD |
737 | * @aux: DisplayPort AUX channel |
773 | * @aux: DisplayPort AUX channel |
738 | * @offset: address of the register to write |
774 | * @offset: address of the register to write |
739 | * @value: value to write to the register |
775 | * @value: value to write to the register |
740 | * |
776 | * |
741 | * Returns the number of bytes transferred (1) on success, or a negative |
777 | * Returns the number of bytes transferred (1) on success, or a negative |
742 | * error code on failure. |
778 | * error code on failure. |
743 | */ |
779 | */ |
744 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, |
780 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, |
745 | unsigned int offset, u8 value) |
781 | unsigned int offset, u8 value) |
746 | { |
782 | { |
747 | return drm_dp_dpcd_write(aux, offset, &value, 1); |
783 | return drm_dp_dpcd_write(aux, offset, &value, 1); |
748 | } |
784 | } |
749 | 785 | ||
750 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
786 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
751 | u8 status[DP_LINK_STATUS_SIZE]); |
787 | u8 status[DP_LINK_STATUS_SIZE]); |
752 | 788 | ||
753 | /* |
789 | /* |
754 | * DisplayPort link |
790 | * DisplayPort link |
755 | */ |
791 | */ |
756 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) |
792 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) |
757 | 793 | ||
758 | struct drm_dp_link { |
794 | struct drm_dp_link { |
759 | unsigned char revision; |
795 | unsigned char revision; |
760 | unsigned int rate; |
796 | unsigned int rate; |
761 | unsigned int num_lanes; |
797 | unsigned int num_lanes; |
762 | unsigned long capabilities; |
798 | unsigned long capabilities; |
763 | }; |
799 | }; |
764 | 800 | ||
765 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); |
801 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); |
766 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); |
802 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); |
767 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); |
803 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); |
768 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
804 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
769 | 805 | ||
770 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
806 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
771 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); |
807 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); |
772 | 808 | ||
773 | #endif /* _DRM_DP_HELPER_H_ */><>2) |
809 | #endif /* _DRM_DP_HELPER_H_ */><>2) |
774 | 810 | ||
775 | static><2) |
811 | static><2) |
776 | 812 | ||
777 | static>1) |
813 | static>1) |
778 | #define><1) |
814 | #define><1) |
779 | #define>0) |
815 | #define>0) |
780 | #define><0) |
816 | #define><0) |
781 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
817 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |