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1 | #ifndef _ASM_X86_MSR_INDEX_H |
1 | #ifndef _ASM_X86_MSR_INDEX_H |
2 | #define _ASM_X86_MSR_INDEX_H |
2 | #define _ASM_X86_MSR_INDEX_H |
3 | 3 | ||
4 | /* CPU model specific register (MSR) numbers */ |
4 | /* CPU model specific register (MSR) numbers */ |
5 | 5 | ||
6 | /* x86-64 specific MSRs */ |
6 | /* x86-64 specific MSRs */ |
7 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
7 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
8 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
8 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
9 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
9 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
10 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
10 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
11 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
11 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
12 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
12 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
13 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
13 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
14 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
14 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
15 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
15 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
16 | 16 | ||
17 | /* EFER bits: */ |
17 | /* EFER bits: */ |
18 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
18 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
19 | #define _EFER_LME 8 /* Long mode enable */ |
19 | #define _EFER_LME 8 /* Long mode enable */ |
20 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
20 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
21 | #define _EFER_NX 11 /* No execute enable */ |
21 | #define _EFER_NX 11 /* No execute enable */ |
22 | #define _EFER_SVME 12 /* Enable virtualization */ |
22 | #define _EFER_SVME 12 /* Enable virtualization */ |
23 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
23 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
24 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
24 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
25 | 25 | ||
26 | #define EFER_SCE (1<<_EFER_SCE) |
26 | #define EFER_SCE (1<<_EFER_SCE) |
27 | #define EFER_LME (1<<_EFER_LME) |
27 | #define EFER_LME (1<<_EFER_LME) |
28 | #define EFER_LMA (1<<_EFER_LMA) |
28 | #define EFER_LMA (1<<_EFER_LMA) |
29 | #define EFER_NX (1<<_EFER_NX) |
29 | #define EFER_NX (1<<_EFER_NX) |
30 | #define EFER_SVME (1<<_EFER_SVME) |
30 | #define EFER_SVME (1<<_EFER_SVME) |
31 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
31 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
32 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
32 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
33 | 33 | ||
34 | /* Intel MSRs. Some also available on other CPUs */ |
34 | /* Intel MSRs. Some also available on other CPUs */ |
35 | #define MSR_IA32_PERFCTR0 0x000000c1 |
35 | #define MSR_IA32_PERFCTR0 0x000000c1 |
36 | #define MSR_IA32_PERFCTR1 0x000000c2 |
36 | #define MSR_IA32_PERFCTR1 0x000000c2 |
37 | #define MSR_FSB_FREQ 0x000000cd |
37 | #define MSR_FSB_FREQ 0x000000cd |
38 | #define MSR_PLATFORM_INFO 0x000000ce |
38 | #define MSR_PLATFORM_INFO 0x000000ce |
39 | 39 | ||
40 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
40 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
41 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
41 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
42 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
42 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
43 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
43 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
44 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) |
44 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) |
45 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) |
45 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) |
46 | 46 | ||
47 | #define MSR_MTRRcap 0x000000fe |
47 | #define MSR_MTRRcap 0x000000fe |
48 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
48 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
49 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
49 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
50 | 50 | ||
51 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
51 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
52 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
52 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
53 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
53 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
54 | 54 | ||
55 | #define MSR_IA32_MCG_CAP 0x00000179 |
55 | #define MSR_IA32_MCG_CAP 0x00000179 |
56 | #define MSR_IA32_MCG_STATUS 0x0000017a |
56 | #define MSR_IA32_MCG_STATUS 0x0000017a |
57 | #define MSR_IA32_MCG_CTL 0x0000017b |
57 | #define MSR_IA32_MCG_CTL 0x0000017b |
58 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
58 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
59 | 59 | ||
60 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
60 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
61 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
61 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
62 | #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad |
62 | #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad |
63 | #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae |
63 | #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae |
64 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
64 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
65 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae |
65 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae |
66 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af |
66 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af |
67 | 67 | ||
68 | #define MSR_LBR_SELECT 0x000001c8 |
68 | #define MSR_LBR_SELECT 0x000001c8 |
69 | #define MSR_LBR_TOS 0x000001c9 |
69 | #define MSR_LBR_TOS 0x000001c9 |
70 | #define MSR_LBR_NHM_FROM 0x00000680 |
70 | #define MSR_LBR_NHM_FROM 0x00000680 |
71 | #define MSR_LBR_NHM_TO 0x000006c0 |
71 | #define MSR_LBR_NHM_TO 0x000006c0 |
72 | #define MSR_LBR_CORE_FROM 0x00000040 |
72 | #define MSR_LBR_CORE_FROM 0x00000040 |
73 | #define MSR_LBR_CORE_TO 0x00000060 |
73 | #define MSR_LBR_CORE_TO 0x00000060 |
74 | 74 | ||
75 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ |
75 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ |
76 | #define LBR_INFO_MISPRED BIT_ULL(63) |
76 | #define LBR_INFO_MISPRED BIT_ULL(63) |
77 | #define LBR_INFO_IN_TX BIT_ULL(62) |
77 | #define LBR_INFO_IN_TX BIT_ULL(62) |
78 | #define LBR_INFO_ABORT BIT_ULL(61) |
78 | #define LBR_INFO_ABORT BIT_ULL(61) |
79 | #define LBR_INFO_CYCLES 0xffff |
79 | #define LBR_INFO_CYCLES 0xffff |
80 | 80 | ||
81 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
81 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
82 | #define MSR_IA32_DS_AREA 0x00000600 |
82 | #define MSR_IA32_DS_AREA 0x00000600 |
83 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
83 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
84 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
84 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
85 | 85 | ||
86 | #define MSR_IA32_RTIT_CTL 0x00000570 |
86 | #define MSR_IA32_RTIT_CTL 0x00000570 |
87 | #define RTIT_CTL_TRACEEN BIT(0) |
87 | #define RTIT_CTL_TRACEEN BIT(0) |
88 | #define RTIT_CTL_CYCLEACC BIT(1) |
88 | #define RTIT_CTL_CYCLEACC BIT(1) |
89 | #define RTIT_CTL_OS BIT(2) |
89 | #define RTIT_CTL_OS BIT(2) |
90 | #define RTIT_CTL_USR BIT(3) |
90 | #define RTIT_CTL_USR BIT(3) |
91 | #define RTIT_CTL_CR3EN BIT(7) |
91 | #define RTIT_CTL_CR3EN BIT(7) |
92 | #define RTIT_CTL_TOPA BIT(8) |
92 | #define RTIT_CTL_TOPA BIT(8) |
93 | #define RTIT_CTL_MTC_EN BIT(9) |
93 | #define RTIT_CTL_MTC_EN BIT(9) |
94 | #define RTIT_CTL_TSC_EN BIT(10) |
94 | #define RTIT_CTL_TSC_EN BIT(10) |
95 | #define RTIT_CTL_DISRETC BIT(11) |
95 | #define RTIT_CTL_DISRETC BIT(11) |
96 | #define RTIT_CTL_BRANCH_EN BIT(13) |
96 | #define RTIT_CTL_BRANCH_EN BIT(13) |
97 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
97 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
98 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) |
98 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) |
99 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 |
99 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 |
100 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) |
100 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) |
101 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 |
101 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 |
102 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) |
102 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) |
103 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
103 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
104 | #define RTIT_STATUS_CONTEXTEN BIT(1) |
104 | #define RTIT_STATUS_CONTEXTEN BIT(1) |
105 | #define RTIT_STATUS_TRIGGEREN BIT(2) |
105 | #define RTIT_STATUS_TRIGGEREN BIT(2) |
106 | #define RTIT_STATUS_ERROR BIT(4) |
106 | #define RTIT_STATUS_ERROR BIT(4) |
107 | #define RTIT_STATUS_STOPPED BIT(5) |
107 | #define RTIT_STATUS_STOPPED BIT(5) |
108 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
108 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
109 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 |
109 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 |
110 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 |
110 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 |
111 | 111 | ||
112 | #define MSR_MTRRfix64K_00000 0x00000250 |
112 | #define MSR_MTRRfix64K_00000 0x00000250 |
113 | #define MSR_MTRRfix16K_80000 0x00000258 |
113 | #define MSR_MTRRfix16K_80000 0x00000258 |
114 | #define MSR_MTRRfix16K_A0000 0x00000259 |
114 | #define MSR_MTRRfix16K_A0000 0x00000259 |
115 | #define MSR_MTRRfix4K_C0000 0x00000268 |
115 | #define MSR_MTRRfix4K_C0000 0x00000268 |
116 | #define MSR_MTRRfix4K_C8000 0x00000269 |
116 | #define MSR_MTRRfix4K_C8000 0x00000269 |
117 | #define MSR_MTRRfix4K_D0000 0x0000026a |
117 | #define MSR_MTRRfix4K_D0000 0x0000026a |
118 | #define MSR_MTRRfix4K_D8000 0x0000026b |
118 | #define MSR_MTRRfix4K_D8000 0x0000026b |
119 | #define MSR_MTRRfix4K_E0000 0x0000026c |
119 | #define MSR_MTRRfix4K_E0000 0x0000026c |
120 | #define MSR_MTRRfix4K_E8000 0x0000026d |
120 | #define MSR_MTRRfix4K_E8000 0x0000026d |
121 | #define MSR_MTRRfix4K_F0000 0x0000026e |
121 | #define MSR_MTRRfix4K_F0000 0x0000026e |
122 | #define MSR_MTRRfix4K_F8000 0x0000026f |
122 | #define MSR_MTRRfix4K_F8000 0x0000026f |
123 | #define MSR_MTRRdefType 0x000002ff |
123 | #define MSR_MTRRdefType 0x000002ff |
124 | 124 | ||
125 | #define MSR_IA32_CR_PAT 0x00000277 |
125 | #define MSR_IA32_CR_PAT 0x00000277 |
126 | 126 | ||
127 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
127 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
128 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
128 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
129 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
129 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
130 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
130 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
131 | #define MSR_IA32_LASTINTTOIP 0x000001de |
131 | #define MSR_IA32_LASTINTTOIP 0x000001de |
132 | 132 | ||
133 | /* DEBUGCTLMSR bits (others vary by model): */ |
133 | /* DEBUGCTLMSR bits (others vary by model): */ |
134 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
134 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
135 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
135 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
136 | #define DEBUGCTLMSR_TR (1UL << 6) |
136 | #define DEBUGCTLMSR_TR (1UL << 6) |
137 | #define DEBUGCTLMSR_BTS (1UL << 7) |
137 | #define DEBUGCTLMSR_BTS (1UL << 7) |
138 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
138 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
139 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
139 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
140 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
140 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
141 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
141 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
142 | 142 | ||
143 | #define MSR_PEBS_FRONTEND 0x000003f7 |
143 | #define MSR_PEBS_FRONTEND 0x000003f7 |
144 | 144 | ||
145 | #define MSR_IA32_POWER_CTL 0x000001fc |
145 | #define MSR_IA32_POWER_CTL 0x000001fc |
146 | 146 | ||
147 | #define MSR_IA32_MC0_CTL 0x00000400 |
147 | #define MSR_IA32_MC0_CTL 0x00000400 |
148 | #define MSR_IA32_MC0_STATUS 0x00000401 |
148 | #define MSR_IA32_MC0_STATUS 0x00000401 |
149 | #define MSR_IA32_MC0_ADDR 0x00000402 |
149 | #define MSR_IA32_MC0_ADDR 0x00000402 |
150 | #define MSR_IA32_MC0_MISC 0x00000403 |
150 | #define MSR_IA32_MC0_MISC 0x00000403 |
151 | 151 | ||
152 | /* C-state Residency Counters */ |
152 | /* C-state Residency Counters */ |
153 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 |
153 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 |
154 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 |
154 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 |
155 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
155 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
156 | #define MSR_CORE_C3_RESIDENCY 0x000003fc |
156 | #define MSR_CORE_C3_RESIDENCY 0x000003fc |
157 | #define MSR_CORE_C6_RESIDENCY 0x000003fd |
157 | #define MSR_CORE_C6_RESIDENCY 0x000003fd |
158 | #define MSR_CORE_C7_RESIDENCY 0x000003fe |
158 | #define MSR_CORE_C7_RESIDENCY 0x000003fe |
159 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
159 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
160 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
160 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
161 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
161 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
162 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
162 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
163 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
163 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
164 | 164 | ||
165 | /* Run Time Average Power Limiting (RAPL) Interface */ |
165 | /* Run Time Average Power Limiting (RAPL) Interface */ |
166 | 166 | ||
167 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
167 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
168 | 168 | ||
169 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
169 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
170 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
170 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
171 | #define MSR_PKG_PERF_STATUS 0x00000613 |
171 | #define MSR_PKG_PERF_STATUS 0x00000613 |
172 | #define MSR_PKG_POWER_INFO 0x00000614 |
172 | #define MSR_PKG_POWER_INFO 0x00000614 |
173 | 173 | ||
174 | #define MSR_DRAM_POWER_LIMIT 0x00000618 |
174 | #define MSR_DRAM_POWER_LIMIT 0x00000618 |
175 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 |
175 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 |
176 | #define MSR_DRAM_PERF_STATUS 0x0000061b |
176 | #define MSR_DRAM_PERF_STATUS 0x0000061b |
177 | #define MSR_DRAM_POWER_INFO 0x0000061c |
177 | #define MSR_DRAM_POWER_INFO 0x0000061c |
178 | 178 | ||
179 | #define MSR_PP0_POWER_LIMIT 0x00000638 |
179 | #define MSR_PP0_POWER_LIMIT 0x00000638 |
180 | #define MSR_PP0_ENERGY_STATUS 0x00000639 |
180 | #define MSR_PP0_ENERGY_STATUS 0x00000639 |
181 | #define MSR_PP0_POLICY 0x0000063a |
181 | #define MSR_PP0_POLICY 0x0000063a |
182 | #define MSR_PP0_PERF_STATUS 0x0000063b |
182 | #define MSR_PP0_PERF_STATUS 0x0000063b |
183 | 183 | ||
184 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
184 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
185 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
185 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
186 | #define MSR_PP1_POLICY 0x00000642 |
186 | #define MSR_PP1_POLICY 0x00000642 |
187 | 187 | ||
188 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
188 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
189 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
189 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 |
190 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
190 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A |
191 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
191 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
192 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
192 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
193 | 193 | ||
194 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
194 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
195 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |
195 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |
196 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A |
196 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A |
197 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B |
197 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B |
198 | 198 | ||
199 | #define MSR_CORE_C1_RES 0x00000660 |
199 | #define MSR_CORE_C1_RES 0x00000660 |
200 | 200 | ||
201 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
201 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
202 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
202 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
203 | 203 | ||
204 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
204 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
205 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
205 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
206 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
206 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
207 | 207 | ||
208 | /* Config TDP MSRs */ |
208 | /* Config TDP MSRs */ |
209 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
209 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
210 | #define MSR_CONFIG_TDP_LEVEL1 0x00000649 |
210 | #define MSR_CONFIG_TDP_LEVEL1 0x00000649 |
211 | #define MSR_CONFIG_TDP_LEVEL2 0x0000064A |
211 | #define MSR_CONFIG_TDP_LEVEL2 0x0000064A |
212 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
212 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B |
213 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
213 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C |
214 | 214 | ||
215 | /* Hardware P state interface */ |
215 | /* Hardware P state interface */ |
216 | #define MSR_PPERF 0x0000064e |
216 | #define MSR_PPERF 0x0000064e |
217 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
217 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
218 | #define MSR_PM_ENABLE 0x00000770 |
218 | #define MSR_PM_ENABLE 0x00000770 |
219 | #define MSR_HWP_CAPABILITIES 0x00000771 |
219 | #define MSR_HWP_CAPABILITIES 0x00000771 |
220 | #define MSR_HWP_REQUEST_PKG 0x00000772 |
220 | #define MSR_HWP_REQUEST_PKG 0x00000772 |
221 | #define MSR_HWP_INTERRUPT 0x00000773 |
221 | #define MSR_HWP_INTERRUPT 0x00000773 |
222 | #define MSR_HWP_REQUEST 0x00000774 |
222 | #define MSR_HWP_REQUEST 0x00000774 |
223 | #define MSR_HWP_STATUS 0x00000777 |
223 | #define MSR_HWP_STATUS 0x00000777 |
224 | 224 | ||
225 | /* CPUID.6.EAX */ |
225 | /* CPUID.6.EAX */ |
226 | #define HWP_BASE_BIT (1<<7) |
226 | #define HWP_BASE_BIT (1<<7) |
227 | #define HWP_NOTIFICATIONS_BIT (1<<8) |
227 | #define HWP_NOTIFICATIONS_BIT (1<<8) |
228 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
228 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
229 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
229 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
230 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
230 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
231 | 231 | ||
232 | /* IA32_HWP_CAPABILITIES */ |
232 | /* IA32_HWP_CAPABILITIES */ |
233 | #define HWP_HIGHEST_PERF(x) (x & 0xff) |
233 | #define HWP_HIGHEST_PERF(x) (x & 0xff) |
234 | #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) |
234 | #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) |
235 | #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) |
235 | #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) |
236 | #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) |
236 | #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) |
237 | 237 | ||
238 | /* IA32_HWP_REQUEST */ |
238 | /* IA32_HWP_REQUEST */ |
239 | #define HWP_MIN_PERF(x) (x & 0xff) |
239 | #define HWP_MIN_PERF(x) (x & 0xff) |
240 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) |
240 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) |
241 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) |
241 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) |
242 | #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) |
242 | #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) |
243 | #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) |
243 | #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) |
244 | #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) |
244 | #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) |
245 | 245 | ||
246 | /* IA32_HWP_STATUS */ |
246 | /* IA32_HWP_STATUS */ |
247 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) |
247 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) |
248 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) |
248 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) |
249 | 249 | ||
250 | /* IA32_HWP_INTERRUPT */ |
250 | /* IA32_HWP_INTERRUPT */ |
251 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) |
251 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) |
252 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) |
252 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) |
253 | 253 | ||
254 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
254 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
255 | 255 | ||
256 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
256 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
257 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
257 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
258 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
258 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
259 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
259 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
260 | 260 | ||
261 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
261 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
262 | 262 | ||
263 | /* These are consecutive and not in the normal 4er MCE bank block */ |
263 | /* These are consecutive and not in the normal 4er MCE bank block */ |
264 | #define MSR_IA32_MC0_CTL2 0x00000280 |
264 | #define MSR_IA32_MC0_CTL2 0x00000280 |
265 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
265 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
266 | 266 | ||
267 | #define MSR_P6_PERFCTR0 0x000000c1 |
267 | #define MSR_P6_PERFCTR0 0x000000c1 |
268 | #define MSR_P6_PERFCTR1 0x000000c2 |
268 | #define MSR_P6_PERFCTR1 0x000000c2 |
269 | #define MSR_P6_EVNTSEL0 0x00000186 |
269 | #define MSR_P6_EVNTSEL0 0x00000186 |
270 | #define MSR_P6_EVNTSEL1 0x00000187 |
270 | #define MSR_P6_EVNTSEL1 0x00000187 |
271 | 271 | ||
272 | #define MSR_KNC_PERFCTR0 0x00000020 |
272 | #define MSR_KNC_PERFCTR0 0x00000020 |
273 | #define MSR_KNC_PERFCTR1 0x00000021 |
273 | #define MSR_KNC_PERFCTR1 0x00000021 |
274 | #define MSR_KNC_EVNTSEL0 0x00000028 |
274 | #define MSR_KNC_EVNTSEL0 0x00000028 |
275 | #define MSR_KNC_EVNTSEL1 0x00000029 |
275 | #define MSR_KNC_EVNTSEL1 0x00000029 |
276 | 276 | ||
277 | /* Alternative perfctr range with full access. */ |
277 | /* Alternative perfctr range with full access. */ |
278 | #define MSR_IA32_PMC0 0x000004c1 |
278 | #define MSR_IA32_PMC0 0x000004c1 |
279 | 279 | ||
280 | /* AMD64 MSRs. Not complete. See the architecture manual for a more |
280 | /* AMD64 MSRs. Not complete. See the architecture manual for a more |
281 | complete list. */ |
281 | complete list. */ |
282 | 282 | ||
283 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
283 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
284 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
284 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
285 | #define MSR_AMD64_NB_CFG 0xc001001f |
285 | #define MSR_AMD64_NB_CFG 0xc001001f |
286 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
286 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
287 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
287 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
288 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
288 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
289 | #define MSR_AMD64_LS_CFG 0xc0011020 |
289 | #define MSR_AMD64_LS_CFG 0xc0011020 |
290 | #define MSR_AMD64_DC_CFG 0xc0011022 |
290 | #define MSR_AMD64_DC_CFG 0xc0011022 |
291 | #define MSR_AMD64_BU_CFG2 0xc001102a |
291 | #define MSR_AMD64_BU_CFG2 0xc001102a |
292 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
292 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
293 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
293 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
294 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
294 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
295 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
295 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
296 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL< |
296 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL< |
297 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
297 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
298 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
298 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
299 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
299 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
300 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
300 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
301 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
301 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
302 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
302 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
303 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
303 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
304 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
304 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
305 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL< |
305 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL< |
306 | #define MSR_AMD64_IBSCTL 0xc001103a |
306 | #define MSR_AMD64_IBSCTL 0xc001103a |
307 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
307 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
308 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
308 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
309 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
309 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
310 | 310 | ||
311 | /* Fam 16h MSRs */ |
311 | /* Fam 16h MSRs */ |
312 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
312 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
313 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
313 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
314 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
314 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
315 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a |
315 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a |
316 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b |
316 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b |
317 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 |
317 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 |
318 | 318 | ||
319 | /* Fam 15h MSRs */ |
319 | /* Fam 15h MSRs */ |
320 | #define MSR_F15H_PERF_CTL 0xc0010200 |
320 | #define MSR_F15H_PERF_CTL 0xc0010200 |
321 | #define MSR_F15H_PERF_CTR 0xc0010201 |
321 | #define MSR_F15H_PERF_CTR 0xc0010201 |
322 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
322 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
323 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
323 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
- | 324 | #define MSR_F15H_IC_CFG 0xc0011021 |
|
324 | 325 | ||
325 | /* Fam 10h MSRs */ |
326 | /* Fam 10h MSRs */ |
326 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
327 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
327 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
328 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
328 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
329 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
329 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
330 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
330 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
331 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
331 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
332 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
332 | #define MSR_FAM10H_NODE_ID 0xc001100c |
333 | #define MSR_FAM10H_NODE_ID 0xc001100c |
333 | 334 | ||
334 | /* K8 MSRs */ |
335 | /* K8 MSRs */ |
335 | #define MSR_K8_TOP_MEM1 0xc001001a |
336 | #define MSR_K8_TOP_MEM1 0xc001001a |
336 | #define MSR_K8_TOP_MEM2 0xc001001d |
337 | #define MSR_K8_TOP_MEM2 0xc001001d |
337 | #define MSR_K8_SYSCFG 0xc0010010 |
338 | #define MSR_K8_SYSCFG 0xc0010010 |
338 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
339 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
339 | /* C1E active bits in int pending message */ |
340 | /* C1E active bits in int pending message */ |
340 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
341 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
341 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
342 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
342 | #define MSR_K8_TSEG_MASK 0xc0010113 |
343 | #define MSR_K8_TSEG_MASK 0xc0010113 |
343 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
344 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
344 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
345 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
345 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
346 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
346 | 347 | ||
347 | /* K7 MSRs */ |
348 | /* K7 MSRs */ |
348 | #define MSR_K7_EVNTSEL0 0xc0010000 |
349 | #define MSR_K7_EVNTSEL0 0xc0010000 |
349 | #define MSR_K7_PERFCTR0 0xc0010004 |
350 | #define MSR_K7_PERFCTR0 0xc0010004 |
350 | #define MSR_K7_EVNTSEL1 0xc0010001 |
351 | #define MSR_K7_EVNTSEL1 0xc0010001 |
351 | #define MSR_K7_PERFCTR1 0xc0010005 |
352 | #define MSR_K7_PERFCTR1 0xc0010005 |
352 | #define MSR_K7_EVNTSEL2 0xc0010002 |
353 | #define MSR_K7_EVNTSEL2 0xc0010002 |
353 | #define MSR_K7_PERFCTR2 0xc0010006 |
354 | #define MSR_K7_PERFCTR2 0xc0010006 |
354 | #define MSR_K7_EVNTSEL3 0xc0010003 |
355 | #define MSR_K7_EVNTSEL3 0xc0010003 |
355 | #define MSR_K7_PERFCTR3 0xc0010007 |
356 | #define MSR_K7_PERFCTR3 0xc0010007 |
356 | #define MSR_K7_CLK_CTL 0xc001001b |
357 | #define MSR_K7_CLK_CTL 0xc001001b |
357 | #define MSR_K7_HWCR 0xc0010015 |
358 | #define MSR_K7_HWCR 0xc0010015 |
358 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
359 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
359 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
360 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
360 | 361 | ||
361 | /* K6 MSRs */ |
362 | /* K6 MSRs */ |
362 | #define MSR_K6_WHCR 0xc0000082 |
363 | #define MSR_K6_WHCR 0xc0000082 |
363 | #define MSR_K6_UWCCR 0xc0000085 |
364 | #define MSR_K6_UWCCR 0xc0000085 |
364 | #define MSR_K6_EPMR 0xc0000086 |
365 | #define MSR_K6_EPMR 0xc0000086 |
365 | #define MSR_K6_PSOR 0xc0000087 |
366 | #define MSR_K6_PSOR 0xc0000087 |
366 | #define MSR_K6_PFIR 0xc0000088 |
367 | #define MSR_K6_PFIR 0xc0000088 |
367 | 368 | ||
368 | /* Centaur-Hauls/IDT defined MSRs. */ |
369 | /* Centaur-Hauls/IDT defined MSRs. */ |
369 | #define MSR_IDT_FCR1 0x00000107 |
370 | #define MSR_IDT_FCR1 0x00000107 |
370 | #define MSR_IDT_FCR2 0x00000108 |
371 | #define MSR_IDT_FCR2 0x00000108 |
371 | #define MSR_IDT_FCR3 0x00000109 |
372 | #define MSR_IDT_FCR3 0x00000109 |
372 | #define MSR_IDT_FCR4 0x0000010a |
373 | #define MSR_IDT_FCR4 0x0000010a |
373 | 374 | ||
374 | #define MSR_IDT_MCR0 0x00000110 |
375 | #define MSR_IDT_MCR0 0x00000110 |
375 | #define MSR_IDT_MCR1 0x00000111 |
376 | #define MSR_IDT_MCR1 0x00000111 |
376 | #define MSR_IDT_MCR2 0x00000112 |
377 | #define MSR_IDT_MCR2 0x00000112 |
377 | #define MSR_IDT_MCR3 0x00000113 |
378 | #define MSR_IDT_MCR3 0x00000113 |
378 | #define MSR_IDT_MCR4 0x00000114 |
379 | #define MSR_IDT_MCR4 0x00000114 |
379 | #define MSR_IDT_MCR5 0x00000115 |
380 | #define MSR_IDT_MCR5 0x00000115 |
380 | #define MSR_IDT_MCR6 0x00000116 |
381 | #define MSR_IDT_MCR6 0x00000116 |
381 | #define MSR_IDT_MCR7 0x00000117 |
382 | #define MSR_IDT_MCR7 0x00000117 |
382 | #define MSR_IDT_MCR_CTRL 0x00000120 |
383 | #define MSR_IDT_MCR_CTRL 0x00000120 |
383 | 384 | ||
384 | /* VIA Cyrix defined MSRs*/ |
385 | /* VIA Cyrix defined MSRs*/ |
385 | #define MSR_VIA_FCR 0x00001107 |
386 | #define MSR_VIA_FCR 0x00001107 |
386 | #define MSR_VIA_LONGHAUL 0x0000110a |
387 | #define MSR_VIA_LONGHAUL 0x0000110a |
387 | #define MSR_VIA_RNG 0x0000110b |
388 | #define MSR_VIA_RNG 0x0000110b |
388 | #define MSR_VIA_BCR2 0x00001147 |
389 | #define MSR_VIA_BCR2 0x00001147 |
389 | 390 | ||
390 | /* Transmeta defined MSRs */ |
391 | /* Transmeta defined MSRs */ |
391 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
392 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
392 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
393 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
393 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
394 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
394 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
395 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
395 | 396 | ||
396 | /* Intel defined MSRs. */ |
397 | /* Intel defined MSRs. */ |
397 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
398 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
398 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
399 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
399 | #define MSR_IA32_TSC 0x00000010 |
400 | #define MSR_IA32_TSC 0x00000010 |
400 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
401 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
401 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
402 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
402 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
403 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
403 | #define MSR_SMI_COUNT 0x00000034 |
404 | #define MSR_SMI_COUNT 0x00000034 |
404 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
405 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
405 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
406 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
406 | #define MSR_IA32_BNDCFGS 0x00000d90 |
407 | #define MSR_IA32_BNDCFGS 0x00000d90 |
407 | 408 | ||
408 | #define MSR_IA32_XSS 0x00000da0 |
409 | #define MSR_IA32_XSS 0x00000da0 |
409 | 410 | ||
410 | #define FEATURE_CONTROL_LOCKED (1<<0) |
411 | #define FEATURE_CONTROL_LOCKED (1<<0) |
411 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
412 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
412 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
413 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
413 | #define FEATURE_CONTROL_LMCE (1<<20) |
414 | #define FEATURE_CONTROL_LMCE (1<<20) |
414 | 415 | ||
415 | #define MSR_IA32_APICBASE 0x0000001b |
416 | #define MSR_IA32_APICBASE 0x0000001b |
416 | #define MSR_IA32_APICBASE_BSP (1<<8) |
417 | #define MSR_IA32_APICBASE_BSP (1<<8) |
417 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
418 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
418 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
419 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
419 | 420 | ||
420 | #define MSR_IA32_TSCDEADLINE 0x000006e0 |
421 | #define MSR_IA32_TSCDEADLINE 0x000006e0 |
421 | 422 | ||
422 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
423 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
423 | #define MSR_IA32_UCODE_REV 0x0000008b |
424 | #define MSR_IA32_UCODE_REV 0x0000008b |
424 | 425 | ||
425 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
426 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
426 | #define MSR_IA32_SMBASE 0x0000009e |
427 | #define MSR_IA32_SMBASE 0x0000009e |
427 | 428 | ||
428 | #define MSR_IA32_PERF_STATUS 0x00000198 |
429 | #define MSR_IA32_PERF_STATUS 0x00000198 |
429 | #define MSR_IA32_PERF_CTL 0x00000199 |
430 | #define MSR_IA32_PERF_CTL 0x00000199 |
430 | #define INTEL_PERF_CTL_MASK 0xffff |
431 | #define INTEL_PERF_CTL_MASK 0xffff |
431 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
432 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
432 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
433 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
433 | #define MSR_AMD_PERF_CTL 0xc0010062 |
434 | #define MSR_AMD_PERF_CTL 0xc0010062 |
434 | 435 | ||
435 | #define MSR_IA32_MPERF 0x000000e7 |
436 | #define MSR_IA32_MPERF 0x000000e7 |
436 | #define MSR_IA32_APERF 0x000000e8 |
437 | #define MSR_IA32_APERF 0x000000e8 |
437 | 438 | ||
438 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
439 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
439 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
440 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
440 | 441 | ||
441 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
442 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
442 | #define THERM_INT_LOW_ENABLE (1 << 1) |
443 | #define THERM_INT_LOW_ENABLE (1 << 1) |
443 | #define THERM_INT_PLN_ENABLE (1 << 24) |
444 | #define THERM_INT_PLN_ENABLE (1 << 24) |
444 | 445 | ||
445 | #define MSR_IA32_THERM_STATUS 0x0000019c |
446 | #define MSR_IA32_THERM_STATUS 0x0000019c |
446 | 447 | ||
447 | #define THERM_STATUS_PROCHOT (1 << 0) |
448 | #define THERM_STATUS_PROCHOT (1 << 0) |
448 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
449 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
449 | 450 | ||
450 | #define MSR_THERM2_CTL 0x0000019d |
451 | #define MSR_THERM2_CTL 0x0000019d |
451 | 452 | ||
452 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
453 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
453 | 454 | ||
454 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
455 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
455 | 456 | ||
456 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
457 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
457 | 458 | ||
458 | #define MSR_MISC_PWR_MGMT 0x000001aa |
459 | #define MSR_MISC_PWR_MGMT 0x000001aa |
459 | 460 | ||
460 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
461 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
461 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
462 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
462 | #define ENERGY_PERF_BIAS_NORMAL 6 |
463 | #define ENERGY_PERF_BIAS_NORMAL 6 |
463 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
464 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
464 | 465 | ||
465 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
466 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
466 | 467 | ||
467 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
468 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
468 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
469 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
469 | 470 | ||
470 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
471 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
471 | 472 | ||
472 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
473 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
473 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
474 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
474 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
475 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
475 | 476 | ||
476 | /* Thermal Thresholds Support */ |
477 | /* Thermal Thresholds Support */ |
477 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
478 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
478 | #define THERM_SHIFT_THRESHOLD0 8 |
479 | #define THERM_SHIFT_THRESHOLD0 8 |
479 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
480 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
480 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
481 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
481 | #define THERM_SHIFT_THRESHOLD1 16 |
482 | #define THERM_SHIFT_THRESHOLD1 16 |
482 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
483 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
483 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
484 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
484 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
485 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
485 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
486 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
486 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
487 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
487 | 488 | ||
488 | /* MISC_ENABLE bits: architectural */ |
489 | /* MISC_ENABLE bits: architectural */ |
489 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
490 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
490 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) |
491 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) |
491 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 |
492 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 |
492 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) |
493 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) |
493 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 |
494 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 |
494 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) |
495 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) |
495 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 |
496 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 |
496 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) |
497 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) |
497 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 |
498 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 |
498 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) |
499 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) |
499 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 |
500 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 |
500 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) |
501 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) |
501 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
502 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
502 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
503 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
503 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
504 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
504 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
505 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
505 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
506 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
506 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
507 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
507 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |
508 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |
508 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) |
509 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) |
509 | 510 | ||
510 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
511 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
511 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
512 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
512 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) |
513 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) |
513 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 |
514 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 |
514 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) |
515 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) |
515 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 |
516 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 |
516 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) |
517 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) |
517 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 |
518 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 |
518 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) |
519 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) |
519 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 |
520 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 |
520 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) |
521 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) |
521 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 |
522 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 |
522 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) |
523 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) |
523 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 |
524 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 |
524 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) |
525 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) |
525 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 |
526 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 |
526 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) |
527 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) |
527 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 |
528 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 |
528 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) |
529 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) |
529 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 |
530 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 |
530 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) |
531 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) |
531 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 |
532 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 |
532 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) |
533 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) |
533 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 |
534 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 |
534 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) |
535 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) |
535 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 |
536 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 |
536 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) |
537 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) |
537 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 |
538 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 |
538 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) |
539 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) |
539 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 |
540 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 |
540 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) |
541 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) |
541 | 542 | ||
542 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
543 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
543 | 544 | ||
544 | /* P4/Xeon+ specific */ |
545 | /* P4/Xeon+ specific */ |
545 | #define MSR_IA32_MCG_EAX 0x00000180 |
546 | #define MSR_IA32_MCG_EAX 0x00000180 |
546 | #define MSR_IA32_MCG_EBX 0x00000181 |
547 | #define MSR_IA32_MCG_EBX 0x00000181 |
547 | #define MSR_IA32_MCG_ECX 0x00000182 |
548 | #define MSR_IA32_MCG_ECX 0x00000182 |
548 | #define MSR_IA32_MCG_EDX 0x00000183 |
549 | #define MSR_IA32_MCG_EDX 0x00000183 |
549 | #define MSR_IA32_MCG_ESI 0x00000184 |
550 | #define MSR_IA32_MCG_ESI 0x00000184 |
550 | #define MSR_IA32_MCG_EDI 0x00000185 |
551 | #define MSR_IA32_MCG_EDI 0x00000185 |
551 | #define MSR_IA32_MCG_EBP 0x00000186 |
552 | #define MSR_IA32_MCG_EBP 0x00000186 |
552 | #define MSR_IA32_MCG_ESP 0x00000187 |
553 | #define MSR_IA32_MCG_ESP 0x00000187 |
553 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
554 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
554 | #define MSR_IA32_MCG_EIP 0x00000189 |
555 | #define MSR_IA32_MCG_EIP 0x00000189 |
555 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
556 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
556 | 557 | ||
557 | /* Pentium IV performance counter MSRs */ |
558 | /* Pentium IV performance counter MSRs */ |
558 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
559 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
559 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
560 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
560 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
561 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
561 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
562 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
562 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
563 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
563 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
564 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
564 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
565 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
565 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
566 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
566 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
567 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
567 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
568 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
568 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
569 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
569 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
570 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
570 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
571 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
571 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
572 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
572 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
573 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
573 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
574 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
574 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
575 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
575 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
576 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
576 | #define MSR_P4_BPU_CCCR0 0x00000360 |
577 | #define MSR_P4_BPU_CCCR0 0x00000360 |
577 | #define MSR_P4_BPU_CCCR1 0x00000361 |
578 | #define MSR_P4_BPU_CCCR1 0x00000361 |
578 | #define MSR_P4_BPU_CCCR2 0x00000362 |
579 | #define MSR_P4_BPU_CCCR2 0x00000362 |
579 | #define MSR_P4_BPU_CCCR3 0x00000363 |
580 | #define MSR_P4_BPU_CCCR3 0x00000363 |
580 | #define MSR_P4_MS_CCCR0 0x00000364 |
581 | #define MSR_P4_MS_CCCR0 0x00000364 |
581 | #define MSR_P4_MS_CCCR1 0x00000365 |
582 | #define MSR_P4_MS_CCCR1 0x00000365 |
582 | #define MSR_P4_MS_CCCR2 0x00000366 |
583 | #define MSR_P4_MS_CCCR2 0x00000366 |
583 | #define MSR_P4_MS_CCCR3 0x00000367 |
584 | #define MSR_P4_MS_CCCR3 0x00000367 |
584 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
585 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
585 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
586 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
586 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
587 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
587 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
588 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
588 | #define MSR_P4_IQ_CCCR0 0x0000036c |
589 | #define MSR_P4_IQ_CCCR0 0x0000036c |
589 | #define MSR_P4_IQ_CCCR1 0x0000036d |
590 | #define MSR_P4_IQ_CCCR1 0x0000036d |
590 | #define MSR_P4_IQ_CCCR2 0x0000036e |
591 | #define MSR_P4_IQ_CCCR2 0x0000036e |
591 | #define MSR_P4_IQ_CCCR3 0x0000036f |
592 | #define MSR_P4_IQ_CCCR3 0x0000036f |
592 | #define MSR_P4_IQ_CCCR4 0x00000370 |
593 | #define MSR_P4_IQ_CCCR4 0x00000370 |
593 | #define MSR_P4_IQ_CCCR5 0x00000371 |
594 | #define MSR_P4_IQ_CCCR5 0x00000371 |
594 | #define MSR_P4_ALF_ESCR0 0x000003ca |
595 | #define MSR_P4_ALF_ESCR0 0x000003ca |
595 | #define MSR_P4_ALF_ESCR1 0x000003cb |
596 | #define MSR_P4_ALF_ESCR1 0x000003cb |
596 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
597 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
597 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
598 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
598 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
599 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
599 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
600 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
600 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
601 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
601 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
602 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
602 | #define MSR_P4_CRU_ESCR2 0x000003cc |
603 | #define MSR_P4_CRU_ESCR2 0x000003cc |
603 | #define MSR_P4_CRU_ESCR3 0x000003cd |
604 | #define MSR_P4_CRU_ESCR3 0x000003cd |
604 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
605 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
605 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
606 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
606 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
607 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
607 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
608 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
608 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
609 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
609 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
610 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
610 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
611 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
611 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
612 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
612 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
613 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
613 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
614 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
614 | #define MSR_P4_IQ_ESCR0 0x000003ba |
615 | #define MSR_P4_IQ_ESCR0 0x000003ba |
615 | #define MSR_P4_IQ_ESCR1 0x000003bb |
616 | #define MSR_P4_IQ_ESCR1 0x000003bb |
616 | #define MSR_P4_IS_ESCR0 0x000003b4 |
617 | #define MSR_P4_IS_ESCR0 0x000003b4 |
617 | #define MSR_P4_IS_ESCR1 0x000003b5 |
618 | #define MSR_P4_IS_ESCR1 0x000003b5 |
618 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
619 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
619 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
620 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
620 | #define MSR_P4_IX_ESCR0 0x000003c8 |
621 | #define MSR_P4_IX_ESCR0 0x000003c8 |
621 | #define MSR_P4_IX_ESCR1 0x000003c9 |
622 | #define MSR_P4_IX_ESCR1 0x000003c9 |
622 | #define MSR_P4_MOB_ESCR0 0x000003aa |
623 | #define MSR_P4_MOB_ESCR0 0x000003aa |
623 | #define MSR_P4_MOB_ESCR1 0x000003ab |
624 | #define MSR_P4_MOB_ESCR1 0x000003ab |
624 | #define MSR_P4_MS_ESCR0 0x000003c0 |
625 | #define MSR_P4_MS_ESCR0 0x000003c0 |
625 | #define MSR_P4_MS_ESCR1 0x000003c1 |
626 | #define MSR_P4_MS_ESCR1 0x000003c1 |
626 | #define MSR_P4_PMH_ESCR0 0x000003ac |
627 | #define MSR_P4_PMH_ESCR0 0x000003ac |
627 | #define MSR_P4_PMH_ESCR1 0x000003ad |
628 | #define MSR_P4_PMH_ESCR1 0x000003ad |
628 | #define MSR_P4_RAT_ESCR0 0x000003bc |
629 | #define MSR_P4_RAT_ESCR0 0x000003bc |
629 | #define MSR_P4_RAT_ESCR1 0x000003bd |
630 | #define MSR_P4_RAT_ESCR1 0x000003bd |
630 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
631 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
631 | #define MSR_P4_SAAT_ESCR1 0x000003af |
632 | #define MSR_P4_SAAT_ESCR1 0x000003af |
632 | #define MSR_P4_SSU_ESCR0 0x000003be |
633 | #define MSR_P4_SSU_ESCR0 0x000003be |
633 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
634 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
634 | 635 | ||
635 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
636 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
636 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
637 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
637 | #define MSR_P4_TC_ESCR0 0x000003c4 |
638 | #define MSR_P4_TC_ESCR0 0x000003c4 |
638 | #define MSR_P4_TC_ESCR1 0x000003c5 |
639 | #define MSR_P4_TC_ESCR1 0x000003c5 |
639 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
640 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
640 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
641 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
641 | 642 | ||
642 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
643 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
643 | 644 | ||
644 | /* Intel Core-based CPU performance counters */ |
645 | /* Intel Core-based CPU performance counters */ |
645 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
646 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
646 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
647 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
647 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
648 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
648 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
649 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
649 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
650 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
650 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
651 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
651 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
652 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
652 | 653 | ||
653 | /* Geode defined MSRs */ |
654 | /* Geode defined MSRs */ |
654 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
655 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
655 | 656 | ||
656 | /* Intel VT MSRs */ |
657 | /* Intel VT MSRs */ |
657 | #define MSR_IA32_VMX_BASIC 0x00000480 |
658 | #define MSR_IA32_VMX_BASIC 0x00000480 |
658 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
659 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
659 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
660 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
660 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
661 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
661 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
662 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
662 | #define MSR_IA32_VMX_MISC 0x00000485 |
663 | #define MSR_IA32_VMX_MISC 0x00000485 |
663 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
664 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
664 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
665 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
665 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
666 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
666 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
667 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
667 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
668 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
668 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
669 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
669 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
670 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
670 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
671 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
671 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
672 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
672 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
673 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
673 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
674 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
674 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
675 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
675 | 676 | ||
676 | /* VMX_BASIC bits and bitmasks */ |
677 | /* VMX_BASIC bits and bitmasks */ |
677 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
678 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
678 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
679 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
679 | #define VMX_BASIC_64 0x0001000000000000LLU |
680 | #define VMX_BASIC_64 0x0001000000000000LLU |
680 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
681 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
681 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
682 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
682 | #define VMX_BASIC_MEM_TYPE_WB 6LLU |
683 | #define VMX_BASIC_MEM_TYPE_WB 6LLU |
683 | #define VMX_BASIC_INOUT 0x0040000000000000LLU |
684 | #define VMX_BASIC_INOUT 0x0040000000000000LLU |
684 | 685 | ||
685 | /* MSR_IA32_VMX_MISC bits */ |
686 | /* MSR_IA32_VMX_MISC bits */ |
686 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
687 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
687 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
688 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
688 | /* AMD-V MSRs */ |
689 | /* AMD-V MSRs */ |
689 | 690 | ||
690 | #define MSR_VM_CR 0xc0010114 |
691 | #define MSR_VM_CR 0xc0010114 |
691 | #define MSR_VM_IGNNE 0xc0010115 |
692 | #define MSR_VM_IGNNE 0xc0010115 |
692 | #define MSR_VM_HSAVE_PA 0xc0010117 |
693 | #define MSR_VM_HSAVE_PA 0xc0010117 |
693 | 694 | ||
694 | #endif /* _ASM_X86_MSR_INDEX_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>12) |
695 | #endif /* _ASM_X86_MSR_INDEX_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>12) |
695 | 696 | ||
696 | #define><12) |
697 | #define><12) |
697 | 698 | ||
698 | #define>11) |
699 | #define>11) |
699 | #define><11) |
700 | #define><11) |
700 | #define>8) |
701 | #define>8) |
701 | #define><8) |
702 | #define><8) |
702 | #define>20) |
703 | #define>20) |
703 | 704 | ||
704 | #define><20) |
705 | #define><20) |
705 | 706 | ||
706 | #define>2) |
707 | #define>2) |
707 | #define><2) |
708 | #define><2) |
708 | #define>1) |
709 | #define>1) |
709 | #define><1) |
710 | #define><1) |
710 | #define>0) |
711 | #define>0) |
711 | #define><0) |
712 | #define><0) |
712 | #define>0) |
713 | #define>0) |
713 | #define><0) |
714 | #define><0) |
714 | #define> |
715 | #define> |
715 | #define> |
716 | #define> |
716 | #define> |
717 | #define> |
717 | #define> |
718 | #define> |
718 | #define>><>><>><>><>><>><>><>><>11) |
719 | #define>><>><>><>><>><>><>><>><>11) |
719 | 720 | ||
720 | /*><11) |
721 | /*><11) |
721 | 722 | ||
722 | /*>10) |
723 | /*>10) |
723 | #define><10) |
724 | #define><10) |
724 | #define>9) |
725 | #define>9) |
725 | #define><9) |
726 | #define><9) |
726 | #define>8) |
727 | #define>8) |
727 | #define><8) |
728 | #define><8) |
728 | #define>7) |
729 | #define>7) |
729 | #define><7) |
730 | #define><7) |
730 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
731 | #define>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
731 | 732 | ||
732 | /*><_EFER_FFXSR) |
733 | /*><_EFER_FFXSR) |
733 | 734 | ||
734 | /*> |
735 | /*> |
735 | #define><_EFER_LMSLE) |
736 | #define><_EFER_LMSLE) |
736 | #define> |
737 | #define> |
737 | #define><_EFER_SVME) |
738 | #define><_EFER_SVME) |
738 | #define> |
739 | #define> |
739 | #define><_EFER_NX) |
740 | #define><_EFER_NX) |
740 | #define> |
741 | #define> |
741 | #define><_EFER_LMA) |
742 | #define><_EFER_LMA) |
742 | #define> |
743 | #define> |
743 | #define><_EFER_LME) |
744 | #define><_EFER_LME) |
744 | #define> |
745 | #define> |
745 | #define><_EFER_SCE) |
746 | #define><_EFER_SCE) |
746 | #define> |
747 | #define> |