WebSVN – Kolibri OS – Diff – /drivers/ethernet/dec21x4x.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  DEC 21x4x driver for KolibriOS                                 ;;
;;                                                                 ;;
;;  Based on dec21140.Asm from Solar OS by                         ;;
;;     Eugen Brasoveanu,                                           ;;
;;       Ontanu Bogdan Valentin                                    ;;
;;                                                                 ;;
;;  Written by hidnplayr@kolibrios.org                             ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format MS COFF
 
        API_VERSION             = 0x01000100
        DRIVER_VERSION          = 5
 
        MAX_DEVICES             = 16
 
        RX_DES_COUNT            = 4     ; no of RX descriptors, must be power of 2
        RX_BUFF_SIZE            = 2048  ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
 
        TX_DES_COUNT            = 4     ; no of TX descriptors, must be power of 2
        TX_BUFF_SIZE            = 2048  ; size of buffer for each descriptor, used for memory allocation only
 
 
        DEBUG                   = 1
        __DEBUG__               = 1
        __DEBUG_LEVEL__         = 2
 
include '../struct.inc'
include '../macros.inc'
include '../proc32.inc'
include '../imports.inc'
include '../fdo.inc'
include '../netdrv.inc'
 
public START
public service_proc
public version
 
virtual at ebx
 
        device:
 
        ETH_DEVICE
 
        .rx_p_des         dd ?  ; descriptors ring with received packets
        .tx_p_des         dd ?  ; descriptors ring with 'to transmit' packets
        .tx_free_des      dd ?  ; Tx descriptors available
        .tx_wr_des        dd ?  ; Tx current descriptor to write data to
        .tx_rd_des        dd ?  ; Tx current descriptor to read TX completion
        .rx_crt_des       dd ?  ; Rx current descriptor
 
        .io_addr          dd ?
        .pci_bus          dd ?
        .pci_dev          dd ?
        .irq_line         db ?
 
        .size = $ - device
 
end virtual
 
;-------------------------------------------
; configuration registers
;-------------------------------------------
CFCS                    = 4             ; configuration and status register
 
CSR0                    = 0x00          ; Bus mode
CSR1                    = 0x08          ; Transmit Poll Command
CSR2                    = 0x10          ; Receive Poll Command
CSR3                    = 0x18          ; Receive list base address
CSR4                    = 0x20          ; Transmit list base address
CSR5                    = 0x28          ; Status
CSR6                    = 0x30          ; Operation mode
CSR7                    = 0x38          ; Interrupt enable
CSR8                    = 0x40          ; Missed frames and overflow counter
CSR9                    = 0x48          ; Boot ROM, serial ROM, and MII management
CSR10                   = 0x50          ; Boot ROM programming address
CSR11                   = 0x58          ; General-purpose timer
CSR12                   = 0x60          ; General-purpose port
CSR13                   = 0x68
CSR14                   = 0x70
CSR15                   = 0x78          ; Watchdog timer
 
;--------bits/commands of CSR0-------------------
CSR0_RESET              = 1b
 
CSR0_WIE                = 1 shl 24      ; Write and Invalidate Enable
CSR0_RLE                = 1 shl 23      ; PCI Read Line Enable
CSR0_RML                = 1 shl 21      ; PCI Read Multiple
 
CSR0_CACHEALIGN_NONE    = 00b shl 14
CSR0_CACHEALIGN_32      = 01b shl 14
CSR0_CACHEALIGN_64      = 10b shl 14
CSR0_CACHEALIGN_128     = 11b shl 14
 
; using values from linux driver..
CSR0_DEFAULT            = CSR0_WIE + CSR0_RLE + CSR0_RML + CSR0_CACHEALIGN_NONE
 
;------- CSR5 -STATUS- bits --------------------------------
CSR5_TI                 = 1 shl 0       ; Transmit interupt - frame transmition completed
CSR5_TPS                = 1 shl 1       ; Transmit process stopped
CSR5_TU                 = 1 shl 2       ; Transmit Buffer unavailable
CSR5_TJT                = 1 shl 3       ; Transmit Jabber Timeout (transmitter had been excessively active)
CSR5_UNF                = 1 shl 5       ; Transmit underflow - FIFO underflow
CSR5_RI                 = 1 shl 6       ; Receive Interrupt
CSR5_RU                 = 1 shl 7       ; Receive Buffer unavailable
CSR5_RPS                = 1 shl 8       ; Receive Process stopped
CSR5_RWT                = 1 shl 9       ; Receive Watchdow Timeout
CSR5_ETI                = 1 shl 10      ; Early transmit Interrupt
CSR5_GTE                = 1 shl 11      ; General Purpose Timer Expired
CSR5_FBE                = 1 shl 13      ; Fatal bus error
CSR5_ERI                = 1 shl 14      ; Early receive Interrupt
CSR5_AIS                = 1 shl 15      ; Abnormal interrupt summary
CSR5_NIS                = 1 shl 16      ; normal interrupt summary
CSR5_RS_SH              = 17            ; Receive process state  -shift
CSR5_RS_MASK            = 111b          ;                        -mask
CSR5_TS_SH              = 20            ; Transmit process state -shift
CSR5_TS_MASK            = 111b          ;                        -mask
CSR5_EB_SH              = 23            ; Error bits             -shift
CSR5_EB_MASK            = 111b          ; Error bits             -mask
 
;CSR5 TS values
CSR5_TS_STOPPED                 = 000b
CSR5_TS_RUNNING_FETCHING_DESC   = 001b
CSR5_TS_RUNNING_WAITING_TX      = 010b
CSR5_TS_RUNNING_READING_BUFF    = 011b
CSR5_TS_RUNNING_SETUP_PCKT      = 101b
CSR5_TS_SUSPENDED               = 110b
CSR5_TS_RUNNING_CLOSING_DESC    = 111b
 
;------- CSR6 -OPERATION MODE- bits --------------------------------
CSR6_HP                 = 1 shl 0       ; Hash/Perfect Receive Filtering mode
CSR6_SR                 = 1 shl 1       ; Start/Stop receive
CSR6_HO                 = 1 shl 2       ; Hash only Filtering mode
CSR6_PB                 = 1 shl 3       ; Pass bad frames
CSR6_IF                 = 1 shl 4       ; Inverse filtering
CSR6_SB                 = 1 shl 5       ; Start/Stop backoff counter
CSR6_PR                 = 1 shl 6       ; Promiscuos mode -default after reset
CSR6_PM                 = 1 shl 7       ; Pass all multicast
CSR6_F                  = 1 shl 9       ; Full Duplex mode
CSR6_OM_SH              = 10            ; Operating Mode -shift
CSR6_OM_MASK            = 11b           ;                -mask
CSR6_FC                 = 1 shl 12      ; Force Collision Mode
CSR6_ST                 = 1 shl 13      ; Start/Stop Transmission Command
CSR6_TR_SH              = 14            ; Threshold Control      -shift
CSR6_TR_MASK            = 11b           ;                        -mask
CSR6_CA                 = 1 shl 17      ; Capture Effect Enable
CSR6_PS                 = 1 shl 18      ; Port select SRL / MII/SYM
CSR6_HBD                = 1 shl 19      ; Heartbeat Disable
CSR6_SF                 = 1 shl 21      ; Store and Forward -transmit full packet only
CSR6_TTM                = 1 shl 22      ; Transmit Threshold Mode -
CSR6_PCS                = 1 shl 23      ; PCS active and MII/SYM port operates in symbol mode
CSR6_SCR                = 1 shl 24      ; Scrambler Mode
CSR6_MBO                = 1 shl 25      ; Must Be One
CSR6_RA                 = 1 shl 30      ; Receive All
CSR6_SC                 = 1 shl 31      ; Special Capture Effect Enable
 
 
;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------
CSR7_TI                 = 1 shl 0       ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
CSR7_TS                 = 1 shl 1       ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
CSR7_TU                 = 1 shl 2       ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
CSR7_TJ                 = 1 shl 3       ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
CSR7_UN                 = 1 shl 5       ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
CSR7_RI                 = 1 shl 6       ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
CSR7_RU                 = 1 shl 7       ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
CSR7_RS                 = 1 shl 8       ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
CSR7_RW                 = 1 shl 9       ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
CSR7_ETE                = 1 shl 10      ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
CSR7_GPT                = 1 shl 11      ; general purpose timer enable (set with CSR7<15> & CSR5<11> )
CSR7_FBE                = 1 shl 13      ; Fatal bus error enable (set with CSR7<15> & CSR5<13> )
CSR7_ERE                = 1 shl 14      ; Early receive enable (set with CSR7<16> & CSR5<14> )
CSR7_AI                 = 1 shl 15      ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>)
CSR7_NI                 = 1 shl 16      ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>)
 
CSR7_DEFAULT            = CSR7_TI + CSR7_TS + CSR7_RI + CSR7_RS + CSR7_TU + CSR7_TJ + CSR7_UN + \
                                        CSR7_RU + CSR7_RW + CSR7_FBE + CSR7_AI + CSR7_NI
 
;----------- descriptor structure ---------------------
struc   DES {
        .status         dd ?    ; bit 31 is 'own' and rest is 'status'
        .length         dd ?    ; control bits + bytes-count buffer 1 + bytes-count buffer 2
        .buffer1        dd ?    ; pointer to buffer1
        .buffer2        dd ?    ; pointer to buffer2 or in this case to next descriptor, as we use a chained structure
        .virtaddr       dd ?
        .size = 64              ; 64, for alignment purposes
}
 
virtual at 0
        DES DES
end virtual
 
;common to Rx and Tx
DES0_OWN                = 1 shl 31              ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
 
;receive
RDES0_ZER               = 1 shl 0               ; must be 0 if legal length :D
RDES0_CE                = 1 shl 1               ; CRC error, valid only on last desc (RDES0<8>=1)
RDES0_DB                = 1 shl 2               ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
RDES0_RE                = 1 shl 3               ; Report on MII error.. i dont realy know what this means :P
RDES0_RW                = 1 shl 4               ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
RDES0_FT                = 1 shl 5               ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
RDES0_CS                = 1 shl 6               ; Collision seen, valid only on last desc (RDES0<8>=1)
RDES0_TL                = 1 shl 7               ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
RDES0_LS                = 1 shl 8               ; Last descriptor of current frame
RDES0_FS                = 1 shl 9               ; First descriptor of current frame
RDES0_MF                = 1 shl 10              ; Multicast frame, valid only on last desc (RDES0<8>=1)
RDES0_RF                = 1 shl 11              ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
RDES0_DT_SERIAL         = 00b shl 12            ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_INTERNAL       = 01b shl 12            ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_EXTERNAL       = 11b shl 12            ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DE                = 1 shl 14              ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
RDES0_ES                = 1 shl 15              ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
RDES0_FL_SH             = 16                    ; Field length shift, valid only on last desc (RDES0<8>=1)
RDES0_FL_MASK           = 11111111111111b       ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
RDES0_FF                = 1 shl 30              ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
 
RDES1_RBS1_MASK         = 11111111111b          ; first buffer size MASK
RDES1_RBS2_SH           = 11                    ; second buffer size SHIFT
RDES1_RBS2_MASK         = 11111111111b          ; second buffer size MASK
RDES1_RCH               = 1 shl 24              ; Second address chained - second address (buffer) is next desc address
RDES1_RER               = 1 shl 25              ; Receive End of Ring - final descriptor, NIC must return to first desc
 
;transmition
TDES0_DE                = 1 shl 0               ; Deffered
TDES0_UF                = 1 shl 1               ; Underflow error
TDES0_LF                = 1 shl 2               ; Link fail report (only if CSR6<23>=1)
TDES0_CC_SH             = 3                     ; Collision Count shift - no of collision before transmition
TDES0_CC_MASK           = 1111b                 ; Collision Count mask
TDES0_HF                = 1 shl 7               ; Heartbeat fail
TDES0_EC                = 1 shl 8               ; Excessive Collisions - >16 collisions
TDES0_LC                = 1 shl 9               ; Late collision
TDES0_NC                = 1 shl 10              ; No carrier
TDES0_LO                = 1 shl 11              ; Loss of carrier
TDES0_TO                = 1 shl 14              ; Transmit Jabber Timeout
TDES0_ES                = 1 shl 15              ; Error summary TDES0<1+8+9+10+11+14>=1
 
TDES1_TBS1_MASK         = 11111111111b          ; Buffer 1 size mask
TDES1_TBS2_SH           = 11                    ; Buffer 2 size shift
TDES1_TBS2_MASK         = 11111111111b          ; Buffer 2 size mask
TDES1_FT0               = 1 shl 22              ; Filtering type 0
TDES1_DPD               = 1 shl 23              ; Disabled padding for packets <64bytes, no padding
TDES1_TCH               = 1 shl 24              ; Second address chained - second buffer pointer is to next desc
TDES1_TER               = 1 shl 25              ; Transmit end of ring - final descriptor
TDES1_AC                = 1 shl 26              ; Add CRC disable -pretty obvious
TDES1_SET               = 1 shl 27              ; Setup packet
TDES1_FT1               = 1 shl 28              ; Filtering type 1
TDES1_FS                = 1 shl 29              ; First segment - buffer is first segment of frame
TDES1_LS                = 1 shl 30              ; Last segment
TDES1_IC                = 1 shl 31              ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
 
MAX_ETH_FRAME_SIZE      = 1514
 
RX_MEM_TOTAL_SIZE       = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
TX_MEM_TOTAL_SIZE       = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
 
;=============================================================================
; serial ROM operations
;=============================================================================
CSR9_SR                 = 1 shl 11        ; SROM Select
CSR9_RD                 = 1 shl 14        ; ROM Read Operation
CSR9_SROM_DO            = 1 shl 3         ; Data Out for SROM
CSR9_SROM_DI            = 1 shl 2         ; Data In to SROM
CSR9_SROM_CK            = 1 shl 1         ; clock for SROM
CSR9_SROM_CS            = 1 shl 0         ; chip select.. always needed
 
; assume dx is CSR9
macro SROM_Delay {
        push    eax
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        in      eax, dx
        pop     eax
}
 
; assume dx is CSR9
macro MDIO_Delay {
        push    eax
        in      eax, dx
        pop     eax
}
 
macro Bit_Set a_bit {
        in      eax, dx
        or      eax, a_bit
        out     dx , eax
}
 
macro Bit_Clear a_bit {
        in      eax, dx
        and     eax, not (a_bit)
        out     dx, eax
}
 
 
section '.flat' code readable align 16
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc START stdcall, state:dword
 
        cmp [state], 1
        jne .exit
 
  .entry:
 
        DEBUGF  2,"Loading %s driver\n", my_service
        stdcall RegService, my_service, service_proc
        ret
 
  .fail:
  .exit:
        xor eax, eax
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc service_proc stdcall, ioctl:dword
 
        mov     edx, [ioctl]
        mov     eax, [edx + IOCTL.io_code]
 
;------------------------------------------------------
 
        cmp     eax, 0 ;SRV_GETVERSION
        jne     @F
 
        cmp     [edx + IOCTL.out_size], 4
        jb      .fail
        mov     eax, [edx + IOCTL.output]
        mov     [eax], dword API_VERSION
 
        xor     eax, eax
        ret
 
;------------------------------------------------------
  @@:
        cmp     eax, 1 ;SRV_HOOK
        jne     .fail
 
        cmp     [edx + IOCTL.inp_size], 3                     ; Data input must be at least 3 bytes
        jb      .fail
 
        mov     eax, [edx + IOCTL.input]
        cmp     byte [eax], 1                           ; 1 means device number and bus number (pci) are given
        jne     .fail                                   ; other types arent supported for this card yet
 
; check if the device is already listed
 
        mov     esi, device_list
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .firstdevice
 
;        mov     eax, [edx + IOCTL.input]                ; get the pci bus and device numbers
        mov     ax, [eax+1]                             ;
  .nextdevice:
        mov     ebx, [esi]
        cmp     al, byte[device.pci_bus]
        jne     @f
        cmp     ah, byte[device.pci_dev]
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
       @@:
        add     esi, 4
        loop    .nextdevice
 
 
; This device doesnt have its own eth_device structure yet, lets create one
  .firstdevice:
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
        jae     .fail
 
        push    edx
        stdcall KernelAlloc, dword device.size          ; Allocate the buffer for eth_device structure
        pop     edx
        test    eax, eax
        jz      .fail
        mov     ebx, eax                                ; ebx is always used as a pointer to the structure (in driver, but also in kernel code)
 
; Fill in the direct call addresses into the struct
 
        mov     [device.reset], reset
        mov     [device.transmit], transmit
        mov     [device.unload], unload
        mov     [device.name], my_service
 
; save the pci bus and device numbers
 
        mov     eax, [edx + IOCTL.input]
        movzx   ecx, byte[eax+1]
        mov     [device.pci_bus], ecx
        movzx   ecx, byte[eax+2]
        mov     [device.pci_dev], ecx
 
; Now, it's time to find the base io addres of the PCI device
 
        PCI_find_io
 
; We've found the io address, find IRQ now
 
        PCI_find_irq
 
        DEBUGF  2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
        [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
 
        allocate_and_clear [device.rx_p_des], RX_DES_COUNT*(DES.size+RX_BUFF_SIZE), .err
        allocate_and_clear [device.tx_p_des], TX_DES_COUNT*(DES.size+TX_BUFF_SIZE), .err
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
        mov     eax, [devices]                                          ; Add the device structure to our device list
        mov     [device_list+4*eax], ebx                                ; (IRQ handler uses this list to find device)
        inc     [devices]                                               ;
 
        call    probe                                                   ; this function will output in eax
        test    eax, eax
        jnz     .err2                                                   ; If an error occured, exit
 
 
        mov     [device.type], NET_TYPE_ETH
        call    NetRegDev
 
        cmp     eax, -1
        je      .destroy
 
        ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
        DEBUGF  2,"Trying to find device number of already registered device\n"
        call    NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
                                                                        ; into a device number in edi
        mov     eax, edi                                                ; Application wants it in eax instead
        DEBUGF  2,"Kernel says: %u\n", eax
        ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
        ; todo: reset device into virgin state
 
  .err2:
        dec     [devices]
  .err:
        DEBUGF  2,"removing device structure\n"
        stdcall KernelFree, [device.rx_p_des]
        stdcall KernelFree, [device.tx_p_des]
        stdcall KernelFree, ebx
 
 
  .fail:
        or      eax, -1
        ret
 
;------------------------------------------------------
endp
 
 
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
;;                                                                        ;;
;;        Actual Hardware dependent code starts here                      ;;
;;                                                                        ;;
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
 
 
 
align 4
unload:
        ; TODO: (in this particular order)
        ;
        ; - Stop the device
        ; - Detach int handler
        ; - Remove device from local list (RTL8139_LIST)
        ; - call unregister function in kernel
        ; - Remove all allocated structures and buffers the card used
 
        or      eax,-1
 
ret
 
 
macro status {
        set_io  CSR5
        in      eax, dx
        DEBUGF  1,"CSR5: %x\n", eax
}
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Probe                                   ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
probe:
 
        DEBUGF  2,"Probing dec21x4x device: "
 
        PCI_make_bus_master
 
        stdcall PciRead32, [device.pci_bus], [device.pci_dev], 0                                ; get device/vendor id
        DEBUGF  1,"Vendor id: 0x%x\n", ax
 
        cmp     ax, 0x1011
        je      .dec
        cmp     ax, 0x1317
        je      .admtek
        jmp     .notfound
 
  .dec:
        shr     eax, 16
        DEBUGF  1,"Vendor ok!, device id: 0x%x\n", ax                 ; TODO: use another method to detect chip!
 
        cmp     ax, 0x0009
        je      .supported_device
 
        cmp     ax, 0x0019
        je      .supported_device2
 
  .admtek:
        shr     eax, 16
        DEBUGF  1,"Vendor ok!, device id: 0x%x\n", ax
 
        cmp     ax, 0x0985
        je      .supported_device
 
  .notfound:
        DEBUGF  1,"Device not supported!\n"
        or      eax, -1
        ret
 
  .supported_device2:
 
        ; wake up the 21143
 
        xor     eax, eax
        stdcall PciWrite32, [device.pci_bus], [device.pci_dev], 0x40, eax
 
 
  .supported_device:
        call    SROM_GetWidth           ; TODO: use this value returned in ecx
                                        ; in the read_word routine!
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Reset                                   ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
reset:
 
        DEBUGF  2,"Resetting dec21x4x\n"
 
;-----------------------------------------------------------
; board software reset - if fails, dont do nothing else
 
        set_io  0
        status
        set_io  CSR0
        mov     eax, CSR0_RESET
        out     dx, eax
 
; wait at least 50 PCI cycles
        mov     esi, 1000
        call    Sleep
 
;-----------
; setup CSR0
 
        set_io  0
        status
        set_io  CSR0
        mov     eax, CSR0_DEFAULT
        out     dx, eax
 
 
; wait at least 50 PCI cycles
        mov     esi, 1000
        call    Sleep
 
;-----------------------------------
; Read mac from eeprom to driver ram
 
        call    read_mac_eeprom
 
;--------------------------------
; insert irq handler on given irq
 
        movzx   eax, [device.irq_line]
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
        stdcall AttachIntHandler, eax, int_handler, dword 0
        test    eax, eax
        jnz     @f
        DEBUGF  2,"Could not attach int handler!\n"
;        or      eax, -1
;        ret
  @@:
 
        set_io  0
        status
 
        call    init_ring
 
;--------------------------------------------
; setup CSR3 & CSR4 (pointers to descriptors)
 
        set_io  0
        status
        set_io  CSR3
        mov     eax, [device.rx_p_des]
        GetRealAddr
        DEBUGF  1,"RX descriptor base address: %x\n", eax
        out     dx, eax
 
        set_io  CSR4
        mov     eax, [device.tx_p_des]
        GetRealAddr
        DEBUGF  1,"TX descriptor base address: %x\n", eax
        out     dx, eax
 
;-------------------------------------------------------
; setup interrupt mask register -expect IRQs from now on
 
        status
        DEBUGF  1,"Enabling interrupts\n"
        set_io  CSR7
        mov     eax, CSR7_DEFAULT
        out     dx, eax
        status
 
;----------
; enable RX
 
        set_io  0
        status
        DEBUGF  1,"Enable RX\n"
 
        set_io  CSR6
        Bit_Set CSR6_SR; or CSR6_PR or CSR6_ST
        DEBUGF  1,"CSR6: %x\n", eax
 
        status
 
        call    start_link
 
; wait a bit
        mov     esi, 500
        call    Sleep
 
;----------------------------------------------------
; send setup packet to notify the board about the MAC
 
        call    Send_Setup_Packet
 
        xor     eax, eax
; clear packet/byte counters
 
        lea     edi, [device.bytes_tx]
        mov     ecx, 6
        rep     stosd
 
; Set the mtu, kernel will be able to send now
        mov     [device.mtu], 1514
 
; Set link state to unknown
        mov     [device.state], ETH_LINK_UNKOWN
 
        DEBUGF  1,"Reset done\n"
 
        ret
 
 
 
align 4
init_ring:
 
;------------------------------------------
; Setup RX descriptors (use chained method)
 
        mov     eax, [device.rx_p_des]
        GetRealAddr
        mov     edx, eax
        push    eax
        lea     esi, [eax + RX_DES_COUNT*(DES.size)]    ; jump over RX descriptors
        mov     eax, [device.rx_p_des]
        add     eax, RX_DES_COUNT*(DES.size)            ; jump over RX descriptors
        mov     edi, [device.rx_p_des]
        mov     ecx, RX_DES_COUNT
  .loop_rx_des:
        add     edx, DES.size
        mov     [edi + DES.status], DES0_OWN            ; hardware owns buffer
        mov     [edi + DES.length], 1984 + RDES1_RCH    ; only size of first buffer, chained buffers
        mov     [edi + DES.buffer1], esi                ; hw buffer address
        mov     [edi + DES.buffer2], edx                ; pointer to next descriptor
        mov     [edi + DES.virtaddr], eax               ; virtual buffer address
        DEBUGF  1,"RX desc: buff addr: %x, next desc: %x, real buff addr: %x, real descr addr: %x \n", esi, edx, eax, edi
 
        add     esi, RX_BUFF_SIZE
        add     eax, RX_BUFF_SIZE
        add     edi, DES.size
        dec     ecx
        jnz     .loop_rx_des
 
; set last descriptor as LAST
        sub     edi, DES.size
        or      [edi + DES.length], RDES1_RER           ; EndOfRing
        pop     [edi + DES.buffer2]                     ; point it to the first descriptor
 
;---------------------
; Setup TX descriptors
 
        mov     eax, [device.tx_p_des]
        GetRealAddr
        mov     edx, eax
        push    eax
        lea     esi, [eax + TX_DES_COUNT*(DES.size)]    ; jump over TX descriptors
        mov     eax, [device.tx_p_des]
        add     eax, TX_DES_COUNT*(DES.size)            ; jump over TX descriptors
        mov     edi, [device.tx_p_des]
        mov     ecx, TX_DES_COUNT
  .loop_tx_des:
        add     edx, DES.size
        mov     [edi + DES.status], 0                   ; owned by driver
        mov     [edi + DES.length], TDES1_TCH           ; chained method
        mov     [edi + DES.buffer1], esi                ; pointer to buffer
        mov     [edi + DES.buffer2], edx                ; pointer to next descr
        mov     [edi + DES.virtaddr], eax
        DEBUGF  1,"TX desc: buff addr: %x, next desc: %x, virt buff addr: %x, virt descr addr: %x \n", esi, edx, eax, edi
 
        add     esi, TX_BUFF_SIZE
        add     eax, TX_BUFF_SIZE
        add     edi, DES.size
        dec     ecx
        jnz     .loop_tx_des
        
; set last descriptor as LAST
        sub     edi, DES.size
        or      [edi + DES.length], TDES1_TER           ; EndOfRing
        pop     [edi + DES.buffer2]                     ; point it to the first descriptor
 
;------------------
; Reset descriptors
 
        mov     [device.tx_wr_des], 0
        mov     [device.tx_rd_des], 0
        mov     [device.rx_crt_des], 0
        mov     [device.tx_free_des], TX_DES_COUNT
 
        ret
 
 
align 4
start_link:
 
        DEBUGF  1,"Starting link\n"
 
        ; TODO: write working code here
 
        ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Send setup packet                       ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
Send_Setup_Packet:
 
        DEBUGF  1,"Sending setup packet\n"
 
; if no descriptors available, out
        mov     ecx, 1000
@@loop_wait_desc:
        cmp     [device.tx_free_des], 0
        jne     @f
 
        dec     ecx
        jnz     @@loop_wait_desc
 
        mov     eax, -1
        ret
      @@:
 
; go to current send descriptor
        mov     edi, [device.tx_p_des]
        mov     eax, [device.tx_wr_des]
        DEBUGF  1,"Got free descriptor: %u (%x)", eax, edi
        mov     edx, DES.size
        mul     edx
        add     edi, eax
        DEBUGF  1,"=>%x\n",  edi
 
; if NOT sending FIRST setup packet, must set current descriptor to 0 size for both buffers,
;  and go to next descriptor for real setup packet...            ;; TODO: check if 2 descriptors are available
 
;       cmp     [device.tx_packets], 0
;       je      .first
;               
;       and     [edi+DES.des1], 0
;       mov     [edi+DES.des0], DES0_OWN
;               
; go to next descriptor
;        inc     [device.tx_wr_des]
;        and     [device.tx_wr_des], TX_DES_COUNT-1
;
; dec free descriptors count
;        cmp     [device.tx_free_des], 0
;        jz      @f
;        dec     [device.tx_free_des]
;       @@:
;
;       ; recompute pointer to current descriptor
;       mov     edi, [device.tx_p_des]
;       mov     eax, [device.tx_wr_des]
;       mov     edx, DES.size
;       mul     edx
;       add     edi, eax
 
  .first:
 
        push    edi
; copy setup packet to current descriptor
        mov     edi, [edi + DES.virtaddr]
; copy the address once
        lea     esi, [device.mac]
        DEBUGF  1,"copying packet to %x from %x\n", edi, esi
        mov     ecx, 3  ; mac is 6 bytes thus 3 words
  .loop:
        DEBUGF  1,"%x ", [esi]:4
        movsw
        inc     edi
        inc     edi
        dec     ecx
        jnz     .loop
 
        DEBUGF  1,"\n"
 
; copy 15 times the broadcast address
        mov     ecx, 3*15
        mov     eax, 0xffffffff
        rep     stosd
 
        pop     edi
 
; setup descriptor
        DEBUGF  1,"setting up descriptor\n"
        mov     [edi + DES.length], TDES1_IC + TDES1_SET + TDES1_TCH + 192        ; size must be EXACTLY 192 bytes
        mov     [edi + DES.status], DES0_OWN
 
        DEBUGF  1,"status: %x\n", [edi + DES.status]:8
        DEBUGF  1,"length: %x\n", [edi + DES.length]:8
        DEBUGF  1,"buffer1: %x\n", [edi + DES.buffer1]:8
        DEBUGF  1,"buffer2: %x\n", [edi + DES.buffer2]:8
 
; go to next descriptor
        inc     [device.tx_wr_des]
        and     [device.tx_wr_des], TX_DES_COUNT-1
 
; dec free descriptors count
        cmp     [device.tx_free_des], 0
        jz      @f
        dec     [device.tx_free_des]
       @@:
 
; start tx
        set_io  0
        status
        set_io  CSR6
        in      eax, dx
        test    eax, CSR6_ST            ; if NOT started, start now
        jnz     .already_started
        or      eax, CSR6_ST
        DEBUGF  1,"Starting TX\n"
        jmp     .do_it
  .already_started:
                                        ; if already started, issue a Transmit Poll command
        set_io  CSR1
        xor     eax, eax
        DEBUGF  1,"Issuing transmit poll command\n"
  .do_it:
        out     dx, eax
        status
 
        DEBUGF  1,"Sending setup packet, completed!\n"
 
        ret
 
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Transmit                                ;;
;;                                         ;;
;; In: buffer pointer in [esp+4]           ;;
;;     size of buffer in [esp+8]           ;;
;;     pointer to device structure in ebx  ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
transmit:
 
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n",[esp+4],[esp+8]
        mov     eax, [esp+4]
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
        [eax+13]:2,[eax+12]:2
 
        cmp     dword [esp+8], MAX_ETH_FRAME_SIZE
        ja      .fail
 
        cmp     [device.tx_free_des], 0
        je      .fail
 
;--------------------------
; copy packet to crt buffer
        
        mov     eax, [device.tx_wr_des]
        mov     edx, DES.size
        mul     edx
        add     eax, [device.tx_p_des]
        mov     edi, [eax + DES.virtaddr]                 ; pointer to buffer
        mov     esi, [esp+4]
        mov     ecx, [esp+8]
        DEBUGF  1,"copying %u bytes from %x to %x\n", ecx, esi, edi
        rep     movsb
 
; set packet size
        mov     ecx, [eax+DES.length]
        and     ecx, TDES1_TER                          ; preserve 'End of Ring' bit
        or      ecx, [esp+8]                            ; set size
        or      ecx, TDES1_FS or TDES1_LS or TDES1_IC or TDES1_TCH    ; first descr, last descr, interrupt on complete, chained modus
        mov     [eax+DES.length], ecx
 
; set descriptor info
        mov     [eax+DES.status], DES0_OWN                ; say it is now owned by the 21x4x
 
; start tx
        set_io  0
        status
        set_io  CSR6
        in      eax, dx
        test    eax, CSR6_ST            ; if NOT started, start now
        jnz     .already_started
        or      eax, CSR6_ST
        DEBUGF  1,"Starting TX\n"
        jmp     .do_it
  .already_started:
                                        ; if already started, issues a Transmit Poll command
        set_io  CSR1
        mov     eax, -1
  .do_it:
        out     dx , eax
 
; Update stats
 
        inc     [device.packets_tx]
        mov     eax, [esp+8]
        add     dword [device.bytes_tx], eax
        adc     dword [device.bytes_tx + 4], 0
 
; go to next descriptor
        inc     [device.tx_wr_des]
        and     [device.tx_wr_des], TX_DES_COUNT-1
 
; dec free descriptors count
        test    [device.tx_free_des], -1
        jz      .end
        dec     [device.tx_free_des]
  .end:
        status
 
        DEBUGF  1,"transmit ok\n"
        xor     eax, eax
        stdcall KernelFree, [esp+4]
        ret     8
 
  .fail:
        DEBUGF  1,"transmit failed\n"
        stdcall KernelFree, [esp+4]
        or      eax, -1
        ret     8
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
        push    ebx esi edi
 
        DEBUGF  1,"\n%s int\n", my_service
 
; find pointer of device wich made IRQ occur
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .nothing
        mov     esi, device_list
  .nextdevice:
        mov     ebx, [esi]
 
        set_io  0
        set_io  CSR5
        in      ax, dx
        test    ax, ax
        out     dx, ax                                  ; send it back to ACK
        jnz     .got_it
  .continue:
        add     esi, 4
        dec     ecx
        jnz     .nextdevice
  .nothing:
        pop     edi esi ebx
        xor     eax, eax
 
        ret                                             ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
 
  .got_it:
 
        DEBUGF  1,"Device: %x CSR5: %x ", ebx, ax
 
;----------------------------------
; TX ok?
 
        test    ax, CSR5_TI
        jz      .not_tx
        push    ax esi ecx
 
        DEBUGF 1,"TX ok!\n"
                
        ; go to current descriptor
        mov     edi, [device.tx_p_des]
 
        mov     eax, [device.tx_rd_des]
        mov     edx, DES.size
        mul     edx
        add     edi, eax
                
      .loop_tx:
                
        ; done if all desc are free
        cmp     [device.tx_free_des], TX_DES_COUNT
        jz      .end_tx
 
        mov     eax, [edi+DES.status]
 
        ; we stop at first desc that is owned be NIC
        test    eax, DES0_OWN
        jnz     .end_tx
 
        ; detect is setup packet
        cmp     eax, (0ffffffffh - DES0_OWN)            ; all other bits are 1
        jne     .not_setup_packet
        DEBUGF  1,"Setup Packet detected\n"
      .not_setup_packet:
 
        DEBUGF  1,"packet status: %x\n", eax
 
        ; next descriptor
        add     edi, DES.size
        inc     [device.tx_rd_des]
        and     [device.tx_rd_des], TX_DES_COUNT-1
 
        ; inc free desc
        inc     [device.tx_free_des]
        cmp     [device.tx_free_des], TX_DES_COUNT
        jbe     @f
        mov     [device.tx_free_des], TX_DES_COUNT
       @@:
 
        jmp     .loop_tx
      .end_tx:
                
        ;------------------------------------------------------
        ; here must be called standard Ethernet Tx Irq Handler
        ;------------------------------------------------------
 
        pop     ecx esi ax
 
;----------------------------------
; RX irq
  .not_tx:
        test    ax, CSR5_RI
        jz      .not_rx
        push    ax esi ecx
 
        DEBUGF 1,"RX ok!\n"
 
        push    ebx
  .rx_loop:
        pop     ebx
 
        ; get current descriptor
        mov     edi, [device.rx_p_des]
        mov     eax, [device.rx_crt_des]
        mov     edx, DES.size
        mul     edx
        add     edi, eax
 
        ; now check status
        mov     eax, [edi + DES.status]
 
        test    eax, DES0_OWN
        jnz     .end_rx                                 ; current desc is busy, nothing to do
 
        test    eax, RDES0_FS
        jz      .end_rx                                 ; current desc is NOT first packet, ERROR!
 
        test    eax, RDES0_LS                           ; if not last desc of packet, error for now
        jz      .end_rx
 
        test    eax, RDES0_ES
        jnz     .end_rx
 
        mov     esi, [edi + DES.virtaddr]
        mov     ecx, [edi + DES.status]
        shr     ecx, RDES0_FL_SH
        and     ecx, RDES0_FL_MASK
        sub     ecx, 4                                  ; crc, we dont need it
 
        DEBUGF  1,"Received packet!, size=%u, addr:%x\n", ecx, esi
 
        push    esi edi ecx
        stdcall KernelAlloc, ecx                        ; Allocate a buffer to put packet into
        pop     ecx edi esi
        test    eax, eax
        jz      .fail
 
        push    ebx
        push    dword .rx_loop
        push    ecx eax
        mov     edi, eax
 
; update statistics
        inc     [device.packets_rx]
        add     dword [device.bytes_rx], ecx
        adc     dword [device.bytes_rx + 4], 0
 
; copy packet data
        shr     cx , 1
        jnc     .nb
        movsb
  .nb:
        shr     cx , 1
        jnc     .nw
        movsw
  .nw:
        rep     movsd
 
        mov     [edi + DES.status], DES0_OWN            ; free descriptor
                
        inc     [device.rx_crt_des]                     ; next descriptor
        and     [device.rx_crt_des], RX_DES_COUNT-1
 
        jmp     Eth_input
 
  .end_rx:
  .fail:
        pop     ecx esi ax
  .not_rx:
 
        pop     edi esi ebx
        ret
 
 
 
align 4
write_mac:      ; in: mac pushed onto stack (as 3 words)
 
        DEBUGF  2,"Writing MAC: "
 
; write data into driver cache
        mov     esi, esp
        lea     edi, [device.mac]
        movsd
        movsw
        add     esp, 6
        
; send setup packet (only if driver is started)
        call    Send_Setup_Packet
 
align 4
read_mac:
 
        DEBUGF 1,"Read_mac\n"
 
        ret
 
 
 
align 4
read_mac_eeprom:
 
        DEBUGF 1,"Read_mac_eeprom\n"
 
        lea     edi, [device.mac]
        mov     esi, 20/2               ; read words, start address is 20
     .loop:
        push    esi edi
        call    SROM_Read_Word
        pop     edi esi
        stosw
        inc     esi
        cmp     esi, 26/2
        jb      .loop
 
        DEBUGF  2,"%x-%x-%x-%x-%x-%x\n",[edi-6]:2,[edi-5]:2,[edi-4]:2,[edi-3]:2,[edi-2]:2,[edi-1]:2
 
        ret
 
align 4
write_mac_eeprom:
 
        DEBUGF 1,"Write_mac_eeprom\n"
 
        ret
 
 
align 4
SROM_GetWidth:  ; should be 6 or 8 according to some manuals (returns in ecx)
 
        DEBUGF 1,"SROM_GetWidth\n"
 
        call    SROM_Idle
        call    SROM_EnterAccessMode
 
;        set_io  0
;        set_io  CSR9
 
        ; send 110b
 
        in      eax, dx
        or      eax, CSR9_SROM_DI
        call    SROM_out
 
        in      eax, dx
        or      eax, CSR9_SROM_DI
        call    SROM_out
 
        in      eax, dx
        and     eax, not (CSR9_SROM_DI)
        call    SROM_out
        
        mov     ecx,1
  .loop2:
        Bit_Set CSR9_SROM_CK
        SROM_Delay
        
        in      eax, dx
        and     eax, CSR9_SROM_DO
        jnz     .not_zero
 
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
        jmp     .end_loop2
  .not_zero:
        
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
        
        inc     ecx
        cmp     ecx, 12
        jbe     .loop2
  .end_loop2:
        
        DEBUGF 1,"Srom width=%u\n", ecx
        
        call    SROM_Idle
        call    SROM_EnterAccessMode
        call    SROM_Idle
        
        ret
 
 
align 4
SROM_out:
 
        out     dx, eax
        SROM_Delay
        Bit_Set CSR9_SROM_CK
        SROM_Delay
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
 
        ret
 
 
 
align 4
SROM_EnterAccessMode:
 
        DEBUGF 1,"SROM_EnterAccessMode\n"
 
        set_io  0
        set_io  CSR9
        mov     eax, CSR9_SR
        out     dx, eax
        SROM_Delay
 
        Bit_Set CSR9_RD
        SROM_Delay
 
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
 
        Bit_Set CSR9_SROM_CS
        SROM_Delay
        
        ret
 
 
 
align 4
SROM_Idle:
 
        DEBUGF 1,"SROM_Idle\n"
 
        call    SROM_EnterAccessMode
        
;        set_io  0
;        set_io  CSR9
        
        mov     ecx, 25
     .loop_clk:
 
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
        Bit_Set CSR9_SROM_CK
        SROM_Delay
        
        dec     ecx
        jnz     .loop_clk
 
        
        Bit_Clear CSR9_SROM_CK
        SROM_Delay
        Bit_Clear CSR9_SROM_CS
        SROM_Delay
        
        xor     eax, eax
        out     dx, eax
        
        ret
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                      ;;
;; Read serial EEprom word                                              ;;
;;                                                                      ;;
;; In: esi = read address                                               ;;
;; OUT: ax = data word                                                  ;;
;;                                                                      ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align 4
SROM_Read_Word:
 
        DEBUGF 1,"SROM_Read_word at: %x result: ", esi
 
        set_io  0
        set_io  CSR9
 
; enter access mode
        mov     eax, CSR9_SR + CSR9_RD
        out     dx , eax
        or      eax, CSR9_SROM_CS
        out     dx , eax
 
        ; TODO: change this hard-coded 6-bit stuff to use value from srom_getwidth
        
; send read command "110b" + address to read from
        and     esi, 111111b
        or      esi, 110b shl 6
        
        mov     ecx, 1 shl 9
  .loop_cmd:
        mov     eax, CSR9_SR + CSR9_RD + CSR9_SROM_CS
        test    esi, ecx
        jz      @f
        or      eax, CSR9_SROM_DI
       @@:
        out     dx , eax
        SROM_Delay
        or      eax, CSR9_SROM_CK
        out     dx , eax
        SROM_Delay
        
        shr     ecx, 1
        jnz     .loop_cmd
 
; read data from SROM
 
        xor     esi, esi
        mov     ecx, 17 ;;; TODO: figure out why 17, not 16
  .loop_read:
        
        mov     eax, CSR9_SR + CSR9_RD + CSR9_SROM_CS + CSR9_SROM_CK
        out     dx , eax
        SROM_Delay
        
        in      eax, dx
        and     eax, CSR9_SROM_DO
        shr     eax, 3
        shl     esi, 1
        or      esi, eax
        
        mov     eax, CSR9_SR + CSR9_RD + CSR9_SROM_CS
        out     dx , eax
        SROM_Delay
        
        dec     ecx
        jnz     .loop_read
        
        mov     eax, esi
 
        DEBUGF 1,"%x\n", ax
 
        ret
 
 
 
 
 
 
 
;<<<<<<<<<<<<<<<<<<<<<<<<<<<<
 
 
 
;*********************************************************************
;* Media Descriptor Code                                             *
;*********************************************************************
 
; MII transceiver control section.
; Read and write the MII registers using software-generated serial
; MDIO protocol.  See the MII specifications or DP83840A data sheet
; for details.
 
; The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
; met by back-to-back PCI I/O cycles, but we insert a delay to avoid
; "overclocking" issues or future 66Mhz PCI.
 
; Read and write the MII registers using software-generated serial
; MDIO protocol.  It is just different enough from the EEPROM protocol
; to not share code.  The maxium data clock rate is 2.5 Mhz.
 
MDIO_SHIFT_CLK          =        0x10000
MDIO_DATA_WRITE0        =        0x00000
MDIO_DATA_WRITE1        =        0x20000
MDIO_ENB                =        0x00000         ; Ignore the 0x02000 databook setting.
MDIO_ENB_IN             =        0x40000
MDIO_DATA_READ          =        0x80000
 
; MII transceiver control section.
; Read and write the MII registers using software-generated serial
; MDIO protocol.  See the MII specifications or DP83840A data sheet
; for details.
 
align 4
mdio_read:      ; phy_id:edx, location:esi
 
        DEBUGF  1,"mdio read, phy=%x, location=%x", edx, esi
 
        shl     edx, 5
        or      esi, edx
        or      esi, 0xf6 shl 10
 
        set_io  0
        set_io  CSR9
 
;    if (tp->chip_id == LC82C168) {
;        int i = 1000;
;        outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
;        inl(ioaddr + 0xA0);
;        inl(ioaddr + 0xA0);
;        while (--i > 0)
;            if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
;                return retval & 0xffff;
;        return 0xffff;
;    }
;
;    if (tp->chip_id == COMET) {
;        if (phy_id == 1) {
;            if (location < 7)
;                return inl(ioaddr + 0xB4 + (location<<2));
;            else if (location == 17)
;                return inl(ioaddr + 0xD0);
;            else if (location >= 29 && location <= 31)
;                return inl(ioaddr + 0xD4 + ((location-29)<<2));
;        }
;        return 0xffff;
;    }
 
; Establish sync by sending at least 32 logic ones.
 
        mov     ecx, 32
  .loop:
        mov     eax, MDIO_ENB or MDIO_DATA_WRITE1
        out     dx, eax
        MDIO_Delay
 
        or      eax, MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        dec     ecx
        jnz     .loop
 
 
; Shift the read command bits out.
 
        mov     ecx, 1 shl 15
  .loop2:
        mov     eax, MDIO_ENB
        test    esi, ecx
        jz      @f
        or      eax, MDIO_DATA_WRITE1
       @@:
        out     dx, eax
        MDIO_Delay
 
        or      eax, MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        shr     ecx, 1
        jnz     .loop2
 
 
; Read the two transition, 16 data, and wire-idle bits.
 
        xor     esi, esi
        mov     ecx, 19
  .loop3:
        mov     eax, MDIO_ENB_IN
        out     dx, eax
        MDIO_Delay
 
        shl     esi, 1
        in      eax, dx
        test    eax, MDIO_DATA_READ
        jz      @f
        inc     esi
       @@:
 
        mov     eax, MDIO_ENB_IN or MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        dec     ecx
        jnz     .loop3
 
        shr     esi, 1
        movzx   eax, si
 
        DEBUGF  1,", data=%x\n", ax
 
        ret
 
 
 
 
align 4
mdio_write:     ;int phy_id: edx, int location: edi, int value: ax)
 
        DEBUGF  1,"mdio write, phy=%x, location=%x, data=%x\n", edx, edi, ax
 
        shl     edi, 18
        or      edi, 0x5002 shl 16
        shl     edx, 23
        or      edi, edx
        mov     di, ax
 
        set_io  0
        set_io  CSR9
 
;    if (tp->chip_id == LC82C168) {
;        int i = 1000;
;        outl(cmd, ioaddr + 0xA0);
;        do
;            if ( ! (inl(ioaddr + 0xA0) & 0x80000000))
;                break;
;        while (--i > 0);
;        return;
;    }
 
;    if (tp->chip_id == COMET) {
;        if (phy_id != 1)
;            return;
;        if (location < 7)
;            outl(value, ioaddr + 0xB4 + (location<<2));
;        else if (location == 17)
;            outl(value, ioaddr + 0xD0);
;        else if (location >= 29 && location <= 31)
;            outl(value, ioaddr + 0xD4 + ((location-29)<<2));
;        return;
;    }
 
 
; Establish sync by sending at least 32 logic ones.
 
        mov     ecx, 32
  .loop:
        mov     eax, MDIO_ENB or MDIO_DATA_WRITE1
        out     dx, eax
        MDIO_Delay
 
        or      eax, MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        dec     ecx
        jnz     .loop
 
 
; Shift the command bits out.
 
        mov     ecx, 1 shl 31
  .loop2:
        mov     eax, MDIO_ENB
        test    edi, ecx
        jz      @f
        or      eax, MDIO_DATA_WRITE1
       @@:
        out     dx, eax
        MDIO_Delay
 
        or      eax, MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        shr     ecx, 1
        jnz     .loop2
 
 
; Clear out extra bits.
 
        mov     ecx, 2
  .loop3:
        mov     eax, MDIO_ENB
        out     dx, eax
        MDIO_Delay
 
        or      eax, MDIO_SHIFT_CLK
        out     dx, eax
        MDIO_Delay
 
        dec     ecx
        jnz     .loop3
 
        ret
 
 
; End of code
align 4                                         ; Place all initialised data here
 
devices       dd 0
version       dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF)
my_service    db 'DEC21X4X',0                    ; max 16 chars include zero
 
include_debug_strings                           ; All data wich FDO uses will be included here
 
section '.data' data readable writable align 16 ; place all uninitialized data place here
 
device_list rd MAX_DEVICES                     ; This list contains all pointers to device structures the driver is handling
;>
;>
;>
;>
;>
;>
;>
;>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>
 
 
 
;*********************************************************************
;*>

Rev 4467	Rev 4470
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; DEC 21x4x driver for KolibriOS ;;	6	;; DEC 21x4x driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; Based on dec21140.Asm from Solar OS by ;;	8	;; Based on dec21140.Asm from Solar OS by ;;
9	;; Eugen Brasoveanu, ;;	9	;; Eugen Brasoveanu, ;;
10	;; Ontanu Bogdan Valentin ;;	10	;; Ontanu Bogdan Valentin ;;
11	;; ;;	11	;; ;;
12	;; Written by hidnplayr@kolibrios.org ;;	12	;; Written by hidnplayr@kolibrios.org ;;
13	;; ;;	13	;; ;;
14	;; GNU GENERAL PUBLIC LICENSE ;;	14	;; GNU GENERAL PUBLIC LICENSE ;;
15	;; Version 2, June 1991 ;;	15	;; Version 2, June 1991 ;;
16	;; ;;	16	;; ;;
17	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	17	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18		18
19	format MS COFF	19	format MS COFF
20		20
21	API_VERSION = 0x01000100	21	API_VERSION = 0x01000100
22	DRIVER_VERSION = 5	22	DRIVER_VERSION = 5
23		23
24	MAX_DEVICES = 16	24	MAX_DEVICES = 16
25		25
26	RX_DES_COUNT = 4 ; no of RX descriptors, must be power of 2	26	RX_DES_COUNT = 4 ; no of RX descriptors, must be power of 2
27	RX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK	27	RX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
28		28
29	TX_DES_COUNT = 4 ; no of TX descriptors, must be power of 2	29	TX_DES_COUNT = 4 ; no of TX descriptors, must be power of 2
30	TX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, used for memory allocation only	30	TX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, used for memory allocation only
31		31
32		32
33	DEBUG = 1	33	DEBUG = 1
34	__DEBUG__ = 1	34	__DEBUG__ = 1
35	__DEBUG_LEVEL__ = 2	35	__DEBUG_LEVEL__ = 2
36		36
37	include '../struct.inc'	37	include '../struct.inc'
38	include '../macros.inc'	38	include '../macros.inc'
39	include '../proc32.inc'	39	include '../proc32.inc'
40	include '../imports.inc'	40	include '../imports.inc'
41	include '../fdo.inc'	41	include '../fdo.inc'
42	include '../netdrv.inc'	42	include '../netdrv.inc'
43		43
44	public START	44	public START
45	public service_proc	45	public service_proc
46	public version	46	public version
47		47
48	virtual at ebx	48	virtual at ebx
49		49
50	device:	50	device:
51		51
52	ETH_DEVICE	52	ETH_DEVICE
53		53
54	.rx_p_des dd ? ; descriptors ring with received packets	54	.rx_p_des dd ? ; descriptors ring with received packets
55	.tx_p_des dd ? ; descriptors ring with 'to transmit' packets	55	.tx_p_des dd ? ; descriptors ring with 'to transmit' packets
56	.tx_free_des dd ? ; Tx descriptors available	56	.tx_free_des dd ? ; Tx descriptors available
57	.tx_wr_des dd ? ; Tx current descriptor to write data to	57	.tx_wr_des dd ? ; Tx current descriptor to write data to
58	.tx_rd_des dd ? ; Tx current descriptor to read TX completion	58	.tx_rd_des dd ? ; Tx current descriptor to read TX completion
59	.rx_crt_des dd ? ; Rx current descriptor	59	.rx_crt_des dd ? ; Rx current descriptor
60		60
61	.io_addr dd ?	61	.io_addr dd ?
62	.pci_bus dd ?	62	.pci_bus dd ?
63	.pci_dev dd ?	63	.pci_dev dd ?
64	.irq_line db ?	64	.irq_line db ?
65		65
66	.size = $ - device	66	.size = $ - device
67		67
68	end virtual	68	end virtual
69		69
70	;-------------------------------------------	70	;-------------------------------------------
71	; configuration registers	71	; configuration registers
72	;-------------------------------------------	72	;-------------------------------------------
73	CFCS = 4 ; configuration and status register	73	CFCS = 4 ; configuration and status register
74		74
75	CSR0 = 0x00 ; Bus mode	75	CSR0 = 0x00 ; Bus mode
76	CSR1 = 0x08 ; Transmit Poll Command	76	CSR1 = 0x08 ; Transmit Poll Command
77	CSR2 = 0x10 ; Receive Poll Command	77	CSR2 = 0x10 ; Receive Poll Command
78	CSR3 = 0x18 ; Receive list base address	78	CSR3 = 0x18 ; Receive list base address
79	CSR4 = 0x20 ; Transmit list base address	79	CSR4 = 0x20 ; Transmit list base address
80	CSR5 = 0x28 ; Status	80	CSR5 = 0x28 ; Status
81	CSR6 = 0x30 ; Operation mode	81	CSR6 = 0x30 ; Operation mode
82	CSR7 = 0x38 ; Interrupt enable	82	CSR7 = 0x38 ; Interrupt enable
83	CSR8 = 0x40 ; Missed frames and overflow counter	83	CSR8 = 0x40 ; Missed frames and overflow counter
84	CSR9 = 0x48 ; Boot ROM, serial ROM, and MII management	84	CSR9 = 0x48 ; Boot ROM, serial ROM, and MII management
85	CSR10 = 0x50 ; Boot ROM programming address	85	CSR10 = 0x50 ; Boot ROM programming address
86	CSR11 = 0x58 ; General-purpose timer	86	CSR11 = 0x58 ; General-purpose timer
87	CSR12 = 0x60 ; General-purpose port	87	CSR12 = 0x60 ; General-purpose port
88	CSR13 = 0x68	88	CSR13 = 0x68
89	CSR14 = 0x70	89	CSR14 = 0x70
90	CSR15 = 0x78 ; Watchdog timer	90	CSR15 = 0x78 ; Watchdog timer
91		91
92	;--------bits/commands of CSR0-------------------	92	;--------bits/commands of CSR0-------------------
93	CSR0_RESET = 1b	93	CSR0_RESET = 1b
94		94
95	CSR0_WIE = 1 shl 24 ; Write and Invalidate Enable	95	CSR0_WIE = 1 shl 24 ; Write and Invalidate Enable
96	CSR0_RLE = 1 shl 23 ; PCI Read Line Enable	96	CSR0_RLE = 1 shl 23 ; PCI Read Line Enable
97	CSR0_RML = 1 shl 21 ; PCI Read Multiple	97	CSR0_RML = 1 shl 21 ; PCI Read Multiple
98		98
99	CSR0_CACHEALIGN_NONE = 00b shl 14	99	CSR0_CACHEALIGN_NONE = 00b shl 14
100	CSR0_CACHEALIGN_32 = 01b shl 14	100	CSR0_CACHEALIGN_32 = 01b shl 14
101	CSR0_CACHEALIGN_64 = 10b shl 14	101	CSR0_CACHEALIGN_64 = 10b shl 14
102	CSR0_CACHEALIGN_128 = 11b shl 14	102	CSR0_CACHEALIGN_128 = 11b shl 14
103		103
104	; using values from linux driver..	104	; using values from linux driver..
105	CSR0_DEFAULT = CSR0_WIE + CSR0_RLE + CSR0_RML + CSR0_CACHEALIGN_NONE	105	CSR0_DEFAULT = CSR0_WIE + CSR0_RLE + CSR0_RML + CSR0_CACHEALIGN_NONE
106		106
107	;------- CSR5 -STATUS- bits --------------------------------	107	;------- CSR5 -STATUS- bits --------------------------------
108	CSR5_TI = 1 shl 0 ; Transmit interupt - frame transmition completed	108	CSR5_TI = 1 shl 0 ; Transmit interupt - frame transmition completed
109	CSR5_TPS = 1 shl 1 ; Transmit process stopped	109	CSR5_TPS = 1 shl 1 ; Transmit process stopped
110	CSR5_TU = 1 shl 2 ; Transmit Buffer unavailable	110	CSR5_TU = 1 shl 2 ; Transmit Buffer unavailable
111	CSR5_TJT = 1 shl 3 ; Transmit Jabber Timeout (transmitter had been excessively active)	111	CSR5_TJT = 1 shl 3 ; Transmit Jabber Timeout (transmitter had been excessively active)
112	CSR5_UNF = 1 shl 5 ; Transmit underflow - FIFO underflow	112	CSR5_UNF = 1 shl 5 ; Transmit underflow - FIFO underflow
113	CSR5_RI = 1 shl 6 ; Receive Interrupt	113	CSR5_RI = 1 shl 6 ; Receive Interrupt
114	CSR5_RU = 1 shl 7 ; Receive Buffer unavailable	114	CSR5_RU = 1 shl 7 ; Receive Buffer unavailable
115	CSR5_RPS = 1 shl 8 ; Receive Process stopped	115	CSR5_RPS = 1 shl 8 ; Receive Process stopped
116	CSR5_RWT = 1 shl 9 ; Receive Watchdow Timeout	116	CSR5_RWT = 1 shl 9 ; Receive Watchdow Timeout
117	CSR5_ETI = 1 shl 10 ; Early transmit Interrupt	117	CSR5_ETI = 1 shl 10 ; Early transmit Interrupt
118	CSR5_GTE = 1 shl 11 ; General Purpose Timer Expired	118	CSR5_GTE = 1 shl 11 ; General Purpose Timer Expired
119	CSR5_FBE = 1 shl 13 ; Fatal bus error	119	CSR5_FBE = 1 shl 13 ; Fatal bus error
120	CSR5_ERI = 1 shl 14 ; Early receive Interrupt	120	CSR5_ERI = 1 shl 14 ; Early receive Interrupt
121	CSR5_AIS = 1 shl 15 ; Abnormal interrupt summary	121	CSR5_AIS = 1 shl 15 ; Abnormal interrupt summary
122	CSR5_NIS = 1 shl 16 ; normal interrupt summary	122	CSR5_NIS = 1 shl 16 ; normal interrupt summary
123	CSR5_RS_SH = 17 ; Receive process state -shift	123	CSR5_RS_SH = 17 ; Receive process state -shift
124	CSR5_RS_MASK = 111b ; -mask	124	CSR5_RS_MASK = 111b ; -mask
125	CSR5_TS_SH = 20 ; Transmit process state -shift	125	CSR5_TS_SH = 20 ; Transmit process state -shift
126	CSR5_TS_MASK = 111b ; -mask	126	CSR5_TS_MASK = 111b ; -mask
127	CSR5_EB_SH = 23 ; Error bits -shift	127	CSR5_EB_SH = 23 ; Error bits -shift
128	CSR5_EB_MASK = 111b ; Error bits -mask	128	CSR5_EB_MASK = 111b ; Error bits -mask
129		129
130	;CSR5 TS values	130	;CSR5 TS values
131	CSR5_TS_STOPPED = 000b	131	CSR5_TS_STOPPED = 000b
132	CSR5_TS_RUNNING_FETCHING_DESC = 001b	132	CSR5_TS_RUNNING_FETCHING_DESC = 001b
133	CSR5_TS_RUNNING_WAITING_TX = 010b	133	CSR5_TS_RUNNING_WAITING_TX = 010b
134	CSR5_TS_RUNNING_READING_BUFF = 011b	134	CSR5_TS_RUNNING_READING_BUFF = 011b
135	CSR5_TS_RUNNING_SETUP_PCKT = 101b	135	CSR5_TS_RUNNING_SETUP_PCKT = 101b
136	CSR5_TS_SUSPENDED = 110b	136	CSR5_TS_SUSPENDED = 110b
137	CSR5_TS_RUNNING_CLOSING_DESC = 111b	137	CSR5_TS_RUNNING_CLOSING_DESC = 111b
138		138
139	;------- CSR6 -OPERATION MODE- bits --------------------------------	139	;------- CSR6 -OPERATION MODE- bits --------------------------------
140	CSR6_HP = 1 shl 0 ; Hash/Perfect Receive Filtering mode	140	CSR6_HP = 1 shl 0 ; Hash/Perfect Receive Filtering mode
141	CSR6_SR = 1 shl 1 ; Start/Stop receive	141	CSR6_SR = 1 shl 1 ; Start/Stop receive
142	CSR6_HO = 1 shl 2 ; Hash only Filtering mode	142	CSR6_HO = 1 shl 2 ; Hash only Filtering mode
143	CSR6_PB = 1 shl 3 ; Pass bad frames	143	CSR6_PB = 1 shl 3 ; Pass bad frames
144	CSR6_IF = 1 shl 4 ; Inverse filtering	144	CSR6_IF = 1 shl 4 ; Inverse filtering
145	CSR6_SB = 1 shl 5 ; Start/Stop backoff counter	145	CSR6_SB = 1 shl 5 ; Start/Stop backoff counter
146	CSR6_PR = 1 shl 6 ; Promiscuos mode -default after reset	146	CSR6_PR = 1 shl 6 ; Promiscuos mode -default after reset
147	CSR6_PM = 1 shl 7 ; Pass all multicast	147	CSR6_PM = 1 shl 7 ; Pass all multicast
148	CSR6_F = 1 shl 9 ; Full Duplex mode	148	CSR6_F = 1 shl 9 ; Full Duplex mode
149	CSR6_OM_SH = 10 ; Operating Mode -shift	149	CSR6_OM_SH = 10 ; Operating Mode -shift
150	CSR6_OM_MASK = 11b ; -mask	150	CSR6_OM_MASK = 11b ; -mask
151	CSR6_FC = 1 shl 12 ; Force Collision Mode	151	CSR6_FC = 1 shl 12 ; Force Collision Mode
152	CSR6_ST = 1 shl 13 ; Start/Stop Transmission Command	152	CSR6_ST = 1 shl 13 ; Start/Stop Transmission Command
153	CSR6_TR_SH = 14 ; Threshold Control -shift	153	CSR6_TR_SH = 14 ; Threshold Control -shift
154	CSR6_TR_MASK = 11b ; -mask	154	CSR6_TR_MASK = 11b ; -mask
155	CSR6_CA = 1 shl 17 ; Capture Effect Enable	155	CSR6_CA = 1 shl 17 ; Capture Effect Enable
156	CSR6_PS = 1 shl 18 ; Port select SRL / MII/SYM	156	CSR6_PS = 1 shl 18 ; Port select SRL / MII/SYM
157	CSR6_HBD = 1 shl 19 ; Heartbeat Disable	157	CSR6_HBD = 1 shl 19 ; Heartbeat Disable
158	CSR6_SF = 1 shl 21 ; Store and Forward -transmit full packet only	158	CSR6_SF = 1 shl 21 ; Store and Forward -transmit full packet only
159	CSR6_TTM = 1 shl 22 ; Transmit Threshold Mode -	159	CSR6_TTM = 1 shl 22 ; Transmit Threshold Mode -
160	CSR6_PCS = 1 shl 23 ; PCS active and MII/SYM port operates in symbol mode	160	CSR6_PCS = 1 shl 23 ; PCS active and MII/SYM port operates in symbol mode
161	CSR6_SCR = 1 shl 24 ; Scrambler Mode	161	CSR6_SCR = 1 shl 24 ; Scrambler Mode
162	CSR6_MBO = 1 shl 25 ; Must Be One	162	CSR6_MBO = 1 shl 25 ; Must Be One
163	CSR6_RA = 1 shl 30 ; Receive All	163	CSR6_RA = 1 shl 30 ; Receive All
164	CSR6_SC = 1 shl 31 ; Special Capture Effect Enable	164	CSR6_SC = 1 shl 31 ; Special Capture Effect Enable
165		165
166		166
167	;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------	167	;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------
168	CSR7_TI = 1 shl 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )	168	CSR7_TI = 1 shl 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
169	CSR7_TS = 1 shl 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )	169	CSR7_TS = 1 shl 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
170	CSR7_TU = 1 shl 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )	170	CSR7_TU = 1 shl 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
171	CSR7_TJ = 1 shl 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )	171	CSR7_TJ = 1 shl 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
172	CSR7_UN = 1 shl 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )	172	CSR7_UN = 1 shl 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
173	CSR7_RI = 1 shl 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )	173	CSR7_RI = 1 shl 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
174	CSR7_RU = 1 shl 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )	174	CSR7_RU = 1 shl 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
175	CSR7_RS = 1 shl 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> )	175	CSR7_RS = 1 shl 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
176	CSR7_RW = 1 shl 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )	176	CSR7_RW = 1 shl 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
177	CSR7_ETE = 1 shl 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )	177	CSR7_ETE = 1 shl 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
178	CSR7_GPT = 1 shl 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> )	178	CSR7_GPT = 1 shl 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> )
179	CSR7_FBE = 1 shl 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> )	179	CSR7_FBE = 1 shl 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> )
180	CSR7_ERE = 1 shl 14 ; Early receive enable (set with CSR7<16> & CSR5<14> )	180	CSR7_ERE = 1 shl 14 ; Early receive enable (set with CSR7<16> & CSR5<14> )
181	CSR7_AI = 1 shl 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>)	181	CSR7_AI = 1 shl 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>)
182	CSR7_NI = 1 shl 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>)	182	CSR7_NI = 1 shl 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>)
183		183
184	CSR7_DEFAULT = CSR7_TI + CSR7_TS + CSR7_RI + CSR7_RS + CSR7_TU + CSR7_TJ + CSR7_UN + \	184	CSR7_DEFAULT = CSR7_TI + CSR7_TS + CSR7_RI + CSR7_RS + CSR7_TU + CSR7_TJ + CSR7_UN + \
185	CSR7_RU + CSR7_RW + CSR7_FBE + CSR7_AI + CSR7_NI	185	CSR7_RU + CSR7_RW + CSR7_FBE + CSR7_AI + CSR7_NI
186		186
187	;----------- descriptor structure ---------------------	187	;----------- descriptor structure ---------------------
188	struc DES {	188	struc DES {
189	.status dd ? ; bit 31 is 'own' and rest is 'status'	189	.status dd ? ; bit 31 is 'own' and rest is 'status'
190	.length dd ? ; control bits + bytes-count buffer 1 + bytes-count buffer 2	190	.length dd ? ; control bits + bytes-count buffer 1 + bytes-count buffer 2
191	.buffer1 dd ? ; pointer to buffer1	191	.buffer1 dd ? ; pointer to buffer1
192	.buffer2 dd ? ; pointer to buffer2 or in this case to next descriptor, as we use a chained structure	192	.buffer2 dd ? ; pointer to buffer2 or in this case to next descriptor, as we use a chained structure
193	.virtaddr dd ?	193	.virtaddr dd ?
194	.size = 64 ; 64, for alignment purposes	194	.size = 64 ; 64, for alignment purposes
195	}	195	}
196		196
197	virtual at 0	197	virtual at 0
198	DES DES	198	DES DES
199	end virtual	199	end virtual
200		200
201	;common to Rx and Tx	201	;common to Rx and Tx
202	DES0_OWN = 1 shl 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors	202	DES0_OWN = 1 shl 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
203		203
204	;receive	204	;receive
205	RDES0_ZER = 1 shl 0 ; must be 0 if legal length :D	205	RDES0_ZER = 1 shl 0 ; must be 0 if legal length :D
206	RDES0_CE = 1 shl 1 ; CRC error, valid only on last desc (RDES0<8>=1)	206	RDES0_CE = 1 shl 1 ; CRC error, valid only on last desc (RDES0<8>=1)
207	RDES0_DB = 1 shl 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)	207	RDES0_DB = 1 shl 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
208	RDES0_RE = 1 shl 3 ; Report on MII error.. i dont realy know what this means :P	208	RDES0_RE = 1 shl 3 ; Report on MII error.. i dont realy know what this means :P
209	RDES0_RW = 1 shl 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)	209	RDES0_RW = 1 shl 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
210	RDES0_FT = 1 shl 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)	210	RDES0_FT = 1 shl 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
211	RDES0_CS = 1 shl 6 ; Collision seen, valid only on last desc (RDES0<8>=1)	211	RDES0_CS = 1 shl 6 ; Collision seen, valid only on last desc (RDES0<8>=1)
212	RDES0_TL = 1 shl 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)	212	RDES0_TL = 1 shl 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
213	RDES0_LS = 1 shl 8 ; Last descriptor of current frame	213	RDES0_LS = 1 shl 8 ; Last descriptor of current frame
214	RDES0_FS = 1 shl 9 ; First descriptor of current frame	214	RDES0_FS = 1 shl 9 ; First descriptor of current frame
215	RDES0_MF = 1 shl 10 ; Multicast frame, valid only on last desc (RDES0<8>=1)	215	RDES0_MF = 1 shl 10 ; Multicast frame, valid only on last desc (RDES0<8>=1)
216	RDES0_RF = 1 shl 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow	216	RDES0_RF = 1 shl 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
217	RDES0_DT_SERIAL = 00b shl 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)	217	RDES0_DT_SERIAL = 00b shl 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
218	RDES0_DT_INTERNAL = 01b shl 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)	218	RDES0_DT_INTERNAL = 01b shl 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
219	RDES0_DT_EXTERNAL = 11b shl 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)	219	RDES0_DT_EXTERNAL = 11b shl 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
220	RDES0_DE = 1 shl 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)	220	RDES0_DE = 1 shl 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
221	RDES0_ES = 1 shl 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)	221	RDES0_ES = 1 shl 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
222	RDES0_FL_SH = 16 ; Field length shift, valid only on last desc (RDES0<8>=1)	222	RDES0_FL_SH = 16 ; Field length shift, valid only on last desc (RDES0<8>=1)
223	RDES0_FL_MASK = 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)	223	RDES0_FL_MASK = 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
224	RDES0_FF = 1 shl 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)	224	RDES0_FF = 1 shl 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
225		225
226	RDES1_RBS1_MASK = 11111111111b ; first buffer size MASK	226	RDES1_RBS1_MASK = 11111111111b ; first buffer size MASK
227	RDES1_RBS2_SH = 11 ; second buffer size SHIFT	227	RDES1_RBS2_SH = 11 ; second buffer size SHIFT
228	RDES1_RBS2_MASK = 11111111111b ; second buffer size MASK	228	RDES1_RBS2_MASK = 11111111111b ; second buffer size MASK
229	RDES1_RCH = 1 shl 24 ; Second address chained - second address (buffer) is next desc address	229	RDES1_RCH = 1 shl 24 ; Second address chained - second address (buffer) is next desc address
230	RDES1_RER = 1 shl 25 ; Receive End of Ring - final descriptor, NIC must return to first desc	230	RDES1_RER = 1 shl 25 ; Receive End of Ring - final descriptor, NIC must return to first desc
231		231
232	;transmition	232	;transmition
233	TDES0_DE = 1 shl 0 ; Deffered	233	TDES0_DE = 1 shl 0 ; Deffered
234	TDES0_UF = 1 shl 1 ; Underflow error	234	TDES0_UF = 1 shl 1 ; Underflow error
235	TDES0_LF = 1 shl 2 ; Link fail report (only if CSR6<23>=1)	235	TDES0_LF = 1 shl 2 ; Link fail report (only if CSR6<23>=1)
236	TDES0_CC_SH = 3 ; Collision Count shift - no of collision before transmition	236	TDES0_CC_SH = 3 ; Collision Count shift - no of collision before transmition
237	TDES0_CC_MASK = 1111b ; Collision Count mask	237	TDES0_CC_MASK = 1111b ; Collision Count mask
238	TDES0_HF = 1 shl 7 ; Heartbeat fail	238	TDES0_HF = 1 shl 7 ; Heartbeat fail
239	TDES0_EC = 1 shl 8 ; Excessive Collisions - >16 collisions	239	TDES0_EC = 1 shl 8 ; Excessive Collisions - >16 collisions
240	TDES0_LC = 1 shl 9 ; Late collision	240	TDES0_LC = 1 shl 9 ; Late collision
241	TDES0_NC = 1 shl 10 ; No carrier	241	TDES0_NC = 1 shl 10 ; No carrier
242	TDES0_LO = 1 shl 11 ; Loss of carrier	242	TDES0_LO = 1 shl 11 ; Loss of carrier
243	TDES0_TO = 1 shl 14 ; Transmit Jabber Timeout	243	TDES0_TO = 1 shl 14 ; Transmit Jabber Timeout
244	TDES0_ES = 1 shl 15 ; Error summary TDES0<1+8+9+10+11+14>=1	244	TDES0_ES = 1 shl 15 ; Error summary TDES0<1+8+9+10+11+14>=1
245		245
246	TDES1_TBS1_MASK = 11111111111b ; Buffer 1 size mask	246	TDES1_TBS1_MASK = 11111111111b ; Buffer 1 size mask
247	TDES1_TBS2_SH = 11 ; Buffer 2 size shift	247	TDES1_TBS2_SH = 11 ; Buffer 2 size shift
248	TDES1_TBS2_MASK = 11111111111b ; Buffer 2 size mask	248	TDES1_TBS2_MASK = 11111111111b ; Buffer 2 size mask
249	TDES1_FT0 = 1 shl 22 ; Filtering type 0	249	TDES1_FT0 = 1 shl 22 ; Filtering type 0
250	TDES1_DPD = 1 shl 23 ; Disabled padding for packets <64bytes, no padding	250	TDES1_DPD = 1 shl 23 ; Disabled padding for packets <64bytes, no padding
251	TDES1_TCH = 1 shl 24 ; Second address chained - second buffer pointer is to next desc	251	TDES1_TCH = 1 shl 24 ; Second address chained - second buffer pointer is to next desc
252	TDES1_TER = 1 shl 25 ; Transmit end of ring - final descriptor	252	TDES1_TER = 1 shl 25 ; Transmit end of ring - final descriptor
253	TDES1_AC = 1 shl 26 ; Add CRC disable -pretty obvious	253	TDES1_AC = 1 shl 26 ; Add CRC disable -pretty obvious
254	TDES1_SET = 1 shl 27 ; Setup packet	254	TDES1_SET = 1 shl 27 ; Setup packet
255	TDES1_FT1 = 1 shl 28 ; Filtering type 1	255	TDES1_FT1 = 1 shl 28 ; Filtering type 1
256	TDES1_FS = 1 shl 29 ; First segment - buffer is first segment of frame	256	TDES1_FS = 1 shl 29 ; First segment - buffer is first segment of frame
257	TDES1_LS = 1 shl 30 ; Last segment	257	TDES1_LS = 1 shl 30 ; Last segment
258	TDES1_IC = 1 shl 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1	258	TDES1_IC = 1 shl 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
259		259
260	MAX_ETH_FRAME_SIZE = 1514	260	MAX_ETH_FRAME_SIZE = 1514
261		261
262	RX_MEM_TOTAL_SIZE = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)	262	RX_MEM_TOTAL_SIZE = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
263	TX_MEM_TOTAL_SIZE = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)	263	TX_MEM_TOTAL_SIZE = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
264		264
265	;=============================================================================	265	;=============================================================================
266	; serial ROM operations	266	; serial ROM operations
267	;=============================================================================	267	;=============================================================================
268	CSR9_SR = 1 shl 11 ; SROM Select	268	CSR9_SR = 1 shl 11 ; SROM Select
269	CSR9_RD = 1 shl 14 ; ROM Read Operation	269	CSR9_RD = 1 shl 14 ; ROM Read Operation
270	CSR9_SROM_DO = 1 shl 3 ; Data Out for SROM	270	CSR9_SROM_DO = 1 shl 3 ; Data Out for SROM
271	CSR9_SROM_DI = 1 shl 2 ; Data In to SROM	271	CSR9_SROM_DI = 1 shl 2 ; Data In to SROM
272	CSR9_SROM_CK = 1 shl 1 ; clock for SROM	272	CSR9_SROM_CK = 1 shl 1 ; clock for SROM
273	CSR9_SROM_CS = 1 shl 0 ; chip select.. always needed	273	CSR9_SROM_CS = 1 shl 0 ; chip select.. always needed
274		274
275	; assume dx is CSR9	275	; assume dx is CSR9
276	macro SROM_Delay {	276	macro SROM_Delay {
277	push eax	277	push eax
278	in eax, dx	278	in eax, dx
279	in eax, dx	279	in eax, dx
280	in eax, dx	280	in eax, dx
281	in eax, dx	281	in eax, dx
282	in eax, dx	282	in eax, dx
283	in eax, dx	283	in eax, dx
284	in eax, dx	284	in eax, dx
285	in eax, dx	285	in eax, dx
286	in eax, dx	286	in eax, dx
287	in eax, dx	287	in eax, dx
288	pop eax	288	pop eax
289	}	289	}
290		290
291	; assume dx is CSR9	291	; assume dx is CSR9
292	macro MDIO_Delay {	292	macro MDIO_Delay {
293	push eax	293	push eax
294	in eax, dx	294	in eax, dx
295	pop eax	295	pop eax
296	}	296	}
297		297
298	macro Bit_Set a_bit {	298	macro Bit_Set a_bit {
299	in eax, dx	299	in eax, dx
300	or eax, a_bit	300	or eax, a_bit
301	out dx , eax	301	out dx , eax
302	}	302	}
303		303
304	macro Bit_Clear a_bit {	304	macro Bit_Clear a_bit {
305	in eax, dx	305	in eax, dx
306	and eax, not (a_bit)	306	and eax, not (a_bit)
307	out dx, eax	307	out dx, eax
308	}	308	}
309		309
310		310
311	section '.flat' code readable align 16	311	section '.flat' code readable align 16
312		312
313	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	313	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
314	;; ;;	314	;; ;;
315	;; proc START ;;	315	;; proc START ;;
316	;; ;;	316	;; ;;
317	;; (standard driver proc) ;;	317	;; (standard driver proc) ;;
318	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	318	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
319		319
320	align 4	320	align 4
321	proc START stdcall, state:dword	321	proc START stdcall, state:dword
322		322
323	cmp [state], 1	323	cmp [state], 1
324	jne .exit	324	jne .exit
325		325
326	.entry:	326	.entry:
327		327
328	DEBUGF 2,"Loading %s driver\n", my_service	328	DEBUGF 2,"Loading %s driver\n", my_service
329	stdcall RegService, my_service, service_proc	329	stdcall RegService, my_service, service_proc
330	ret	330	ret
331		331
332	.fail:	332	.fail:
333	.exit:	333	.exit:
334	xor eax, eax	334	xor eax, eax
335	ret	335	ret
336		336
337	endp	337	endp
338		338
339		339
340	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	340	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
341	;; ;;	341	;; ;;
342	;; proc SERVICE_PROC ;;	342	;; proc SERVICE_PROC ;;
343	;; ;;	343	;; ;;
344	;; (standard driver proc) ;;	344	;; (standard driver proc) ;;
345	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	345	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
346		346
347	align 4	347	align 4
348	proc service_proc stdcall, ioctl:dword	348	proc service_proc stdcall, ioctl:dword
349		349
350	mov edx, [ioctl]	350	mov edx, [ioctl]
351	mov eax, [IOCTL.io_code]	351	mov eax, [edx + IOCTL.io_code]
352		352
353	;------------------------------------------------------	353	;------------------------------------------------------
354		354
355	cmp eax, 0 ;SRV_GETVERSION	355	cmp eax, 0 ;SRV_GETVERSION
356	jne @F	356	jne @F
357		357
358	cmp [IOCTL.out_size], 4	358	cmp [edx + IOCTL.out_size], 4
359	jb .fail	359	jb .fail
360	mov eax, [IOCTL.output]	360	mov eax, [edx + IOCTL.output]
361	mov [eax], dword API_VERSION	361	mov [eax], dword API_VERSION
362		362
363	xor eax, eax	363	xor eax, eax
364	ret	364	ret
365		365
366	;------------------------------------------------------	366	;------------------------------------------------------
367	@@:	367	@@:
368	cmp eax, 1 ;SRV_HOOK	368	cmp eax, 1 ;SRV_HOOK
369	jne .fail	369	jne .fail
370		370
371	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	371	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
372	jb .fail	372	jb .fail
373		373
374	mov eax, [IOCTL.input]	374	mov eax, [edx + IOCTL.input]
375	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given	375	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
376	jne .fail ; other types arent supported for this card yet	376	jne .fail ; other types arent supported for this card yet
377		377
378	; check if the device is already listed	378	; check if the device is already listed
379		379
380	mov esi, device_list	380	mov esi, device_list
381	mov ecx, [devices]	381	mov ecx, [devices]
382	test ecx, ecx	382	test ecx, ecx
383	jz .firstdevice	383	jz .firstdevice
384		384
385	; mov eax, [IOCTL.input] ; get the pci bus and device numbers	385	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
386	mov ax , [eax+1] ;	386	mov ax, [eax+1] ;
387	.nextdevice:	387	.nextdevice:
388	mov ebx, [esi]	388	mov ebx, [esi]
389	cmp al, byte[device.pci_bus]	389	cmp al, byte[device.pci_bus]
390	jne @f	390	jne @f
391	cmp ah, byte[device.pci_dev]	391	cmp ah, byte[device.pci_dev]
392	je .find_devicenum ; Device is already loaded, let's find it's device number	392	je .find_devicenum ; Device is already loaded, let's find it's device number
393	@@:	393	@@:
394	add esi, 4	394	add esi, 4
395	loop .nextdevice	395	loop .nextdevice
396		396
397		397
398	; This device doesnt have its own eth_device structure yet, lets create one	398	; This device doesnt have its own eth_device structure yet, lets create one
399	.firstdevice:	399	.firstdevice:
400	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	400	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
401	jae .fail	401	jae .fail
402		402
403	push edx	403	push edx
404	stdcall KernelAlloc, dword device.size ; Allocate the buffer for eth_device structure	404	stdcall KernelAlloc, dword device.size ; Allocate the buffer for eth_device structure
405	pop edx	405	pop edx
406	test eax, eax	406	test eax, eax
407	jz .fail	407	jz .fail
408	mov ebx, eax ; ebx is always used as a pointer to the structure (in driver, but also in kernel code)	408	mov ebx, eax ; ebx is always used as a pointer to the structure (in driver, but also in kernel code)
409		409
410	; Fill in the direct call addresses into the struct	410	; Fill in the direct call addresses into the struct
411		411
412	mov [device.reset], reset	412	mov [device.reset], reset
413	mov [device.transmit], transmit	413	mov [device.transmit], transmit
414	mov [device.unload], unload	414	mov [device.unload], unload
415	mov [device.name], my_service	415	mov [device.name], my_service
416		416
417	; save the pci bus and device numbers	417	; save the pci bus and device numbers
418		418
419	mov eax, [IOCTL.input]	419	mov eax, [edx + IOCTL.input]
420	movzx ecx, byte[eax+1]	420	movzx ecx, byte[eax+1]
421	mov [device.pci_bus], ecx	421	mov [device.pci_bus], ecx
422	movzx ecx, byte[eax+2]	422	movzx ecx, byte[eax+2]
423	mov [device.pci_dev], ecx	423	mov [device.pci_dev], ecx
424		424
425	; Now, it's time to find the base io addres of the PCI device	425	; Now, it's time to find the base io addres of the PCI device
426		426
427	PCI_find_io	427	PCI_find_io
428		428
429	; We've found the io address, find IRQ now	429	; We've found the io address, find IRQ now
430		430
431	PCI_find_irq	431	PCI_find_irq
432		432
433	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	433	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
434	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8	434	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
435		435
436	allocate_and_clear [device.rx_p_des], RX_DES_COUNT*(DES.size+RX_BUFF_SIZE), .err	436	allocate_and_clear [device.rx_p_des], RX_DES_COUNT*(DES.size+RX_BUFF_SIZE), .err
437	allocate_and_clear [device.tx_p_des], TX_DES_COUNT*(DES.size+TX_BUFF_SIZE), .err	437	allocate_and_clear [device.tx_p_des], TX_DES_COUNT*(DES.size+TX_BUFF_SIZE), .err
438		438
439	; Ok, the eth_device structure is ready, let's probe the device	439	; Ok, the eth_device structure is ready, let's probe the device
440	; Because initialization fires IRQ, IRQ handler must be aware of this device	440	; Because initialization fires IRQ, IRQ handler must be aware of this device
441	mov eax, [devices] ; Add the device structure to our device list	441	mov eax, [devices] ; Add the device structure to our device list
442	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)	442	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)
443	inc [devices] ;	443	inc [devices] ;
444		444
445	call probe ; this function will output in eax	445	call probe ; this function will output in eax
446	test eax, eax	446	test eax, eax
447	jnz .err2 ; If an error occured, exit	447	jnz .err2 ; If an error occured, exit
448		448
449		449
450	mov [device.type], NET_TYPE_ETH	450	mov [device.type], NET_TYPE_ETH
451	call NetRegDev	451	call NetRegDev
452		452
453	cmp eax, -1	453	cmp eax, -1
454	je .destroy	454	je .destroy
455		455
456	ret	456	ret
457		457
458	; If the device was already loaded, find the device number and return it in eax	458	; If the device was already loaded, find the device number and return it in eax
459		459
460	.find_devicenum:	460	.find_devicenum:
461	DEBUGF 2,"Trying to find device number of already registered device\n"	461	DEBUGF 2,"Trying to find device number of already registered device\n"
462	call NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx	462	call NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
463	; into a device number in edi	463	; into a device number in edi
464	mov eax, edi ; Application wants it in eax instead	464	mov eax, edi ; Application wants it in eax instead
465	DEBUGF 2,"Kernel says: %u\n", eax	465	DEBUGF 2,"Kernel says: %u\n", eax
466	ret	466	ret
467		467
468	; If an error occured, remove all allocated data and exit (returning -1 in eax)	468	; If an error occured, remove all allocated data and exit (returning -1 in eax)
469		469
470	.destroy:	470	.destroy:
471	; todo: reset device into virgin state	471	; todo: reset device into virgin state
472		472
473	.err2:	473	.err2:
474	dec [devices]	474	dec [devices]
475	.err:	475	.err:
476	DEBUGF 2,"removing device structure\n"	476	DEBUGF 2,"removing device structure\n"
477	stdcall KernelFree, [device.rx_p_des]	477	stdcall KernelFree, [device.rx_p_des]
478	stdcall KernelFree, [device.tx_p_des]	478	stdcall KernelFree, [device.tx_p_des]
479	stdcall KernelFree, ebx	479	stdcall KernelFree, ebx
480		480
481		481
482	.fail:	482	.fail:
483	or eax, -1	483	or eax, -1
484	ret	484	ret
485		485
486	;------------------------------------------------------	486	;------------------------------------------------------
487	endp	487	endp
488		488
489		489
490	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;	490	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
491	;; ;;	491	;; ;;
492	;; Actual Hardware dependent code starts here ;;	492	;; Actual Hardware dependent code starts here ;;
493	;; ;;	493	;; ;;
494	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;	494	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
495		495
496		496
497		497
498	align 4	498	align 4
499	unload:	499	unload:
500	; TODO: (in this particular order)	500	; TODO: (in this particular order)

Subversion Repositories Kolibri OS

(root)/drivers/ethernet/dec21x4x.asm – Rev 4467 → 4470