WebSVN – Kolibri OS – Diff – /drivers/devman/pci/probe.c


#include 
#include 
#include 
#include 
#include 
 
LIST_HEAD(pci_root_buses);
 
#define IO_SPACE_LIMIT 0xffff
 
 
 
 
#define LEGACY_IO_RESOURCE  (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
#define CARDBUS_LATENCY_TIMER   176 /* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR   3
 
static int pcibios_assign_all_busses(void)
{
    return 0;
};
 
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
    return bus->self && bus->self->ari_enabled;
}
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
static u64 pci_size(u64 base, u64 maxbase, u64 mask)
{
    u64 size = mask & maxbase;  /* Find the significant bits */
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
{
    if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
        res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
        return pci_bar_io;
    }
 
    res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
    if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
        return pci_bar_mem64;
    return pci_bar_mem32;
}
 
 
 
/**
 * pci_read_base - read a PCI BAR
 * @dev: the PCI device
 * @type: type of the BAR
 * @res: resource buffer to be filled in
 * @pos: BAR position in the config space
 *
 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
 */
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
            struct resource *res, unsigned int pos)
{
    u32 l, sz, mask;
    u16 orig_cmd;
 
    mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 
    if (!dev->mmio_always_on) {
        pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
        pci_write_config_word(dev, PCI_COMMAND,
            orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
    }
 
    res->name = pci_name(dev);
 
    pci_read_config_dword(dev, pos, &l);
    pci_write_config_dword(dev, pos, l | mask);
    pci_read_config_dword(dev, pos, &sz);
    pci_write_config_dword(dev, pos, l);
 
    if (!dev->mmio_always_on)
        pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 
    /*
     * All bits set in sz means the device isn't working properly.
     * If the BAR isn't implemented, all bits must be 0.  If it's a
     * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
     * 1 must be clear.
     */
    if (!sz || sz == 0xffffffff)
        goto fail;
 
    /*
     * I don't know how l can have all bits set.  Copied from old code.
     * Maybe it fixes a bug on some ancient platform.
     */
    if (l == 0xffffffff)
        l = 0;
 
    if (type == pci_bar_unknown) {
        type = decode_bar(res, l);
        res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
        if (type == pci_bar_io) {
            l &= PCI_BASE_ADDRESS_IO_MASK;
            mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
        } else {
            l &= PCI_BASE_ADDRESS_MEM_MASK;
            mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
        }
    } else {
        res->flags |= (l & IORESOURCE_ROM_ENABLE);
        l &= PCI_ROM_ADDRESS_MASK;
        mask = (u32)PCI_ROM_ADDRESS_MASK;
    }
 
    if (type == pci_bar_mem64) {
        u64 l64 = l;
        u64 sz64 = sz;
        u64 mask64 = mask | (u64)~0 << 32;
 
        pci_read_config_dword(dev, pos + 4, &l);
        pci_write_config_dword(dev, pos + 4, ~0);
        pci_read_config_dword(dev, pos + 4, &sz);
        pci_write_config_dword(dev, pos + 4, l);
 
        l64 |= ((u64)l << 32);
        sz64 |= ((u64)sz << 32);
 
        sz64 = pci_size(l64, sz64, mask64);
 
        if (!sz64)
            goto fail;
 
        if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
            dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
                __FUNCTION__, pos);
            goto fail;
        }
 
        res->flags |= IORESOURCE_MEM_64;
        if ((sizeof(resource_size_t) < 8) && l) {
            /* Address above 32-bit boundary; disable the BAR */
            pci_write_config_dword(dev, pos, 0);
            pci_write_config_dword(dev, pos + 4, 0);
            res->start = 0;
            res->end = sz64;
        } else {
            res->start = l64;
            res->end = l64 + sz64;
        dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
        }
    } else {
        sz = pci_size(l, sz, mask);
 
        if (!sz)
            goto fail;
 
        res->start = l;
        res->end = l + sz;
 
        dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
    }
 
 out:
    return (type == pci_bar_mem64) ? 1 : 0;
 fail:
    res->flags = 0;
    goto out;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    unsigned int pos, reg;
 
    for (pos = 0; pos < howmany; pos++) {
        struct resource *res = &dev->resource[pos];
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
    }
 
    if (rom) {
        struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
        dev->rom_base_reg = rom;
        res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
                IORESOURCE_SIZEALIGN;
        __pci_read_base(dev, pci_bar_mem32, res, rom);
    }
}
 
#if 0
 
void pci_read_bridge_bases(struct pci_bus *child)
{
    struct pci_dev *dev = child->self;
    struct resource *res;
    int i;
 
    if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
        return;
 
    dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
         child->secondary, child->subordinate,
         dev->transparent ? " (subtractive decode)" : "");
 
    pci_bus_remove_resources(child);
    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
        child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 
    pci_read_bridge_io(child);
    pci_read_bridge_mmio(child);
    pci_read_bridge_mmio_pref(child);
 
    if (dev->transparent) {
        pci_bus_for_each_resource(child->parent, res, i) {
            if (res) {
                pci_bus_add_resource(child, res,
                             PCI_SUBTRACTIVE_DECODE);
                dbgprintf("  bridge window %pR (subtractive decode)\n", res);
            }
        }
    }
}
 
#endif
 
static struct pci_bus * pci_alloc_bus(void)
{
    struct pci_bus *b;
 
    b = kzalloc(sizeof(*b), GFP_KERNEL);
    if (b) {
        INIT_LIST_HEAD(&b->node);
        INIT_LIST_HEAD(&b->children);
        INIT_LIST_HEAD(&b->devices);
        INIT_LIST_HEAD(&b->slots);
        INIT_LIST_HEAD(&b->resources);
//        b->max_bus_speed = PCI_SPEED_UNKNOWN;
//        b->cur_bus_speed = PCI_SPEED_UNKNOWN;
    }
    return b;
}
 
 
#if 0
 
static unsigned char pcix_bus_speed[] = {
    PCI_SPEED_UNKNOWN,      /* 0 */
    PCI_SPEED_66MHz_PCIX,       /* 1 */
    PCI_SPEED_100MHz_PCIX,      /* 2 */
    PCI_SPEED_133MHz_PCIX,      /* 3 */
    PCI_SPEED_UNKNOWN,      /* 4 */
    PCI_SPEED_66MHz_PCIX_ECC,   /* 5 */
    PCI_SPEED_100MHz_PCIX_ECC,  /* 6 */
    PCI_SPEED_133MHz_PCIX_ECC,  /* 7 */
    PCI_SPEED_UNKNOWN,      /* 8 */
    PCI_SPEED_66MHz_PCIX_266,   /* 9 */
    PCI_SPEED_100MHz_PCIX_266,  /* A */
    PCI_SPEED_133MHz_PCIX_266,  /* B */
    PCI_SPEED_UNKNOWN,      /* C */
    PCI_SPEED_66MHz_PCIX_533,   /* D */
    PCI_SPEED_100MHz_PCIX_533,  /* E */
    PCI_SPEED_133MHz_PCIX_533   /* F */
};
 
static unsigned char pcie_link_speed[] = {
    PCI_SPEED_UNKNOWN,      /* 0 */
    PCIE_SPEED_2_5GT,       /* 1 */
    PCIE_SPEED_5_0GT,       /* 2 */
    PCIE_SPEED_8_0GT,       /* 3 */
    PCI_SPEED_UNKNOWN,      /* 4 */
    PCI_SPEED_UNKNOWN,      /* 5 */
    PCI_SPEED_UNKNOWN,      /* 6 */
    PCI_SPEED_UNKNOWN,      /* 7 */
    PCI_SPEED_UNKNOWN,      /* 8 */
    PCI_SPEED_UNKNOWN,      /* 9 */
    PCI_SPEED_UNKNOWN,      /* A */
    PCI_SPEED_UNKNOWN,      /* B */
    PCI_SPEED_UNKNOWN,      /* C */
    PCI_SPEED_UNKNOWN,      /* D */
    PCI_SPEED_UNKNOWN,      /* E */
    PCI_SPEED_UNKNOWN       /* F */
};
 
 
static void pci_set_bus_speed(struct pci_bus *bus)
{
    struct pci_dev *bridge = bus->self;
    int pos;
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
    if (!pos)
        pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
    if (pos) {
        u32 agpstat, agpcmd;
 
        pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
        bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
 
        pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
        bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
    }
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
    if (pos) {
        u16 status;
        enum pci_bus_speed max;
        pci_read_config_word(bridge, pos + 2, &status);
 
        if (status & 0x8000) {
            max = PCI_SPEED_133MHz_PCIX_533;
        } else if (status & 0x4000) {
            max = PCI_SPEED_133MHz_PCIX_266;
        } else if (status & 0x0002) {
            if (((status >> 12) & 0x3) == 2) {
                max = PCI_SPEED_133MHz_PCIX_ECC;
            } else {
                max = PCI_SPEED_133MHz_PCIX;
            }
        } else {
            max = PCI_SPEED_66MHz_PCIX;
        }
 
        bus->max_bus_speed = max;
        bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
 
        return;
    }
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
    if (pos) {
        u32 linkcap;
        u16 linksta;
 
        pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
        bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
 
        pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
        pcie_update_link_speed(bus, linksta);
    }
}
 
#endif
 
 
static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
                       struct pci_dev *bridge, int busnr)
{
    struct pci_bus *child;
    int i;
 
    /*
     * Allocate a new bus, and inherit stuff from the parent..
     */
    child = pci_alloc_bus();
    if (!child)
        return NULL;
 
    child->parent = parent;
    child->ops = parent->ops;
    child->sysdata = parent->sysdata;
    child->bus_flags = parent->bus_flags;
 
    /* initialize some portions of the bus device, but don't register it
     * now as the parent is not properly set up yet.  This device will get
     * registered later in pci_bus_add_devices()
     */
//    child->dev.class = &pcibus_class;
//    dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 
    /*
     * Set up the primary, secondary and subordinate
     * bus numbers.
     */
    child->number = child->secondary = busnr;
    child->primary = parent->secondary;
    child->subordinate = 0xff;
 
    if (!bridge)
        return child;
 
    child->self = bridge;
//    child->bridge = get_device(&bridge->dev);
 
//    pci_set_bus_speed(child);
 
    /* Set up default resource pointers and names.. */
    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
        child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
        child->resource[i]->name = child->name;
    }
    bridge->subordinate = child;
 
    return child;
}
 
struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
{
    struct pci_bus *child;
 
    child = pci_alloc_child_bus(parent, dev, busnr);
    if (child) {
//        down_write(&pci_bus_sem);
        list_add_tail(&child->node, &parent->children);
//        up_write(&pci_bus_sem);
    }
    return child;
}
 
 
static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
{
    struct pci_bus *parent = child->parent;
 
    /* Attempts to fix that up are really dangerous unless
       we're going to re-assign all bus numbers. */
    if (!pcibios_assign_all_busses())
        return;
 
    while (parent->parent && parent->subordinate < max) {
        parent->subordinate = max;
        pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
        parent = parent->parent;
    }
}
 
 
/*
 * If it's a bridge, configure it and scan the bus behind it.
 * For CardBus bridges, we don't scan behind as the devices will
 * be handled by the bridge driver itself.
 *
 * We need to process bridges in two passes -- first we scan those
 * already configured by the BIOS and after we are done with all of
 * them, we proceed to assigning numbers to the remaining buses in
 * order to avoid overlaps between old and new bus numbers.
 */
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
{
    struct pci_bus *child;
    int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
    u32 buses, i, j = 0;
    u16 bctl;
    u8 primary, secondary, subordinate;
    int broken = 0;
 
    pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
    primary = buses & 0xFF;
    secondary = (buses >> 8) & 0xFF;
    subordinate = (buses >> 16) & 0xFF;
 
    dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
        secondary, subordinate, pass);
 
    /* Check if setup is sensible at all */
    if (!pass &&
        (primary != bus->number || secondary <= bus->number)) {
        dbgprintf("bus configuration invalid, reconfiguring\n");
        broken = 1;
    }
 
    /* Disable MasterAbortMode during probing to avoid reporting
       of bus errors (in some architectures) */
    pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
    pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                  bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 
    if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
        !is_cardbus && !broken) {
        unsigned int cmax;
        /*
         * Bus already configured by firmware, process it in the first
         * pass and just note the configuration.
         */
        if (pass)
            goto out;
 
        /*
         * If we already got to this bus through a different bridge,
         * don't re-add it. This can happen with the i450NX chipset.
         *
         * However, we continue to descend down the hierarchy and
         * scan remaining child buses.
         */
        child = pci_find_bus(pci_domain_nr(bus), secondary);
        if (!child) {
            child = pci_add_new_bus(bus, dev, secondary);
            if (!child)
                goto out;
            child->primary = primary;
            child->subordinate = subordinate;
            child->bridge_ctl = bctl;
        }
 
        cmax = pci_scan_child_bus(child);
        if (cmax > max)
            max = cmax;
        if (child->subordinate > max)
            max = child->subordinate;
    } else {
        /*
         * We need to assign a number to this bus which we always
         * do in the second pass.
         */
        if (!pass) {
            if (pcibios_assign_all_busses() || broken)
                /* Temporarily disable forwarding of the
                   configuration cycles on all bridges in
                   this bus segment to avoid possible
                   conflicts in the second pass between two
                   bridges programmed with overlapping
                   bus ranges. */
                pci_write_config_dword(dev, PCI_PRIMARY_BUS,
                               buses & ~0xffffff);
            goto out;
        }
 
        /* Clear errors */
        pci_write_config_word(dev, PCI_STATUS, 0xffff);
 
        /* Prevent assigning a bus number that already exists.
         * This can happen when a bridge is hot-plugged */
        if (pci_find_bus(pci_domain_nr(bus), max+1))
            goto out;
        child = pci_add_new_bus(bus, dev, ++max);
        buses = (buses & 0xff000000)
              | ((unsigned int)(child->primary)     <<  0)
              | ((unsigned int)(child->secondary)   <<  8)
              | ((unsigned int)(child->subordinate) << 16);
 
        /*
         * yenta.c forces a secondary latency timer of 176.
         * Copy that behaviour here.
         */
        if (is_cardbus) {
            buses &= ~0xff000000;
            buses |= CARDBUS_LATENCY_TIMER << 24;
        }
 
        /*
         * We need to blast all three values with a single write.
         */
        pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
        if (!is_cardbus) {
            child->bridge_ctl = bctl;
            /*
             * Adjust subordinate busnr in parent buses.
             * We do this before scanning for children because
             * some devices may not be detected if the bios
             * was lazy.
             */
            pci_fixup_parent_subordinate_busnr(child, max);
            /* Now we can scan all subordinate buses... */
            max = pci_scan_child_bus(child);
            /*
             * now fix it up again since we have found
             * the real value of max.
             */
            pci_fixup_parent_subordinate_busnr(child, max);
        } else {
            /*
             * For CardBus bridges, we leave 4 bus numbers
             * as cards with a PCI-to-PCI bridge can be
             * inserted later.
             */
            for (i=0; i
                struct pci_bus *parent = bus;
                if (pci_find_bus(pci_domain_nr(bus),
                            max+i+1))
                    break;
                while (parent->parent) {
                    if ((!pcibios_assign_all_busses()) &&
                        (parent->subordinate > max) &&
                        (parent->subordinate <= max+i)) {
                        j = 1;
                    }
                    parent = parent->parent;
                }
                if (j) {
                    /*
                     * Often, there are two cardbus bridges
                     * -- try to leave one valid bus number
                     * for each one.
                     */
                    i /= 2;
                    break;
                }
            }
            max += i;
            pci_fixup_parent_subordinate_busnr(child, max);
        }
        /*
         * Set the subordinate bus number to its real value.
         */
        child->subordinate = max;
        pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
    }
 
    vsprintf(child->name,
        (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
        pci_domain_nr(bus), child->number);
 
    /* Has only triggered on CardBus, fixup is in yenta_socket */
    while (bus->parent) {
        if ((child->subordinate > bus->subordinate) ||
            (child->number > bus->subordinate) ||
            (child->number < bus->number) ||
            (child->subordinate < bus->number)) {
            dbgprintf("[bus %02x-%02x] %s "
                "hidden behind%s bridge %s [bus %02x-%02x]\n",
                child->number, child->subordinate,
                (bus->number > child->subordinate &&
                 bus->subordinate < child->number) ?
                    "wholly" : "partially",
                bus->self->transparent ? " transparent" : "",
                "FIX BRIDGE NAME",
                bus->number, bus->subordinate);
        }
        bus = bus->parent;
    }
 
out:
    pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 
    return max;
}
 
void set_pcie_port_type(struct pci_dev *pdev)
{
    int pos;
    u16 reg16;
 
    pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
    if (!pos)
        return;
    pdev->is_pcie = 1;
    pdev->pcie_cap = pos;
    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
    pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
}
 
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
{
    int pos;
    u16 reg16;
    u32 reg32;
 
    pos = pci_pcie_cap(pdev);
    if (!pos)
        return;
    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
    if (!(reg16 & PCI_EXP_FLAGS_SLOT))
        return;
    pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
    if (reg32 & PCI_EXP_SLTCAP_HPC)
        pdev->is_hotplug_bridge = 1;
}
 
/*
 * Read interrupt line and base address registers.
 * The architecture-dependent code can tweak these, of course.
 */
static void pci_read_irq(struct pci_dev *dev)
{
    unsigned char irq;
 
    pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
    dev->pin = irq;
    if (irq)
        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
    dev->irq = irq;
}
 
 
/**
 * pci_setup_device - fill in class and map information of a device
 * @dev: the device structure to fill
 *
 * Initialize the device structure with information about the device's
 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 * Called at initialisation of the PCI subsystem and by CardBus services.
 * Returns 0 on success and negative if unknown type of device (not normal,
 * bridge or CardBus).
 */
int pci_setup_device(struct pci_dev *dev)
{
    u32 class;
    u8 hdr_type;
    struct pci_slot *slot;
    int pos = 0;
 
    if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
        return -EIO;
 
    dev->sysdata = dev->bus->sysdata;
//    dev->dev.parent = dev->bus->bridge;
//    dev->dev.bus = &pci_bus_type;
    dev->hdr_type = hdr_type & 0x7f;
    dev->multifunction = !!(hdr_type & 0x80);
    dev->error_state = pci_channel_io_normal;
    set_pcie_port_type(dev);
 
    list_for_each_entry(slot, &dev->bus->slots, list)
        if (PCI_SLOT(dev->devfn) == slot->number)
            dev->slot = slot;
 
    /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
       set this higher, assuming the system even supports it.  */
    dev->dma_mask = 0xffffffff;
 
//    dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
//             dev->bus->number, PCI_SLOT(dev->devfn),
//             PCI_FUNC(dev->devfn));
 
    pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
    dev->revision = class & 0xff;
    class >>= 8;                    /* upper 3 bytes */
    dev->class = class;
    class >>= 8;
 
    dbgprintf("found [%04x:%04x] class %06x header type %02x\n",
         dev->vendor, dev->device, class, dev->hdr_type);
 
    /* need to have dev->class ready */
    dev->cfg_size = pci_cfg_space_size(dev);
 
    /* "Unknown power state" */
    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
//    pci_fixup_device(pci_fixup_early, dev);
    /* device class may be changed after fixup */
    class = dev->class >> 8;
 
    switch (dev->hdr_type) {            /* header type */
    case PCI_HEADER_TYPE_NORMAL:            /* standard header */
        if (class == PCI_CLASS_BRIDGE_PCI)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
        pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 
        /*
         *  Do the ugly legacy mode stuff here rather than broken chip
         *  quirk code. Legacy mode ATA controllers have fixed
         *  addresses. These are not always echoed in BAR0-3, and
         *  BAR0-3 in a few cases contain junk!
         */
        if (class == PCI_CLASS_STORAGE_IDE) {
            u8 progif;
            pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
            if ((progif & 1) == 0) {
                dev->resource[0].start = 0x1F0;
                dev->resource[0].end = 0x1F7;
                dev->resource[0].flags = LEGACY_IO_RESOURCE;
                dev->resource[1].start = 0x3F6;
                dev->resource[1].end = 0x3F6;
                dev->resource[1].flags = LEGACY_IO_RESOURCE;
            }
            if ((progif & 4) == 0) {
                dev->resource[2].start = 0x170;
                dev->resource[2].end = 0x177;
                dev->resource[2].flags = LEGACY_IO_RESOURCE;
                dev->resource[3].start = 0x376;
                dev->resource[3].end = 0x376;
                dev->resource[3].flags = LEGACY_IO_RESOURCE;
            }
        }
        break;
 
    case PCI_HEADER_TYPE_BRIDGE:            /* bridge header */
        if (class != PCI_CLASS_BRIDGE_PCI)
            goto bad;
        /* The PCI-to-PCI bridge spec requires that subtractive
           decoding (i.e. transparent) bridge must have programming
           interface code of 0x01. */
        pci_read_irq(dev);
        dev->transparent = ((dev->class & 0xff) == 1);
        pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
        set_pcie_hotplug_bridge(dev);
        pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
        if (pos) {
            pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
            pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
        }
        break;
 
    case PCI_HEADER_TYPE_CARDBUS:           /* CardBus bridge header */
        if (class != PCI_CLASS_BRIDGE_CARDBUS)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 1, 0);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
        break;
 
    default:                    /* unknown header */
        dbgprintf("unknown header type %02x, "
            "ignoring device\n", dev->hdr_type);
        return -EIO;
 
    bad:
        dbgprintf("ignoring class %02x (doesn't match header "
            "type %02x)\n", class, dev->hdr_type);
        dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
    return 0;
}
 
 
 
struct pci_dev *alloc_pci_dev(void)
{
    struct pci_dev *dev;
 
    dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
    if (!dev)
        return NULL;
 
    INIT_LIST_HEAD(&dev->bus_list);
 
    return dev;
}
 
/*
 * Read the config data for a PCI device, sanity-check it
 * and fill in the dev structure...
 */
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;
    u32 l;
    int timeout = 10;
 
    if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
        return NULL;
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (l == 0xffffffff || l == 0x00000000 ||
        l == 0x0000ffff || l == 0xffff0000)
        return NULL;
 
    /* Configuration request Retry Status */
    while (l == 0xffff0001) {
        delay(timeout/10);
        timeout *= 2;
        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
            return NULL;
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 1000) {
            printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
                    "responding\n", pci_domain_nr(bus),
                    bus->number, PCI_SLOT(devfn),
                    PCI_FUNC(devfn));
            return NULL;
        }
    }
 
    dev = alloc_pci_dev();
    if (!dev)
        return NULL;
 
    dev->bus = bus;
    dev->busnr = bus->number;
    dev->devfn = devfn;
    dev->vendor = l & 0xffff;
    dev->device = (l >> 16) & 0xffff;
 
    if (pci_setup_device(dev)) {
        kfree(dev);
        return NULL;
    }
 
    return dev;
}
 
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
{
//    device_initialize(&dev->dev);
//    dev->dev.release = pci_release_dev;
//    pci_dev_get(dev);
 
//    dev->dev.dma_mask = &dev->dma_mask;
//    dev->dev.dma_parms = &dev->dma_parms;
//    dev->dev.coherent_dma_mask = 0xffffffffull;
 
//    pci_set_dma_max_seg_size(dev, 65536);
//    pci_set_dma_seg_boundary(dev, 0xffffffff);
 
    /* Fix up broken headers */
//    pci_fixup_device(pci_fixup_header, dev);
 
    /* Clear the state_saved flag. */
    dev->state_saved = false;
 
    /* Initialize various capabilities */
//    pci_init_capabilities(dev);
 
    /*
     * Add the device to our list of discovered devices
     * and the bus list for fixup functions, etc.
     */
//    down_write(&pci_bus_sem);
    list_add_tail(&dev->bus_list, &bus->devices);
//    up_write(&pci_bus_sem);
}
 
struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;
 
    dev = pci_get_slot(bus, devfn);
    if (dev) {
//        pci_dev_put(dev);
        return dev;
    }
 
    dev = pci_scan_device(bus, devfn);
    if (!dev)
        return NULL;
 
    pci_device_add(dev, bus);
 
    return dev;
}
 
static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
{
    u16 cap;
    unsigned pos, next_fn;
 
    if (!dev)
        return 0;
 
    pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
    if (!pos)
        return 0;
    pci_read_config_word(dev, pos + 4, &cap);
    next_fn = cap >> 8;
    if (next_fn <= fn)
        return 0;
    return next_fn;
}
 
static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
{
    return (fn + 1) % 8;
}
 
static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
{
    return 0;
}
 
static int only_one_child(struct pci_bus *bus)
{
    struct pci_dev *parent = bus->self;
    if (!parent || !pci_is_pcie(parent))
        return 0;
    if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
        parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
        return 1;
    return 0;
}
 
/**
 * pci_scan_slot - scan a PCI slot on a bus for devices.
 * @bus: PCI bus to scan
 * @devfn: slot number to scan (must have zero function.)
 *
 * Scan a PCI slot on the specified PCI bus for devices, adding
 * discovered devices to the @bus->devices list.  New devices
 * will not have is_added set.
 *
 * Returns the number of new devices found.
 */
int pci_scan_slot(struct pci_bus *bus, int devfn)
{
    unsigned fn, nr = 0;
    struct pci_dev *dev;
    unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
 
    if (only_one_child(bus) && (devfn > 0))
        return 0; /* Already scanned the entire slot */
 
    dev = pci_scan_single_device(bus, devfn);
    if (!dev)
        return 0;
    if (!dev->is_added)
        nr++;
 
    if (pci_ari_enabled(bus))
        next_fn = next_ari_fn;
    else if (dev->multifunction)
        next_fn = next_trad_fn;
 
    for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
        dev = pci_scan_single_device(bus, devfn + fn);
        if (dev) {
            if (!dev->is_added)
                nr++;
            dev->multifunction = 1;
        }
    }
 
    /* only one slot has pcie device */
//    if (bus->self && nr)
//        pcie_aspm_init_link_state(bus->self);
 
    return nr;
}
 
 
unsigned int pci_scan_child_bus(struct pci_bus *bus)
{
    unsigned int devfn, pass, max = bus->secondary;
    struct pci_dev *dev;
 
    dbgprintf("scanning bus\n");
 
    /* Go find them, Rover! */
    for (devfn = 0; devfn < 0x100; devfn += 8)
        pci_scan_slot(bus, devfn);
 
    /* Reserve buses for SR-IOV capability. */
    max += pci_iov_bus_range(bus);
 
    /*
     * After performing arch-dependent fixup of the bus, look behind
     * all PCI-to-PCI bridges on this bus.
     */
    if (!bus->is_added) {
        dbgprintf("fixups for bus\n");
//        pcibios_fixup_bus(bus);
        if (pci_is_root_bus(bus))
            bus->is_added = 1;
    }
 
    for (pass=0; pass < 2; pass++)
        list_for_each_entry(dev, &bus->devices, bus_list) {
            if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
                dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
                max = pci_scan_bridge(bus, dev, max, pass);
        }
 
    /*
     * We've scanned the bus and so we know all about what's on
     * the other side of any bridges that may be on this bus plus
     * any devices.
     *
     * Return how far we've got finding sub-buses.
     */
    dbgprintf("bus scan returning with max=%02x\n", max);
    return max;
}
 
/**
 * pci_cfg_space_size - get the configuration space size of the PCI device.
 * @dev: PCI device
 *
 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 * access it.  Maybe we don't have a way to generate extended config space
 * accesses, or the device is behind a reverse Express bridge.  So we try
 * reading the dword at 0x100 which must either be 0 or a valid extended
 * capability header.
 */
int pci_cfg_space_size_ext(struct pci_dev *dev)
{
    u32 status;
    int pos = PCI_CFG_SPACE_SIZE;
 
    if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
        goto fail;
    if (status == 0xffffffff)
        goto fail;
 
    return PCI_CFG_SPACE_EXP_SIZE;
 
 fail:
    return PCI_CFG_SPACE_SIZE;
}
 
int pci_cfg_space_size(struct pci_dev *dev)
{
    int pos;
    u32 status;
    u16 class;
 
    class = dev->class >> 8;
    if (class == PCI_CLASS_BRIDGE_HOST)
        return pci_cfg_space_size_ext(dev);
 
    pos = pci_pcie_cap(dev);
    if (!pos) {
        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
        if (!pos)
            goto fail;
 
        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
            goto fail;
    }
 
    return pci_cfg_space_size_ext(dev);
 
 fail:
    return PCI_CFG_SPACE_SIZE;
}
 
 
 
struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata)
{
    int error;
    struct pci_bus *b, *b2;
 
    b = pci_alloc_bus();
    if (!b)
        return NULL;
 
    b->sysdata = sysdata;
    b->ops = ops;
 
    b2 = pci_find_bus(pci_domain_nr(b), bus);
    if (b2) {
        /* If we already got to this bus through a different bridge, ignore it */
        dbgprintf("bus already known\n");
        goto err_out;
    }
 
//    down_write(&pci_bus_sem);
    list_add_tail(&b->node, &pci_root_buses);
//    up_write(&pci_bus_sem);
 
    b->number = b->secondary = bus;
    b->resource[0] = &ioport_resource;
    b->resource[1] = &iomem_resource;
 
    return b;
 
err_out:
    kfree(b);
    return NULL;
}

Rev 1633	Rev 1867
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4	#include	4	#include
5	#include	5	#include
6		6
7	LIST_HEAD(pci_root_buses);	7	LIST_HEAD(pci_root_buses);
8		8
9	#define IO_SPACE_LIMIT 0xffff	9	#define IO_SPACE_LIMIT 0xffff
10		10
11		11
12		12
13		13
14	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	14	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
15		15
16	#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */	16	#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17	#define CARDBUS_RESERVE_BUSNR 3	17	#define CARDBUS_RESERVE_BUSNR 3
18		18
19	static int pcibios_assign_all_busses(void)	19	static int pcibios_assign_all_busses(void)
20	{	20	{
21	return 0;	21	return 0;
22	};	22	};
23		23
24	/**	24	/**
25	* pci_ari_enabled - query ARI forwarding status	25	* pci_ari_enabled - query ARI forwarding status
26	* @bus: the PCI bus	26	* @bus: the PCI bus
27	*	27	*
28	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;	28	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
29	*/	29	*/
30	static inline int pci_ari_enabled(struct pci_bus *bus)	30	static inline int pci_ari_enabled(struct pci_bus *bus)
31	{	31	{
32	return bus->self && bus->self->ari_enabled;	32	return bus->self && bus->self->ari_enabled;
33	}	33	}
34		34
35	/*	35	/*
36	* Translate the low bits of the PCI base	36	* Translate the low bits of the PCI base
37	* to the resource type	37	* to the resource type
38	*/	38	*/
39	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	39	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
40	{	40	{
41	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	41	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
42	return IORESOURCE_IO;	42	return IORESOURCE_IO;
43		43
44	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	44	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
45	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	45	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
46		46
47	return IORESOURCE_MEM;	47	return IORESOURCE_MEM;
48	}	48	}
49		49
50	static u64 pci_size(u64 base, u64 maxbase, u64 mask)	50	static u64 pci_size(u64 base, u64 maxbase, u64 mask)
51	{	51	{
52	u64 size = mask & maxbase; /* Find the significant bits */	52	u64 size = mask & maxbase; /* Find the significant bits */
53	if (!size)	53	if (!size)
54	return 0;	54	return 0;
55		55
56	/* Get the lowest of them to find the decode size, and	56	/* Get the lowest of them to find the decode size, and
57	from that the extent. */	57	from that the extent. */
58	size = (size & ~(size-1)) - 1;	58	size = (size & ~(size-1)) - 1;
59		59
60	/* base == maxbase can be valid only if the BAR has	60	/* base == maxbase can be valid only if the BAR has
61	already been programmed with all 1s. */	61	already been programmed with all 1s. */
62	if (base == maxbase && ((base \| size) & mask) != mask)	62	if (base == maxbase && ((base \| size) & mask) != mask)
63	return 0;	63	return 0;
64		64
65	return size;	65	return size;
66	}	66	}
67		67
68	static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)	68	static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
69	{	69	{
70	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {	70	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
71	res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;	71	res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
72	return pci_bar_io;	72	return pci_bar_io;
73	}	73	}
74		74
75	res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;	75	res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
76		76
77	if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)	77	if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
78	return pci_bar_mem64;	78	return pci_bar_mem64;
79	return pci_bar_mem32;	79	return pci_bar_mem32;
80	}	80	}
81		81
82		82
83		83
84	/**	84	/**
85	* pci_read_base - read a PCI BAR	85	* pci_read_base - read a PCI BAR
86	* @dev: the PCI device	86	* @dev: the PCI device
87	* @type: type of the BAR	87	* @type: type of the BAR
88	* @res: resource buffer to be filled in	88	* @res: resource buffer to be filled in
89	* @pos: BAR position in the config space	89	* @pos: BAR position in the config space
90	*	90	*
91	* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.	91	* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
92	*/	92	*/
93	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,	93	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
94	struct resource *res, unsigned int pos)	94	struct resource *res, unsigned int pos)
95	{	95	{
96	u32 l, sz, mask;	96	u32 l, sz, mask;
97	u16 orig_cmd;	97	u16 orig_cmd;
98		98
99	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;	99	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
100		100
101	if (!dev->mmio_always_on) {	101	if (!dev->mmio_always_on) {
102	pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);	102	pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
103	pci_write_config_word(dev, PCI_COMMAND,	103	pci_write_config_word(dev, PCI_COMMAND,
104	orig_cmd & ~(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO));	104	orig_cmd & ~(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO));
105	}	105	}
106		106
107	res->name = pci_name(dev);	107	res->name = pci_name(dev);
108		108
109	pci_read_config_dword(dev, pos, &l);	109	pci_read_config_dword(dev, pos, &l);
110	pci_write_config_dword(dev, pos, l \| mask);	110	pci_write_config_dword(dev, pos, l \| mask);
111	pci_read_config_dword(dev, pos, &sz);	111	pci_read_config_dword(dev, pos, &sz);
112	pci_write_config_dword(dev, pos, l);	112	pci_write_config_dword(dev, pos, l);
113		113
114	if (!dev->mmio_always_on)	114	if (!dev->mmio_always_on)
115	pci_write_config_word(dev, PCI_COMMAND, orig_cmd);	115	pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
116		116
117	/*	117	/*
118	* All bits set in sz means the device isn't working properly.	118	* All bits set in sz means the device isn't working properly.
119	* If the BAR isn't implemented, all bits must be 0. If it's a	119	* If the BAR isn't implemented, all bits must be 0. If it's a
120	* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit	120	* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
121	* 1 must be clear.	121	* 1 must be clear.
122	*/	122	*/
123	if (!sz \|\| sz == 0xffffffff)	123	if (!sz \|\| sz == 0xffffffff)
124	goto fail;	124	goto fail;
125		125
126	/*	126	/*
127	* I don't know how l can have all bits set. Copied from old code.	127	* I don't know how l can have all bits set. Copied from old code.
128	* Maybe it fixes a bug on some ancient platform.	128	* Maybe it fixes a bug on some ancient platform.
129	*/	129	*/
130	if (l == 0xffffffff)	130	if (l == 0xffffffff)
131	l = 0;	131	l = 0;
132		132
133	if (type == pci_bar_unknown) {	133	if (type == pci_bar_unknown) {
134	type = decode_bar(res, l);	134	type = decode_bar(res, l);
135	res->flags \|= pci_calc_resource_flags(l) \| IORESOURCE_SIZEALIGN;	135	res->flags \|= pci_calc_resource_flags(l) \| IORESOURCE_SIZEALIGN;
136	if (type == pci_bar_io) {	136	if (type == pci_bar_io) {
137	l &= PCI_BASE_ADDRESS_IO_MASK;	137	l &= PCI_BASE_ADDRESS_IO_MASK;
138	mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;	138	mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
139	} else {	139	} else {
140	l &= PCI_BASE_ADDRESS_MEM_MASK;	140	l &= PCI_BASE_ADDRESS_MEM_MASK;
141	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;	141	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
142	}	142	}
143	} else {	143	} else {
144	res->flags \|= (l & IORESOURCE_ROM_ENABLE);	144	res->flags \|= (l & IORESOURCE_ROM_ENABLE);
145	l &= PCI_ROM_ADDRESS_MASK;	145	l &= PCI_ROM_ADDRESS_MASK;
146	mask = (u32)PCI_ROM_ADDRESS_MASK;	146	mask = (u32)PCI_ROM_ADDRESS_MASK;
147	}	147	}
148		148
149	if (type == pci_bar_mem64) {	149	if (type == pci_bar_mem64) {
150	u64 l64 = l;	150	u64 l64 = l;
151	u64 sz64 = sz;	151	u64 sz64 = sz;
152	u64 mask64 = mask \| (u64)~0 << 32;	152	u64 mask64 = mask \| (u64)~0 << 32;
153		153
154	pci_read_config_dword(dev, pos + 4, &l);	154	pci_read_config_dword(dev, pos + 4, &l);
155	pci_write_config_dword(dev, pos + 4, ~0);	155	pci_write_config_dword(dev, pos + 4, ~0);
156	pci_read_config_dword(dev, pos + 4, &sz);	156	pci_read_config_dword(dev, pos + 4, &sz);
157	pci_write_config_dword(dev, pos + 4, l);	157	pci_write_config_dword(dev, pos + 4, l);
158		158
159	l64 \|= ((u64)l << 32);	159	l64 \|= ((u64)l << 32);
160	sz64 \|= ((u64)sz << 32);	160	sz64 \|= ((u64)sz << 32);
161		161
162	sz64 = pci_size(l64, sz64, mask64);	162	sz64 = pci_size(l64, sz64, mask64);
163		163
164	if (!sz64)	164	if (!sz64)
165	goto fail;	165	goto fail;
166		166
167	if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {	167	if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
168	dbgprintf("%s reg %x: can't handle 64-bit BAR\n",	168	dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
169	__FUNCTION__, pos);	169	__FUNCTION__, pos);
170	goto fail;	170	goto fail;
171	}	171	}
172		172
173	res->flags \|= IORESOURCE_MEM_64;	173	res->flags \|= IORESOURCE_MEM_64;
174	if ((sizeof(resource_size_t) < 8) && l) {	174	if ((sizeof(resource_size_t) < 8) && l) {
175	/* Address above 32-bit boundary; disable the BAR */	175	/* Address above 32-bit boundary; disable the BAR */
176	pci_write_config_dword(dev, pos, 0);	176	pci_write_config_dword(dev, pos, 0);
177	pci_write_config_dword(dev, pos + 4, 0);	177	pci_write_config_dword(dev, pos + 4, 0);
178	res->start = 0;	178	res->start = 0;
179	res->end = sz64;	179	res->end = sz64;
180	} else {	180	} else {
181	res->start = l64;	181	res->start = l64;
182	res->end = l64 + sz64;	182	res->end = l64 + sz64;
183	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);	183	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
184	}	184	}
185	} else {	185	} else {
186	sz = pci_size(l, sz, mask);	186	sz = pci_size(l, sz, mask);
187		187
188	if (!sz)	188	if (!sz)
189	goto fail;	189	goto fail;
190		190
191	res->start = l;	191	res->start = l;
192	res->end = l + sz;	192	res->end = l + sz;
193		193
194	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);	194	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
195	}	195	}
196		196
197	out:	197	out:
198	return (type == pci_bar_mem64) ? 1 : 0;	198	return (type == pci_bar_mem64) ? 1 : 0;
199	fail:	199	fail:
200	res->flags = 0;	200	res->flags = 0;
201	goto out;	201	goto out;
202	}	202	}
203		203
204	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	204	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
205	{	205	{
206	unsigned int pos, reg;	206	unsigned int pos, reg;
207		207
208	for (pos = 0; pos < howmany; pos++) {	208	for (pos = 0; pos < howmany; pos++) {
209	struct resource *res = &dev->resource[pos];	209	struct resource *res = &dev->resource[pos];
210	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	210	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
211	pos += __pci_read_base(dev, pci_bar_unknown, res, reg);	211	pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
212	}	212	}
213		213
214	if (rom) {	214	if (rom) {
215	struct resource *res = &dev->resource[PCI_ROM_RESOURCE];	215	struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
216	dev->rom_base_reg = rom;	216	dev->rom_base_reg = rom;
217	res->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	217	res->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
218	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE \|	218	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE \|
219	IORESOURCE_SIZEALIGN;	219	IORESOURCE_SIZEALIGN;
220	__pci_read_base(dev, pci_bar_mem32, res, rom);	220	__pci_read_base(dev, pci_bar_mem32, res, rom);
221	}	221	}
222	}	222	}
223		223
224	#if 0	224	#if 0
225		225
226	void pci_read_bridge_bases(struct pci_bus *child)	226	void pci_read_bridge_bases(struct pci_bus *child)
227	{	227	{
228	struct pci_dev *dev = child->self;	228	struct pci_dev *dev = child->self;
229	struct resource *res;	229	struct resource *res;
230	int i;	230	int i;
231		231
232	if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */	232	if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
233	return;	233	return;
234		234
235	dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",	235	dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
236	child->secondary, child->subordinate,	236	child->secondary, child->subordinate,
237	dev->transparent ? " (subtractive decode)" : "");	237	dev->transparent ? " (subtractive decode)" : "");
238		238
239	pci_bus_remove_resources(child);	239	pci_bus_remove_resources(child);
240	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)	240	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
241	child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];	241	child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
242		242
243	pci_read_bridge_io(child);	243	pci_read_bridge_io(child);
244	pci_read_bridge_mmio(child);	244	pci_read_bridge_mmio(child);
245	pci_read_bridge_mmio_pref(child);	245	pci_read_bridge_mmio_pref(child);
246		246
247	if (dev->transparent) {	247	if (dev->transparent) {
248	pci_bus_for_each_resource(child->parent, res, i) {	248	pci_bus_for_each_resource(child->parent, res, i) {
249	if (res) {	249	if (res) {
250	pci_bus_add_resource(child, res,	250	pci_bus_add_resource(child, res,
251	PCI_SUBTRACTIVE_DECODE);	251	PCI_SUBTRACTIVE_DECODE);
252	dbgprintf(" bridge window %pR (subtractive decode)\n", res);	252	dbgprintf(" bridge window %pR (subtractive decode)\n", res);
253	}	253	}
254	}	254	}
255	}	255	}
256	}	256	}
257		257
258	#endif	258	#endif
259		259
260	static struct pci_bus * pci_alloc_bus(void)	260	static struct pci_bus * pci_alloc_bus(void)
261	{	261	{
262	struct pci_bus *b;	262	struct pci_bus *b;
263		263
264	b = kzalloc(sizeof(*b), GFP_KERNEL);	264	b = kzalloc(sizeof(*b), GFP_KERNEL);
265	if (b) {	265	if (b) {
266	INIT_LIST_HEAD(&b->node);	266	INIT_LIST_HEAD(&b->node);
267	INIT_LIST_HEAD(&b->children);	267	INIT_LIST_HEAD(&b->children);
268	INIT_LIST_HEAD(&b->devices);	268	INIT_LIST_HEAD(&b->devices);
269	INIT_LIST_HEAD(&b->slots);	269	INIT_LIST_HEAD(&b->slots);
270	INIT_LIST_HEAD(&b->resources);	270	INIT_LIST_HEAD(&b->resources);
271	// b->max_bus_speed = PCI_SPEED_UNKNOWN;	271	// b->max_bus_speed = PCI_SPEED_UNKNOWN;
272	// b->cur_bus_speed = PCI_SPEED_UNKNOWN;	272	// b->cur_bus_speed = PCI_SPEED_UNKNOWN;
273	}	273	}
274	return b;	274	return b;
275	}	275	}
276		276
277		277
278	#if 0	278	#if 0
279		279
280	static unsigned char pcix_bus_speed[] = {	280	static unsigned char pcix_bus_speed[] = {
281	PCI_SPEED_UNKNOWN, /* 0 */	281	PCI_SPEED_UNKNOWN, /* 0 */
282	PCI_SPEED_66MHz_PCIX, /* 1 */	282	PCI_SPEED_66MHz_PCIX, /* 1 */
283	PCI_SPEED_100MHz_PCIX, /* 2 */	283	PCI_SPEED_100MHz_PCIX, /* 2 */
284	PCI_SPEED_133MHz_PCIX, /* 3 */	284	PCI_SPEED_133MHz_PCIX, /* 3 */
285	PCI_SPEED_UNKNOWN, /* 4 */	285	PCI_SPEED_UNKNOWN, /* 4 */
286	PCI_SPEED_66MHz_PCIX_ECC, /* 5 */	286	PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
287	PCI_SPEED_100MHz_PCIX_ECC, /* 6 */	287	PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
288	PCI_SPEED_133MHz_PCIX_ECC, /* 7 */	288	PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
289	PCI_SPEED_UNKNOWN, /* 8 */	289	PCI_SPEED_UNKNOWN, /* 8 */
290	PCI_SPEED_66MHz_PCIX_266, /* 9 */	290	PCI_SPEED_66MHz_PCIX_266, /* 9 */
291	PCI_SPEED_100MHz_PCIX_266, /* A */	291	PCI_SPEED_100MHz_PCIX_266, /* A */
292	PCI_SPEED_133MHz_PCIX_266, /* B */	292	PCI_SPEED_133MHz_PCIX_266, /* B */
293	PCI_SPEED_UNKNOWN, /* C */	293	PCI_SPEED_UNKNOWN, /* C */
294	PCI_SPEED_66MHz_PCIX_533, /* D */	294	PCI_SPEED_66MHz_PCIX_533, /* D */
295	PCI_SPEED_100MHz_PCIX_533, /* E */	295	PCI_SPEED_100MHz_PCIX_533, /* E */
296	PCI_SPEED_133MHz_PCIX_533 /* F */	296	PCI_SPEED_133MHz_PCIX_533 /* F */
297	};	297	};
298		298
299	static unsigned char pcie_link_speed[] = {	299	static unsigned char pcie_link_speed[] = {
300	PCI_SPEED_UNKNOWN, /* 0 */	300	PCI_SPEED_UNKNOWN, /* 0 */
301	PCIE_SPEED_2_5GT, /* 1 */	301	PCIE_SPEED_2_5GT, /* 1 */
302	PCIE_SPEED_5_0GT, /* 2 */	302	PCIE_SPEED_5_0GT, /* 2 */
303	PCIE_SPEED_8_0GT, /* 3 */	303	PCIE_SPEED_8_0GT, /* 3 */
304	PCI_SPEED_UNKNOWN, /* 4 */	304	PCI_SPEED_UNKNOWN, /* 4 */
305	PCI_SPEED_UNKNOWN, /* 5 */	305	PCI_SPEED_UNKNOWN, /* 5 */
306	PCI_SPEED_UNKNOWN, /* 6 */	306	PCI_SPEED_UNKNOWN, /* 6 */
307	PCI_SPEED_UNKNOWN, /* 7 */	307	PCI_SPEED_UNKNOWN, /* 7 */
308	PCI_SPEED_UNKNOWN, /* 8 */	308	PCI_SPEED_UNKNOWN, /* 8 */
309	PCI_SPEED_UNKNOWN, /* 9 */	309	PCI_SPEED_UNKNOWN, /* 9 */
310	PCI_SPEED_UNKNOWN, /* A */	310	PCI_SPEED_UNKNOWN, /* A */
311	PCI_SPEED_UNKNOWN, /* B */	311	PCI_SPEED_UNKNOWN, /* B */
312	PCI_SPEED_UNKNOWN, /* C */	312	PCI_SPEED_UNKNOWN, /* C */
313	PCI_SPEED_UNKNOWN, /* D */	313	PCI_SPEED_UNKNOWN, /* D */
314	PCI_SPEED_UNKNOWN, /* E */	314	PCI_SPEED_UNKNOWN, /* E */
315	PCI_SPEED_UNKNOWN /* F */	315	PCI_SPEED_UNKNOWN /* F */
316	};	316	};
317		317
318		318
319	static void pci_set_bus_speed(struct pci_bus *bus)	319	static void pci_set_bus_speed(struct pci_bus *bus)
320	{	320	{
321	struct pci_dev *bridge = bus->self;	321	struct pci_dev *bridge = bus->self;
322	int pos;	322	int pos;
323		323
324	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);	324	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
325	if (!pos)	325	if (!pos)
326	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);	326	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
327	if (pos) {	327	if (pos) {
328	u32 agpstat, agpcmd;	328	u32 agpstat, agpcmd;
329		329
330	pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);	330	pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
331	bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);	331	bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
332		332
333	pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);	333	pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
334	bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);	334	bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
335	}	335	}
336		336
337	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);	337	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
338	if (pos) {	338	if (pos) {
339	u16 status;	339	u16 status;
340	enum pci_bus_speed max;	340	enum pci_bus_speed max;
341	pci_read_config_word(bridge, pos + 2, &status);	341	pci_read_config_word(bridge, pos + 2, &status);
342		342
343	if (status & 0x8000) {	343	if (status & 0x8000) {
344	max = PCI_SPEED_133MHz_PCIX_533;	344	max = PCI_SPEED_133MHz_PCIX_533;
345	} else if (status & 0x4000) {	345	} else if (status & 0x4000) {
346	max = PCI_SPEED_133MHz_PCIX_266;	346	max = PCI_SPEED_133MHz_PCIX_266;
347	} else if (status & 0x0002) {	347	} else if (status & 0x0002) {
348	if (((status >> 12) & 0x3) == 2) {	348	if (((status >> 12) & 0x3) == 2) {
349	max = PCI_SPEED_133MHz_PCIX_ECC;	349	max = PCI_SPEED_133MHz_PCIX_ECC;
350	} else {	350	} else {
351	max = PCI_SPEED_133MHz_PCIX;	351	max = PCI_SPEED_133MHz_PCIX;
352	}	352	}
353	} else {	353	} else {
354	max = PCI_SPEED_66MHz_PCIX;	354	max = PCI_SPEED_66MHz_PCIX;
355	}	355	}
356		356
357	bus->max_bus_speed = max;	357	bus->max_bus_speed = max;
358	bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];	358	bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
359		359
360	return;	360	return;
361	}	361	}
362		362
363	pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);	363	pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
364	if (pos) {	364	if (pos) {
365	u32 linkcap;	365	u32 linkcap;
366	u16 linksta;	366	u16 linksta;
367		367
368	pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);	368	pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
369	bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];	369	bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
370		370
371	pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);	371	pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
372	pcie_update_link_speed(bus, linksta);	372	pcie_update_link_speed(bus, linksta);
373	}	373	}
374	}	374	}
375		375
376	#endif	376	#endif
377		377
378		378
379	static struct pci_bus pci_alloc_child_bus(struct pci_bus parent,	379	static struct pci_bus pci_alloc_child_bus(struct pci_bus parent,
380	struct pci_dev *bridge, int busnr)	380	struct pci_dev *bridge, int busnr)
381	{	381	{
382	struct pci_bus *child;	382	struct pci_bus *child;
383	int i;	383	int i;
384		384
385	/*	385	/*
386	* Allocate a new bus, and inherit stuff from the parent..	386	* Allocate a new bus, and inherit stuff from the parent..
387	*/	387	*/
388	child = pci_alloc_bus();	388	child = pci_alloc_bus();
389	if (!child)	389	if (!child)
390	return NULL;	390	return NULL;
391		391
392	child->parent = parent;	392	child->parent = parent;
393	child->ops = parent->ops;	393	child->ops = parent->ops;
394	child->sysdata = parent->sysdata;	394	child->sysdata = parent->sysdata;
395	child->bus_flags = parent->bus_flags;	395	child->bus_flags = parent->bus_flags;
396		396
397	/* initialize some portions of the bus device, but don't register it	397	/* initialize some portions of the bus device, but don't register it
398	* now as the parent is not properly set up yet. This device will get	398	* now as the parent is not properly set up yet. This device will get
399	* registered later in pci_bus_add_devices()	399	* registered later in pci_bus_add_devices()
400	*/	400	*/
401	// child->dev.class = &pcibus_class;	401	// child->dev.class = &pcibus_class;
402	// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);	402	// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
403		403
404	/*	404	/*
405	* Set up the primary, secondary and subordinate	405	* Set up the primary, secondary and subordinate
406	* bus numbers.	406	* bus numbers.
407	*/	407	*/
408	child->number = child->secondary = busnr;	408	child->number = child->secondary = busnr;
409	child->primary = parent->secondary;	409	child->primary = parent->secondary;
410	child->subordinate = 0xff;	410	child->subordinate = 0xff;
411		411
412	if (!bridge)	412	if (!bridge)
413	return child;	413	return child;
414		414
415	child->self = bridge;	415	child->self = bridge;
416	// child->bridge = get_device(&bridge->dev);	416	// child->bridge = get_device(&bridge->dev);
417		417
418	// pci_set_bus_speed(child);	418	// pci_set_bus_speed(child);
419		419
420	/* Set up default resource pointers and names.. */	420	/* Set up default resource pointers and names.. */
421	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {	421	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
422	child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];	422	child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
423	child->resource[i]->name = child->name;	423	child->resource[i]->name = child->name;
424	}	424	}
425	bridge->subordinate = child;	425	bridge->subordinate = child;
426		426
427	return child;	427	return child;
428	}	428	}
429		429
430	struct pci_bus* pci_add_new_bus(struct pci_bus parent, struct pci_dev dev, int busnr)	430	struct pci_bus* pci_add_new_bus(struct pci_bus parent, struct pci_dev dev, int busnr)
431	{	431	{
432	struct pci_bus *child;	432	struct pci_bus *child;
433		433
434	child = pci_alloc_child_bus(parent, dev, busnr);	434	child = pci_alloc_child_bus(parent, dev, busnr);
435	if (child) {	435	if (child) {
436	// down_write(&pci_bus_sem);	436	// down_write(&pci_bus_sem);
437	list_add_tail(&child->node, &parent->children);	437	list_add_tail(&child->node, &parent->children);
438	// up_write(&pci_bus_sem);	438	// up_write(&pci_bus_sem);
439	}	439	}
440	return child;	440	return child;
441	}	441	}
442		442
443		443
444	static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)	444	static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
445	{	445	{
446	struct pci_bus *parent = child->parent;	446	struct pci_bus *parent = child->parent;
447		447
448	/* Attempts to fix that up are really dangerous unless	448	/* Attempts to fix that up are really dangerous unless
449	we're going to re-assign all bus numbers. */	449	we're going to re-assign all bus numbers. */
450	if (!pcibios_assign_all_busses())	450	if (!pcibios_assign_all_busses())
451	return;	451	return;
452		452
453	while (parent->parent && parent->subordinate < max) {	453	while (parent->parent && parent->subordinate < max) {
454	parent->subordinate = max;	454	parent->subordinate = max;
455	pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);	455	pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
456	parent = parent->parent;	456	parent = parent->parent;
457	}	457	}
458	}	458	}
459		459
460		460
461	/*	461	/*
462	* If it's a bridge, configure it and scan the bus behind it.	462	* If it's a bridge, configure it and scan the bus behind it.
463	* For CardBus bridges, we don't scan behind as the devices will	463	* For CardBus bridges, we don't scan behind as the devices will
464	* be handled by the bridge driver itself.	464	* be handled by the bridge driver itself.
465	*	465	*
466	* We need to process bridges in two passes -- first we scan those	466	* We need to process bridges in two passes -- first we scan those
467	* already configured by the BIOS and after we are done with all of	467	* already configured by the BIOS and after we are done with all of
468	* them, we proceed to assigning numbers to the remaining buses in	468	* them, we proceed to assigning numbers to the remaining buses in
469	* order to avoid overlaps between old and new bus numbers.	469	* order to avoid overlaps between old and new bus numbers.
470	*/	470	*/
471	int pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, int pass)	471	int pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, int pass)
472	{	472	{
473	struct pci_bus *child;	473	struct pci_bus *child;
474	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);	474	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
475	u32 buses, i, j = 0;	475	u32 buses, i, j = 0;
476	u16 bctl;	476	u16 bctl;
477	u8 primary, secondary, subordinate;	477	u8 primary, secondary, subordinate;
478	int broken = 0;	478	int broken = 0;
479		479
480	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);	480	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
481	primary = buses & 0xFF;	481	primary = buses & 0xFF;
482	secondary = (buses >> 8) & 0xFF;	482	secondary = (buses >> 8) & 0xFF;
483	subordinate = (buses >> 16) & 0xFF;	483	subordinate = (buses >> 16) & 0xFF;
484		484
485	dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",	485	dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
486	secondary, subordinate, pass);	486	secondary, subordinate, pass);
487		487
488	/* Check if setup is sensible at all */	488	/* Check if setup is sensible at all */
489	if (!pass &&	489	if (!pass &&
490	(primary != bus->number \|\| secondary <= bus->number)) {	490	(primary != bus->number \|\| secondary <= bus->number)) {
491	dbgprintf("bus configuration invalid, reconfiguring\n");	491	dbgprintf("bus configuration invalid, reconfiguring\n");
492	broken = 1;	492	broken = 1;
493	}	493	}
494		494
495	/* Disable MasterAbortMode during probing to avoid reporting	495	/* Disable MasterAbortMode during probing to avoid reporting
496	of bus errors (in some architectures) */	496	of bus errors (in some architectures) */
497	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);	497	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
498	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,	498	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
499	bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);	499	bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
500		500

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(root)/drivers/devman/pci/probe.c – Rev 1633 → 1867