WebSVN – Kolibri OS – Diff – /drivers/devman/pci/probe.c


#include 
#include 
#include 
#include 
#include 
#include 
 
LIST_HEAD(pci_root_buses);
 
#define IO_SPACE_LIMIT 0xffff
 
 
 
 
#define LEGACY_IO_RESOURCE  (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
#define CARDBUS_LATENCY_TIMER   176 /* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR   3
 
int pcibios_assign_all_busses(void)
{
    return 0;
};
 
 
 
 
 
 
 
 
 
 
 
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
static u64 pci_size(u64 base, u64 maxbase, u64 mask)
{
    u64 size = mask & maxbase;  /* Find the significant bits */
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
{
    if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
        res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
        return pci_bar_io;
    }
 
    res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
    if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
        return pci_bar_mem64;
    return pci_bar_mem32;
}
 
 
 
/**
 * pci_read_base - read a PCI BAR
 * @dev: the PCI device
 * @type: type of the BAR
 * @res: resource buffer to be filled in
 * @pos: BAR position in the config space
 *
 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
 */
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
            struct resource *res, unsigned int pos)
{
    u32 l, sz, mask;
    u16 orig_cmd;
 
    mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 
    if (!dev->mmio_always_on) {
        pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
        pci_write_config_word(dev, PCI_COMMAND,
            orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
    }
 
    res->name = pci_name(dev);
 
    pci_read_config_dword(dev, pos, &l);
    pci_write_config_dword(dev, pos, l | mask);
    pci_read_config_dword(dev, pos, &sz);
    pci_write_config_dword(dev, pos, l);
 
    if (!dev->mmio_always_on)
        pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 
    /*
     * All bits set in sz means the device isn't working properly.
     * If the BAR isn't implemented, all bits must be 0.  If it's a
     * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
     * 1 must be clear.
     */
    if (!sz || sz == 0xffffffff)
        goto fail;
 
    /*
     * I don't know how l can have all bits set.  Copied from old code.
     * Maybe it fixes a bug on some ancient platform.
     */
    if (l == 0xffffffff)
        l = 0;
 
    if (type == pci_bar_unknown) {
        type = decode_bar(res, l);
        res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
        if (type == pci_bar_io) {
            l &= PCI_BASE_ADDRESS_IO_MASK;
            mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
        } else {
            l &= PCI_BASE_ADDRESS_MEM_MASK;
            mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
        }
    } else {
        res->flags |= (l & IORESOURCE_ROM_ENABLE);
        l &= PCI_ROM_ADDRESS_MASK;
        mask = (u32)PCI_ROM_ADDRESS_MASK;
    }
 
    if (type == pci_bar_mem64) {
        u64 l64 = l;
        u64 sz64 = sz;
        u64 mask64 = mask | (u64)~0 << 32;
 
        pci_read_config_dword(dev, pos + 4, &l);
        pci_write_config_dword(dev, pos + 4, ~0);
        pci_read_config_dword(dev, pos + 4, &sz);
        pci_write_config_dword(dev, pos + 4, l);
 
        l64 |= ((u64)l << 32);
        sz64 |= ((u64)sz << 32);
 
        sz64 = pci_size(l64, sz64, mask64);
 
        if (!sz64)
            goto fail;
 
        if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
            dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
                __FUNCTION__, pos);
            goto fail;
        }
 
        res->flags |= IORESOURCE_MEM_64;
        if ((sizeof(resource_size_t) < 8) && l) {
            /* Address above 32-bit boundary; disable the BAR */
            pci_write_config_dword(dev, pos, 0);
            pci_write_config_dword(dev, pos + 4, 0);
            res->start = 0;
            res->end = sz64;
        } else {
            res->start = l64;
            res->end = l64 + sz64;
        dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
        }
    } else {
        sz = pci_size(l, sz, mask);
 
        if (!sz)
            goto fail;
 
        res->start = l;
        res->end = l + sz;
 
        dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
    }
 
 out:
    return (type == pci_bar_mem64) ? 1 : 0;
 fail:
    res->flags = 0;
    goto out;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    unsigned int pos, reg;
 
    for (pos = 0; pos < howmany; pos++) {
        struct resource *res = &dev->resource[pos];
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
    }
 
    if (rom) {
        struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
        dev->rom_base_reg = rom;
        res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
                IORESOURCE_SIZEALIGN;
        __pci_read_base(dev, pci_bar_mem32, res, rom);
    }
}
 
#if 0
 
void pci_read_bridge_bases(struct pci_bus *child)
{
    struct pci_dev *dev = child->self;
    struct resource *res;
    int i;
 
    if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
        return;
 
    dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
         child->secondary, child->subordinate,
         dev->transparent ? " (subtractive decode)" : "");
 
    pci_bus_remove_resources(child);
    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
        child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 
    pci_read_bridge_io(child);
    pci_read_bridge_mmio(child);
    pci_read_bridge_mmio_pref(child);
 
    if (dev->transparent) {
        pci_bus_for_each_resource(child->parent, res, i) {
            if (res) {
                pci_bus_add_resource(child, res,
                             PCI_SUBTRACTIVE_DECODE);
                dbgprintf("  bridge window %pR (subtractive decode)\n", res);
            }
        }
    }
}
 
#endif
 
static struct pci_bus * pci_alloc_bus(void)
{
    struct pci_bus *b;
 
    b = kzalloc(sizeof(*b), GFP_KERNEL);
    if (b) {
        INIT_LIST_HEAD(&b->node);
        INIT_LIST_HEAD(&b->children);
        INIT_LIST_HEAD(&b->devices);
        INIT_LIST_HEAD(&b->slots);
        INIT_LIST_HEAD(&b->resources);
//        b->max_bus_speed = PCI_SPEED_UNKNOWN;
//        b->cur_bus_speed = PCI_SPEED_UNKNOWN;
    }
    return b;
}
 
 
#if 0
 
static unsigned char pcix_bus_speed[] = {
    PCI_SPEED_UNKNOWN,      /* 0 */
    PCI_SPEED_66MHz_PCIX,       /* 1 */
    PCI_SPEED_100MHz_PCIX,      /* 2 */
    PCI_SPEED_133MHz_PCIX,      /* 3 */
    PCI_SPEED_UNKNOWN,      /* 4 */
    PCI_SPEED_66MHz_PCIX_ECC,   /* 5 */
    PCI_SPEED_100MHz_PCIX_ECC,  /* 6 */
    PCI_SPEED_133MHz_PCIX_ECC,  /* 7 */
    PCI_SPEED_UNKNOWN,      /* 8 */
    PCI_SPEED_66MHz_PCIX_266,   /* 9 */
    PCI_SPEED_100MHz_PCIX_266,  /* A */
    PCI_SPEED_133MHz_PCIX_266,  /* B */
    PCI_SPEED_UNKNOWN,      /* C */
    PCI_SPEED_66MHz_PCIX_533,   /* D */
    PCI_SPEED_100MHz_PCIX_533,  /* E */
    PCI_SPEED_133MHz_PCIX_533   /* F */
};
 
static unsigned char pcie_link_speed[] = {
    PCI_SPEED_UNKNOWN,      /* 0 */
    PCIE_SPEED_2_5GT,       /* 1 */
    PCIE_SPEED_5_0GT,       /* 2 */
    PCIE_SPEED_8_0GT,       /* 3 */
    PCI_SPEED_UNKNOWN,      /* 4 */
    PCI_SPEED_UNKNOWN,      /* 5 */
    PCI_SPEED_UNKNOWN,      /* 6 */
    PCI_SPEED_UNKNOWN,      /* 7 */
    PCI_SPEED_UNKNOWN,      /* 8 */
    PCI_SPEED_UNKNOWN,      /* 9 */
    PCI_SPEED_UNKNOWN,      /* A */
    PCI_SPEED_UNKNOWN,      /* B */
    PCI_SPEED_UNKNOWN,      /* C */
    PCI_SPEED_UNKNOWN,      /* D */
    PCI_SPEED_UNKNOWN,      /* E */
    PCI_SPEED_UNKNOWN       /* F */
};
 
 
static void pci_set_bus_speed(struct pci_bus *bus)
{
    struct pci_dev *bridge = bus->self;
    int pos;
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
    if (!pos)
        pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
    if (pos) {
        u32 agpstat, agpcmd;
 
        pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
        bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
 
        pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
        bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
    }
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
    if (pos) {
        u16 status;
        enum pci_bus_speed max;
        pci_read_config_word(bridge, pos + 2, &status);
 
        if (status & 0x8000) {
            max = PCI_SPEED_133MHz_PCIX_533;
        } else if (status & 0x4000) {
            max = PCI_SPEED_133MHz_PCIX_266;
        } else if (status & 0x0002) {
            if (((status >> 12) & 0x3) == 2) {
                max = PCI_SPEED_133MHz_PCIX_ECC;
            } else {
                max = PCI_SPEED_133MHz_PCIX;
            }
        } else {
            max = PCI_SPEED_66MHz_PCIX;
        }
 
        bus->max_bus_speed = max;
        bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
 
        return;
    }
 
    pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
    if (pos) {
        u32 linkcap;
        u16 linksta;
 
        pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
        bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
 
        pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
        pcie_update_link_speed(bus, linksta);
    }
}
 
#endif
 
 
static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
                       struct pci_dev *bridge, int busnr)
{
    struct pci_bus *child;
    int i;
 
    /*
     * Allocate a new bus, and inherit stuff from the parent..
     */
    child = pci_alloc_bus();
    if (!child)
        return NULL;
 
    child->parent = parent;
    child->ops = parent->ops;
    child->sysdata = parent->sysdata;
    child->bus_flags = parent->bus_flags;
 
    /* initialize some portions of the bus device, but don't register it
     * now as the parent is not properly set up yet.  This device will get
     * registered later in pci_bus_add_devices()
     */
//    child->dev.class = &pcibus_class;
//    dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 
    /*
     * Set up the primary, secondary and subordinate
     * bus numbers.
     */
    child->number = child->secondary = busnr;
    child->primary = parent->secondary;
    child->subordinate = 0xff;
 
    if (!bridge)
        return child;
 
    child->self = bridge;
//    child->bridge = get_device(&bridge->dev);
 
//    pci_set_bus_speed(child);
 
    /* Set up default resource pointers and names.. */
    for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
        child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
        child->resource[i]->name = child->name;
    }
    bridge->subordinate = child;
 
    return child;
}
 
struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
{
    struct pci_bus *child;
 
    child = pci_alloc_child_bus(parent, dev, busnr);
    if (child) {
//        down_write(&pci_bus_sem);
        list_add_tail(&child->node, &parent->children);
//        up_write(&pci_bus_sem);
    }
    return child;
}
 
 
static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
{
    struct pci_bus *parent = child->parent;
 
    /* Attempts to fix that up are really dangerous unless
       we're going to re-assign all bus numbers. */
    if (!pcibios_assign_all_busses())
        return;
 
    while (parent->parent && parent->subordinate < max) {
        parent->subordinate = max;
        pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
        parent = parent->parent;
    }
}
 
 
/*
 * If it's a bridge, configure it and scan the bus behind it.
 * For CardBus bridges, we don't scan behind as the devices will
 * be handled by the bridge driver itself.
 *
 * We need to process bridges in two passes -- first we scan those
 * already configured by the BIOS and after we are done with all of
 * them, we proceed to assigning numbers to the remaining buses in
 * order to avoid overlaps between old and new bus numbers.
 */
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
{
    struct pci_bus *child;
    int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
    u32 buses, i, j = 0;
    u16 bctl;
    u8 primary, secondary, subordinate;
    int broken = 0;
 
    pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
    primary = buses & 0xFF;
    secondary = (buses >> 8) & 0xFF;
    subordinate = (buses >> 16) & 0xFF;
 
    dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
        secondary, subordinate, pass);
 
    /* Check if setup is sensible at all */
    if (!pass &&
        (primary != bus->number || secondary <= bus->number)) {
        dbgprintf("bus configuration invalid, reconfiguring\n");
        broken = 1;
    }
 
    /* Disable MasterAbortMode during probing to avoid reporting
       of bus errors (in some architectures) */
    pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
    pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                  bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 
    if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
        !is_cardbus && !broken) {
        unsigned int cmax;
        /*
         * Bus already configured by firmware, process it in the first
         * pass and just note the configuration.
         */
        if (pass)
            goto out;
 
        /*
         * If we already got to this bus through a different bridge,
         * don't re-add it. This can happen with the i450NX chipset.
         *
         * However, we continue to descend down the hierarchy and
         * scan remaining child buses.
         */
        child = pci_find_bus(pci_domain_nr(bus), secondary);
        if (!child) {
            child = pci_add_new_bus(bus, dev, secondary);
            if (!child)
                goto out;
            child->primary = primary;
            child->subordinate = subordinate;
            child->bridge_ctl = bctl;
        }
 
        cmax = pci_scan_child_bus(child);
        if (cmax > max)
            max = cmax;
        if (child->subordinate > max)
            max = child->subordinate;
    } else {
        /*
         * We need to assign a number to this bus which we always
         * do in the second pass.
         */
        if (!pass) {
            if (pcibios_assign_all_busses() || broken)
                /* Temporarily disable forwarding of the
                   configuration cycles on all bridges in
                   this bus segment to avoid possible
                   conflicts in the second pass between two
                   bridges programmed with overlapping
                   bus ranges. */
                pci_write_config_dword(dev, PCI_PRIMARY_BUS,
                               buses & ~0xffffff);
            goto out;
        }
 
        /* Clear errors */
        pci_write_config_word(dev, PCI_STATUS, 0xffff);
 
        /* Prevent assigning a bus number that already exists.
         * This can happen when a bridge is hot-plugged */
        if (pci_find_bus(pci_domain_nr(bus), max+1))
            goto out;
        child = pci_add_new_bus(bus, dev, ++max);
        buses = (buses & 0xff000000)
              | ((unsigned int)(child->primary)     <<  0)
              | ((unsigned int)(child->secondary)   <<  8)
              | ((unsigned int)(child->subordinate) << 16);
 
        /*
         * yenta.c forces a secondary latency timer of 176.
         * Copy that behaviour here.
         */
        if (is_cardbus) {
            buses &= ~0xff000000;
            buses |= CARDBUS_LATENCY_TIMER << 24;
        }
 
        /*
         * We need to blast all three values with a single write.
         */
        pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
        if (!is_cardbus) {
            child->bridge_ctl = bctl;
            /*
             * Adjust subordinate busnr in parent buses.
             * We do this before scanning for children because
             * some devices may not be detected if the bios
             * was lazy.
             */
            pci_fixup_parent_subordinate_busnr(child, max);
            /* Now we can scan all subordinate buses... */
            max = pci_scan_child_bus(child);
            /*
             * now fix it up again since we have found
             * the real value of max.
             */
            pci_fixup_parent_subordinate_busnr(child, max);
        } else {
            /*
             * For CardBus bridges, we leave 4 bus numbers
             * as cards with a PCI-to-PCI bridge can be
             * inserted later.
             */
            for (i=0; i
                struct pci_bus *parent = bus;
                if (pci_find_bus(pci_domain_nr(bus),
                            max+i+1))
                    break;
                while (parent->parent) {
                    if ((!pcibios_assign_all_busses()) &&
                        (parent->subordinate > max) &&
                        (parent->subordinate <= max+i)) {
                        j = 1;
                    }
                    parent = parent->parent;
                }
                if (j) {
                    /*
                     * Often, there are two cardbus bridges
                     * -- try to leave one valid bus number
                     * for each one.
                     */
                    i /= 2;
                    break;
                }
            }
            max += i;
            pci_fixup_parent_subordinate_busnr(child, max);
        }
        /*
         * Set the subordinate bus number to its real value.
         */
        child->subordinate = max;
        pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
    }
 
    sprintf(child->name,
        (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
        pci_domain_nr(bus), child->number);
 
    /* Has only triggered on CardBus, fixup is in yenta_socket */
    while (bus->parent) {
        if ((child->subordinate > bus->subordinate) ||
            (child->number > bus->subordinate) ||
            (child->number < bus->number) ||
            (child->subordinate < bus->number)) {
            dbgprintf("[bus %02x-%02x] %s "
                "hidden behind%s bridge %s [bus %02x-%02x]\n",
                child->number, child->subordinate,
                (bus->number > child->subordinate &&
                 bus->subordinate < child->number) ?
                    "wholly" : "partially",
                bus->self->transparent ? " transparent" : "",
                "FIX BRIDGE NAME",
                bus->number, bus->subordinate);
        }
        bus = bus->parent;
    }
 
out:
    pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 
    return max;
}
 
void set_pcie_port_type(struct pci_dev *pdev)
{
    int pos;
    u16 reg16;
 
    pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
    if (!pos)
        return;
    //pdev->is_pcie = 1;
    pdev->pcie_cap = pos;
    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
    pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
}
 
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
{
    int pos;
    u16 reg16;
    u32 reg32;
 
    pos = pci_pcie_cap(pdev);
    if (!pos)
        return;
    pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
    if (!(reg16 & PCI_EXP_FLAGS_SLOT))
        return;
    pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
    if (reg32 & PCI_EXP_SLTCAP_HPC)
        pdev->is_hotplug_bridge = 1;
}
 
/*
 * Read interrupt line and base address registers.
 * The architecture-dependent code can tweak these, of course.
 */
static void pci_read_irq(struct pci_dev *dev)
{
    unsigned char irq;
 
    pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
    dev->pin = irq;
    if (irq)
        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
    dev->irq = irq;
}
 
 
/**
 * pci_setup_device - fill in class and map information of a device
 * @dev: the device structure to fill
 *
 * Initialize the device structure with information about the device's
 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 * Called at initialisation of the PCI subsystem and by CardBus services.
 * Returns 0 on success and negative if unknown type of device (not normal,
 * bridge or CardBus).
 */
int pci_setup_device(struct pci_dev *dev)
{
    u32 class;
    u8 hdr_type;
    struct pci_slot *slot;
    int pos = 0;
 
    if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
        return -EIO;
 
    dev->sysdata = dev->bus->sysdata;
//    dev->dev.parent = dev->bus->bridge;
//    dev->dev.bus = &pci_bus_type;
    dev->hdr_type = hdr_type & 0x7f;
    dev->multifunction = !!(hdr_type & 0x80);
    dev->error_state = pci_channel_io_normal;
    set_pcie_port_type(dev);
 
    list_for_each_entry(slot, &dev->bus->slots, list)
        if (PCI_SLOT(dev->devfn) == slot->number)
            dev->slot = slot;
 
    /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
       set this higher, assuming the system even supports it.  */
    dev->dma_mask = 0xffffffff;
 
//    dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
//             dev->bus->number, PCI_SLOT(dev->devfn),
//             PCI_FUNC(dev->devfn));
 
    pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
    dev->revision = class & 0xff;
    class >>= 8;                    /* upper 3 bytes */
    dev->class = class;
    class >>= 8;
 
    dbgprintf("found [%04x:%04x] class %06x header type %02x\n",
         dev->vendor, dev->device, class, dev->hdr_type);
 
    /* need to have dev->class ready */
    dev->cfg_size = pci_cfg_space_size(dev);
 
    /* "Unknown power state" */
    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
//    pci_fixup_device(pci_fixup_early, dev);
    /* device class may be changed after fixup */
    class = dev->class >> 8;
 
    switch (dev->hdr_type) {            /* header type */
    case PCI_HEADER_TYPE_NORMAL:            /* standard header */
        if (class == PCI_CLASS_BRIDGE_PCI)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
        pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 
        /*
         *  Do the ugly legacy mode stuff here rather than broken chip
         *  quirk code. Legacy mode ATA controllers have fixed
         *  addresses. These are not always echoed in BAR0-3, and
         *  BAR0-3 in a few cases contain junk!
         */
        if (class == PCI_CLASS_STORAGE_IDE) {
            u8 progif;
            pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
            if ((progif & 1) == 0) {
                dev->resource[0].start = 0x1F0;
                dev->resource[0].end = 0x1F7;
                dev->resource[0].flags = LEGACY_IO_RESOURCE;
                dev->resource[1].start = 0x3F6;
                dev->resource[1].end = 0x3F6;
                dev->resource[1].flags = LEGACY_IO_RESOURCE;
            }
            if ((progif & 4) == 0) {
                dev->resource[2].start = 0x170;
                dev->resource[2].end = 0x177;
                dev->resource[2].flags = LEGACY_IO_RESOURCE;
                dev->resource[3].start = 0x376;
                dev->resource[3].end = 0x376;
                dev->resource[3].flags = LEGACY_IO_RESOURCE;
            }
        }
        break;
 
    case PCI_HEADER_TYPE_BRIDGE:            /* bridge header */
        if (class != PCI_CLASS_BRIDGE_PCI)
            goto bad;
        /* The PCI-to-PCI bridge spec requires that subtractive
           decoding (i.e. transparent) bridge must have programming
           interface code of 0x01. */
        pci_read_irq(dev);
        dev->transparent = ((dev->class & 0xff) == 1);
        pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
        set_pcie_hotplug_bridge(dev);
        pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
        if (pos) {
            pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
            pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
        }
        break;
 
    case PCI_HEADER_TYPE_CARDBUS:           /* CardBus bridge header */
        if (class != PCI_CLASS_BRIDGE_CARDBUS)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 1, 0);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
        break;
 
    default:                    /* unknown header */
        dbgprintf("unknown header type %02x, "
            "ignoring device\n", dev->hdr_type);
        return -EIO;
 
    bad:
        dbgprintf("ignoring class %02x (doesn't match header "
            "type %02x)\n", class, dev->hdr_type);
        dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
    return 0;
}
 
 
 
struct pci_dev *alloc_pci_dev(void)
{
    struct pci_dev *dev;
 
    dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
    if (!dev)
        return NULL;
 
    INIT_LIST_HEAD(&dev->bus_list);
 
    return dev;
}
 
/*
 * Read the config data for a PCI device, sanity-check it
 * and fill in the dev structure...
 */
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;
    u32 l;
    int timeout = 10;
 
    if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
        return NULL;
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (l == 0xffffffff || l == 0x00000000 ||
        l == 0x0000ffff || l == 0xffff0000)
        return NULL;
 
    /* Configuration request Retry Status */
    while (l == 0xffff0001) {
        delay(timeout/10);
        timeout *= 2;
        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
            return NULL;
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 1000) {
            printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
                    "responding\n", pci_domain_nr(bus),
                    bus->number, PCI_SLOT(devfn),
                    PCI_FUNC(devfn));
            return NULL;
        }
    }
 
    dev = alloc_pci_dev();
    if (!dev)
        return NULL;
 
    dev->bus = bus;
    dev->busnr = bus->number;
    dev->devfn = devfn;
    dev->vendor = l & 0xffff;
    dev->device = (l >> 16) & 0xffff;
 
    if (pci_setup_device(dev)) {
        kfree(dev);
        return NULL;
    }
 
    return dev;
}
 
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
{
//    device_initialize(&dev->dev);
//    dev->dev.release = pci_release_dev;
//    pci_dev_get(dev);
 
//    dev->dev.dma_mask = &dev->dma_mask;
//    dev->dev.dma_parms = &dev->dma_parms;
//    dev->dev.coherent_dma_mask = 0xffffffffull;
 
//    pci_set_dma_max_seg_size(dev, 65536);
//    pci_set_dma_seg_boundary(dev, 0xffffffff);
 
    /* Fix up broken headers */
//    pci_fixup_device(pci_fixup_header, dev);
 
    /* Clear the state_saved flag. */
    dev->state_saved = false;
 
    /* Initialize various capabilities */
//    pci_init_capabilities(dev);
 
    /*
     * Add the device to our list of discovered devices
     * and the bus list for fixup functions, etc.
     */
//    down_write(&pci_bus_sem);
    list_add_tail(&dev->bus_list, &bus->devices);
//    up_write(&pci_bus_sem);
}
 
struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;
 
    dev = pci_get_slot(bus, devfn);
    if (dev) {
//        pci_dev_put(dev);
        return dev;
    }
 
    dev = pci_scan_device(bus, devfn);
    if (!dev)
        return NULL;
 
    pci_device_add(dev, bus);
 
    return dev;
}
 
static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
{
    u16 cap;
    unsigned pos, next_fn;
 
    if (!dev)
        return 0;
 
    pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
    if (!pos)
        return 0;
    pci_read_config_word(dev, pos + 4, &cap);
    next_fn = cap >> 8;
    if (next_fn <= fn)
        return 0;
    return next_fn;
}
 
static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
{
    return (fn + 1) % 8;
}
 
static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
{
    return 0;
}
 
static int only_one_child(struct pci_bus *bus)
{
    struct pci_dev *parent = bus->self;
    if (!parent || !pci_is_pcie(parent))
        return 0;
    if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
        parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
        return 1;
    return 0;
}
 
/**
 * pci_scan_slot - scan a PCI slot on a bus for devices.
 * @bus: PCI bus to scan
 * @devfn: slot number to scan (must have zero function.)
 *
 * Scan a PCI slot on the specified PCI bus for devices, adding
 * discovered devices to the @bus->devices list.  New devices
 * will not have is_added set.
 *
 * Returns the number of new devices found.
 */
int pci_scan_slot(struct pci_bus *bus, int devfn)
{
    unsigned fn, nr = 0;
    struct pci_dev *dev;
    unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
 
    if (only_one_child(bus) && (devfn > 0))
        return 0; /* Already scanned the entire slot */
 
    dev = pci_scan_single_device(bus, devfn);
    if (!dev)
        return 0;
    if (!dev->is_added)
        nr++;
 
    if (pci_ari_enabled(bus))
        next_fn = next_ari_fn;
    else if (dev->multifunction)
        next_fn = next_trad_fn;
 
    for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
        dev = pci_scan_single_device(bus, devfn + fn);
        if (dev) {
            if (!dev->is_added)
                nr++;
            dev->multifunction = 1;
        }
    }
 
    /* only one slot has pcie device */
//    if (bus->self && nr)
//        pcie_aspm_init_link_state(bus->self);
 
    return nr;
}
 
 
unsigned int pci_scan_child_bus(struct pci_bus *bus)
{
    unsigned int devfn, pass, max = bus->secondary;
    struct pci_dev *dev;
 
    dbgprintf("scanning bus\n");
 
    /* Go find them, Rover! */
    for (devfn = 0; devfn < 0x100; devfn += 8)
        pci_scan_slot(bus, devfn);
 
    /* Reserve buses for SR-IOV capability. */
    //max += pci_iov_bus_range(bus);
 
    /*
     * After performing arch-dependent fixup of the bus, look behind
     * all PCI-to-PCI bridges on this bus.
     */
    if (!bus->is_added) {
        dbgprintf("fixups for bus\n");
//        pcibios_fixup_bus(bus);
        if (pci_is_root_bus(bus))
            bus->is_added = 1;
    }
 
    for (pass=0; pass < 2; pass++)
        list_for_each_entry(dev, &bus->devices, bus_list) {
            if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
                dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
                max = pci_scan_bridge(bus, dev, max, pass);
        }
 
    /*
     * We've scanned the bus and so we know all about what's on
     * the other side of any bridges that may be on this bus plus
     * any devices.
     *
     * Return how far we've got finding sub-buses.
     */
    dbgprintf("bus scan returning with max=%02x\n", max);
    return max;
}
 
/**
 * pci_cfg_space_size - get the configuration space size of the PCI device.
 * @dev: PCI device
 *
 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 * access it.  Maybe we don't have a way to generate extended config space
 * accesses, or the device is behind a reverse Express bridge.  So we try
 * reading the dword at 0x100 which must either be 0 or a valid extended
 * capability header.
 */
int pci_cfg_space_size_ext(struct pci_dev *dev)
{
    u32 status;
    int pos = PCI_CFG_SPACE_SIZE;
 
    if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
        goto fail;
    if (status == 0xffffffff)
        goto fail;
 
    return PCI_CFG_SPACE_EXP_SIZE;
 
 fail:
    return PCI_CFG_SPACE_SIZE;
}
 
int pci_cfg_space_size(struct pci_dev *dev)
{
    int pos;
    u32 status;
    u16 class;
 
    class = dev->class >> 8;
    if (class == PCI_CLASS_BRIDGE_HOST)
        return pci_cfg_space_size_ext(dev);
 
    pos = pci_pcie_cap(dev);
    if (!pos) {
        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
        if (!pos)
            goto fail;
 
        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
            goto fail;
    }
 
    return pci_cfg_space_size_ext(dev);
 
 fail:
    return PCI_CFG_SPACE_SIZE;
}
 
 
 
struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata)
{
    int error;
    struct pci_bus *b, *b2;
 
    b = pci_alloc_bus();
    if (!b)
        return NULL;
 
    b->sysdata = sysdata;
    b->ops = ops;
 
    b2 = pci_find_bus(pci_domain_nr(b), bus);
    if (b2) {
        /* If we already got to this bus through a different bridge, ignore it */
        dbgprintf("bus already known\n");
        goto err_out;
    }
 
//    down_write(&pci_bus_sem);
    list_add_tail(&b->node, &pci_root_buses);
//    up_write(&pci_bus_sem);
 
    b->number = b->secondary = bus;
    b->resource[0] = &ioport_resource;
    b->resource[1] = &iomem_resource;
 
    return b;
 
err_out:
    kfree(b);
    return NULL;
}

Rev 2187	Rev 9499
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4	#include	4	#include
5	#include	5	#include
6	#include	6	#include
7		7
8	LIST_HEAD(pci_root_buses);	8	LIST_HEAD(pci_root_buses);
9		9
10	#define IO_SPACE_LIMIT 0xffff	10	#define IO_SPACE_LIMIT 0xffff
11		11
12		12
13		13
14		14
15	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	15	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
16		16
17	#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */	17	#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18	#define CARDBUS_RESERVE_BUSNR 3	18	#define CARDBUS_RESERVE_BUSNR 3
19		19
20	static int pcibios_assign_all_busses(void)	20	int pcibios_assign_all_busses(void)
21	{	21	{
22	return 0;	22	return 0;
23	};	23	};
24		24
25	/**	-
26	* pci_ari_enabled - query ARI forwarding status	-
27	* @bus: the PCI bus	-
28	*	-
29	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;	-
30	*/	-
31	static inline int pci_ari_enabled(struct pci_bus *bus)	-
32	{	-
33	return bus->self && bus->self->ari_enabled;	-
34	}	-
35		-
36	/*	25	/*
37	* Translate the low bits of the PCI base	26	* Translate the low bits of the PCI base
38	* to the resource type	27	* to the resource type
39	*/	28	*/
40	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	29	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
41	{	30	{
42	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	31	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
43	return IORESOURCE_IO;	32	return IORESOURCE_IO;
44		33
45	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	34	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
46	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	35	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
47		36
48	return IORESOURCE_MEM;	37	return IORESOURCE_MEM;
49	}	38	}
50		39
51	static u64 pci_size(u64 base, u64 maxbase, u64 mask)	40	static u64 pci_size(u64 base, u64 maxbase, u64 mask)
52	{	41	{
53	u64 size = mask & maxbase; /* Find the significant bits */	42	u64 size = mask & maxbase; /* Find the significant bits */
54	if (!size)	43	if (!size)
55	return 0;	44	return 0;
56		45
57	/* Get the lowest of them to find the decode size, and	46	/* Get the lowest of them to find the decode size, and
58	from that the extent. */	47	from that the extent. */
59	size = (size & ~(size-1)) - 1;	48	size = (size & ~(size-1)) - 1;
60		49
61	/* base == maxbase can be valid only if the BAR has	50	/* base == maxbase can be valid only if the BAR has
62	already been programmed with all 1s. */	51	already been programmed with all 1s. */
63	if (base == maxbase && ((base \| size) & mask) != mask)	52	if (base == maxbase && ((base \| size) & mask) != mask)
64	return 0;	53	return 0;
65		54
66	return size;	55	return size;
67	}	56	}
68		57
69	static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)	58	static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
70	{	59	{
71	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {	60	if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
72	res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;	61	res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
73	return pci_bar_io;	62	return pci_bar_io;
74	}	63	}
75		64
76	res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;	65	res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
77		66
78	if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)	67	if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
79	return pci_bar_mem64;	68	return pci_bar_mem64;
80	return pci_bar_mem32;	69	return pci_bar_mem32;
81	}	70	}
82		71
83		72
84		73
85	/**	74	/**
86	* pci_read_base - read a PCI BAR	75	* pci_read_base - read a PCI BAR
87	* @dev: the PCI device	76	* @dev: the PCI device
88	* @type: type of the BAR	77	* @type: type of the BAR
89	* @res: resource buffer to be filled in	78	* @res: resource buffer to be filled in
90	* @pos: BAR position in the config space	79	* @pos: BAR position in the config space
91	*	80	*
92	* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.	81	* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
93	*/	82	*/
94	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,	83	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
95	struct resource *res, unsigned int pos)	84	struct resource *res, unsigned int pos)
96	{	85	{
97	u32 l, sz, mask;	86	u32 l, sz, mask;
98	u16 orig_cmd;	87	u16 orig_cmd;
99		88
100	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;	89	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
101		90
102	if (!dev->mmio_always_on) {	91	if (!dev->mmio_always_on) {
103	pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);	92	pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
104	pci_write_config_word(dev, PCI_COMMAND,	93	pci_write_config_word(dev, PCI_COMMAND,
105	orig_cmd & ~(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO));	94	orig_cmd & ~(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO));
106	}	95	}
107		96
108	res->name = pci_name(dev);	97	res->name = pci_name(dev);
109		98
110	pci_read_config_dword(dev, pos, &l);	99	pci_read_config_dword(dev, pos, &l);
111	pci_write_config_dword(dev, pos, l \| mask);	100	pci_write_config_dword(dev, pos, l \| mask);
112	pci_read_config_dword(dev, pos, &sz);	101	pci_read_config_dword(dev, pos, &sz);
113	pci_write_config_dword(dev, pos, l);	102	pci_write_config_dword(dev, pos, l);
114		103
115	if (!dev->mmio_always_on)	104	if (!dev->mmio_always_on)
116	pci_write_config_word(dev, PCI_COMMAND, orig_cmd);	105	pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
117		106
118	/*	107	/*
119	* All bits set in sz means the device isn't working properly.	108	* All bits set in sz means the device isn't working properly.
120	* If the BAR isn't implemented, all bits must be 0. If it's a	109	* If the BAR isn't implemented, all bits must be 0. If it's a
121	* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit	110	* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
122	* 1 must be clear.	111	* 1 must be clear.
123	*/	112	*/
124	if (!sz \|\| sz == 0xffffffff)	113	if (!sz \|\| sz == 0xffffffff)
125	goto fail;	114	goto fail;
126		115
127	/*	116	/*
128	* I don't know how l can have all bits set. Copied from old code.	117	* I don't know how l can have all bits set. Copied from old code.
129	* Maybe it fixes a bug on some ancient platform.	118	* Maybe it fixes a bug on some ancient platform.
130	*/	119	*/
131	if (l == 0xffffffff)	120	if (l == 0xffffffff)
132	l = 0;	121	l = 0;
133		122
134	if (type == pci_bar_unknown) {	123	if (type == pci_bar_unknown) {
135	type = decode_bar(res, l);	124	type = decode_bar(res, l);
136	res->flags \|= pci_calc_resource_flags(l) \| IORESOURCE_SIZEALIGN;	125	res->flags \|= pci_calc_resource_flags(l) \| IORESOURCE_SIZEALIGN;
137	if (type == pci_bar_io) {	126	if (type == pci_bar_io) {
138	l &= PCI_BASE_ADDRESS_IO_MASK;	127	l &= PCI_BASE_ADDRESS_IO_MASK;
139	mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;	128	mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
140	} else {	129	} else {
141	l &= PCI_BASE_ADDRESS_MEM_MASK;	130	l &= PCI_BASE_ADDRESS_MEM_MASK;
142	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;	131	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
143	}	132	}
144	} else {	133	} else {
145	res->flags \|= (l & IORESOURCE_ROM_ENABLE);	134	res->flags \|= (l & IORESOURCE_ROM_ENABLE);
146	l &= PCI_ROM_ADDRESS_MASK;	135	l &= PCI_ROM_ADDRESS_MASK;
147	mask = (u32)PCI_ROM_ADDRESS_MASK;	136	mask = (u32)PCI_ROM_ADDRESS_MASK;
148	}	137	}
149		138
150	if (type == pci_bar_mem64) {	139	if (type == pci_bar_mem64) {
151	u64 l64 = l;	140	u64 l64 = l;
152	u64 sz64 = sz;	141	u64 sz64 = sz;
153	u64 mask64 = mask \| (u64)~0 << 32;	142	u64 mask64 = mask \| (u64)~0 << 32;
154		143
155	pci_read_config_dword(dev, pos + 4, &l);	144	pci_read_config_dword(dev, pos + 4, &l);
156	pci_write_config_dword(dev, pos + 4, ~0);	145	pci_write_config_dword(dev, pos + 4, ~0);
157	pci_read_config_dword(dev, pos + 4, &sz);	146	pci_read_config_dword(dev, pos + 4, &sz);
158	pci_write_config_dword(dev, pos + 4, l);	147	pci_write_config_dword(dev, pos + 4, l);
159		148
160	l64 \|= ((u64)l << 32);	149	l64 \|= ((u64)l << 32);
161	sz64 \|= ((u64)sz << 32);	150	sz64 \|= ((u64)sz << 32);
162		151
163	sz64 = pci_size(l64, sz64, mask64);	152	sz64 = pci_size(l64, sz64, mask64);
164		153
165	if (!sz64)	154	if (!sz64)
166	goto fail;	155	goto fail;
167		156
168	if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {	157	if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
169	dbgprintf("%s reg %x: can't handle 64-bit BAR\n",	158	dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
170	__FUNCTION__, pos);	159	__FUNCTION__, pos);
171	goto fail;	160	goto fail;
172	}	161	}
173		162
174	res->flags \|= IORESOURCE_MEM_64;	163	res->flags \|= IORESOURCE_MEM_64;
175	if ((sizeof(resource_size_t) < 8) && l) {	164	if ((sizeof(resource_size_t) < 8) && l) {
176	/* Address above 32-bit boundary; disable the BAR */	165	/* Address above 32-bit boundary; disable the BAR */
177	pci_write_config_dword(dev, pos, 0);	166	pci_write_config_dword(dev, pos, 0);
178	pci_write_config_dword(dev, pos + 4, 0);	167	pci_write_config_dword(dev, pos + 4, 0);
179	res->start = 0;	168	res->start = 0;
180	res->end = sz64;	169	res->end = sz64;
181	} else {	170	} else {
182	res->start = l64;	171	res->start = l64;
183	res->end = l64 + sz64;	172	res->end = l64 + sz64;
184	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);	173	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
185	}	174	}
186	} else {	175	} else {
187	sz = pci_size(l, sz, mask);	176	sz = pci_size(l, sz, mask);
188		177
189	if (!sz)	178	if (!sz)
190	goto fail;	179	goto fail;
191		180
192	res->start = l;	181	res->start = l;
193	res->end = l + sz;	182	res->end = l + sz;
194		183
195	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);	184	dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
196	}	185	}
197		186
198	out:	187	out:
199	return (type == pci_bar_mem64) ? 1 : 0;	188	return (type == pci_bar_mem64) ? 1 : 0;
200	fail:	189	fail:
201	res->flags = 0;	190	res->flags = 0;
202	goto out;	191	goto out;
203	}	192	}
204		193
205	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	194	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
206	{	195	{
207	unsigned int pos, reg;	196	unsigned int pos, reg;
208		197
209	for (pos = 0; pos < howmany; pos++) {	198	for (pos = 0; pos < howmany; pos++) {
210	struct resource *res = &dev->resource[pos];	199	struct resource *res = &dev->resource[pos];
211	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	200	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
212	pos += __pci_read_base(dev, pci_bar_unknown, res, reg);	201	pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
213	}	202	}
214		203
215	if (rom) {	204	if (rom) {
216	struct resource *res = &dev->resource[PCI_ROM_RESOURCE];	205	struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
217	dev->rom_base_reg = rom;	206	dev->rom_base_reg = rom;
218	res->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	207	res->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
219	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE \|	208	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE \|
220	IORESOURCE_SIZEALIGN;	209	IORESOURCE_SIZEALIGN;
221	__pci_read_base(dev, pci_bar_mem32, res, rom);	210	__pci_read_base(dev, pci_bar_mem32, res, rom);
222	}	211	}
223	}	212	}
224		213
225	#if 0	214	#if 0
226		215
227	void pci_read_bridge_bases(struct pci_bus *child)	216	void pci_read_bridge_bases(struct pci_bus *child)
228	{	217	{
229	struct pci_dev *dev = child->self;	218	struct pci_dev *dev = child->self;
230	struct resource *res;	219	struct resource *res;
231	int i;	220	int i;
232		221
233	if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */	222	if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
234	return;	223	return;
235		224
236	dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",	225	dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
237	child->secondary, child->subordinate,	226	child->secondary, child->subordinate,
238	dev->transparent ? " (subtractive decode)" : "");	227	dev->transparent ? " (subtractive decode)" : "");
239		228
240	pci_bus_remove_resources(child);	229	pci_bus_remove_resources(child);
241	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)	230	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
242	child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];	231	child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
243		232
244	pci_read_bridge_io(child);	233	pci_read_bridge_io(child);
245	pci_read_bridge_mmio(child);	234	pci_read_bridge_mmio(child);
246	pci_read_bridge_mmio_pref(child);	235	pci_read_bridge_mmio_pref(child);
247		236
248	if (dev->transparent) {	237	if (dev->transparent) {
249	pci_bus_for_each_resource(child->parent, res, i) {	238	pci_bus_for_each_resource(child->parent, res, i) {
250	if (res) {	239	if (res) {
251	pci_bus_add_resource(child, res,	240	pci_bus_add_resource(child, res,
252	PCI_SUBTRACTIVE_DECODE);	241	PCI_SUBTRACTIVE_DECODE);
253	dbgprintf(" bridge window %pR (subtractive decode)\n", res);	242	dbgprintf(" bridge window %pR (subtractive decode)\n", res);
254	}	243	}
255	}	244	}
256	}	245	}
257	}	246	}
258		247
259	#endif	248	#endif
260		249
261	static struct pci_bus * pci_alloc_bus(void)	250	static struct pci_bus * pci_alloc_bus(void)
262	{	251	{
263	struct pci_bus *b;	252	struct pci_bus *b;
264		253
265	b = kzalloc(sizeof(*b), GFP_KERNEL);	254	b = kzalloc(sizeof(*b), GFP_KERNEL);
266	if (b) {	255	if (b) {
267	INIT_LIST_HEAD(&b->node);	256	INIT_LIST_HEAD(&b->node);
268	INIT_LIST_HEAD(&b->children);	257	INIT_LIST_HEAD(&b->children);
269	INIT_LIST_HEAD(&b->devices);	258	INIT_LIST_HEAD(&b->devices);
270	INIT_LIST_HEAD(&b->slots);	259	INIT_LIST_HEAD(&b->slots);
271	INIT_LIST_HEAD(&b->resources);	260	INIT_LIST_HEAD(&b->resources);
272	// b->max_bus_speed = PCI_SPEED_UNKNOWN;	261	// b->max_bus_speed = PCI_SPEED_UNKNOWN;
273	// b->cur_bus_speed = PCI_SPEED_UNKNOWN;	262	// b->cur_bus_speed = PCI_SPEED_UNKNOWN;
274	}	263	}
275	return b;	264	return b;
276	}	265	}
277		266
278		267
279	#if 0	268	#if 0
280		269
281	static unsigned char pcix_bus_speed[] = {	270	static unsigned char pcix_bus_speed[] = {
282	PCI_SPEED_UNKNOWN, /* 0 */	271	PCI_SPEED_UNKNOWN, /* 0 */
283	PCI_SPEED_66MHz_PCIX, /* 1 */	272	PCI_SPEED_66MHz_PCIX, /* 1 */
284	PCI_SPEED_100MHz_PCIX, /* 2 */	273	PCI_SPEED_100MHz_PCIX, /* 2 */
285	PCI_SPEED_133MHz_PCIX, /* 3 */	274	PCI_SPEED_133MHz_PCIX, /* 3 */
286	PCI_SPEED_UNKNOWN, /* 4 */	275	PCI_SPEED_UNKNOWN, /* 4 */
287	PCI_SPEED_66MHz_PCIX_ECC, /* 5 */	276	PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
288	PCI_SPEED_100MHz_PCIX_ECC, /* 6 */	277	PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
289	PCI_SPEED_133MHz_PCIX_ECC, /* 7 */	278	PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
290	PCI_SPEED_UNKNOWN, /* 8 */	279	PCI_SPEED_UNKNOWN, /* 8 */
291	PCI_SPEED_66MHz_PCIX_266, /* 9 */	280	PCI_SPEED_66MHz_PCIX_266, /* 9 */
292	PCI_SPEED_100MHz_PCIX_266, /* A */	281	PCI_SPEED_100MHz_PCIX_266, /* A */
293	PCI_SPEED_133MHz_PCIX_266, /* B */	282	PCI_SPEED_133MHz_PCIX_266, /* B */
294	PCI_SPEED_UNKNOWN, /* C */	283	PCI_SPEED_UNKNOWN, /* C */
295	PCI_SPEED_66MHz_PCIX_533, /* D */	284	PCI_SPEED_66MHz_PCIX_533, /* D */
296	PCI_SPEED_100MHz_PCIX_533, /* E */	285	PCI_SPEED_100MHz_PCIX_533, /* E */
297	PCI_SPEED_133MHz_PCIX_533 /* F */	286	PCI_SPEED_133MHz_PCIX_533 /* F */
298	};	287	};
299		288
300	static unsigned char pcie_link_speed[] = {	289	static unsigned char pcie_link_speed[] = {
301	PCI_SPEED_UNKNOWN, /* 0 */	290	PCI_SPEED_UNKNOWN, /* 0 */
302	PCIE_SPEED_2_5GT, /* 1 */	291	PCIE_SPEED_2_5GT, /* 1 */
303	PCIE_SPEED_5_0GT, /* 2 */	292	PCIE_SPEED_5_0GT, /* 2 */
304	PCIE_SPEED_8_0GT, /* 3 */	293	PCIE_SPEED_8_0GT, /* 3 */
305	PCI_SPEED_UNKNOWN, /* 4 */	294	PCI_SPEED_UNKNOWN, /* 4 */
306	PCI_SPEED_UNKNOWN, /* 5 */	295	PCI_SPEED_UNKNOWN, /* 5 */
307	PCI_SPEED_UNKNOWN, /* 6 */	296	PCI_SPEED_UNKNOWN, /* 6 */
308	PCI_SPEED_UNKNOWN, /* 7 */	297	PCI_SPEED_UNKNOWN, /* 7 */
309	PCI_SPEED_UNKNOWN, /* 8 */	298	PCI_SPEED_UNKNOWN, /* 8 */
310	PCI_SPEED_UNKNOWN, /* 9 */	299	PCI_SPEED_UNKNOWN, /* 9 */
311	PCI_SPEED_UNKNOWN, /* A */	300	PCI_SPEED_UNKNOWN, /* A */
312	PCI_SPEED_UNKNOWN, /* B */	301	PCI_SPEED_UNKNOWN, /* B */
313	PCI_SPEED_UNKNOWN, /* C */	302	PCI_SPEED_UNKNOWN, /* C */
314	PCI_SPEED_UNKNOWN, /* D */	303	PCI_SPEED_UNKNOWN, /* D */
315	PCI_SPEED_UNKNOWN, /* E */	304	PCI_SPEED_UNKNOWN, /* E */
316	PCI_SPEED_UNKNOWN /* F */	305	PCI_SPEED_UNKNOWN /* F */
317	};	306	};
318		307
319		308
320	static void pci_set_bus_speed(struct pci_bus *bus)	309	static void pci_set_bus_speed(struct pci_bus *bus)
321	{	310	{
322	struct pci_dev *bridge = bus->self;	311	struct pci_dev *bridge = bus->self;
323	int pos;	312	int pos;
324		313
325	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);	314	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
326	if (!pos)	315	if (!pos)
327	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);	316	pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
328	if (pos) {	317	if (pos) {
329	u32 agpstat, agpcmd;	318	u32 agpstat, agpcmd;
330		319
331	pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);	320	pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
332	bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);	321	bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
333		322
334	pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);	323	pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
335	bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);	324	bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
336	}	325	}
337		326
338	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);	327	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
339	if (pos) {	328	if (pos) {
340	u16 status;	329	u16 status;
341	enum pci_bus_speed max;	330	enum pci_bus_speed max;
342	pci_read_config_word(bridge, pos + 2, &status);	331	pci_read_config_word(bridge, pos + 2, &status);
343		332
344	if (status & 0x8000) {	333	if (status & 0x8000) {
345	max = PCI_SPEED_133MHz_PCIX_533;	334	max = PCI_SPEED_133MHz_PCIX_533;
346	} else if (status & 0x4000) {	335	} else if (status & 0x4000) {
347	max = PCI_SPEED_133MHz_PCIX_266;	336	max = PCI_SPEED_133MHz_PCIX_266;
348	} else if (status & 0x0002) {	337	} else if (status & 0x0002) {
349	if (((status >> 12) & 0x3) == 2) {	338	if (((status >> 12) & 0x3) == 2) {
350	max = PCI_SPEED_133MHz_PCIX_ECC;	339	max = PCI_SPEED_133MHz_PCIX_ECC;
351	} else {	340	} else {
352	max = PCI_SPEED_133MHz_PCIX;	341	max = PCI_SPEED_133MHz_PCIX;
353	}	342	}
354	} else {	343	} else {
355	max = PCI_SPEED_66MHz_PCIX;	344	max = PCI_SPEED_66MHz_PCIX;
356	}	345	}
357		346
358	bus->max_bus_speed = max;	347	bus->max_bus_speed = max;
359	bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];	348	bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
360		349
361	return;	350	return;
362	}	351	}
363		352
364	pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);	353	pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
365	if (pos) {	354	if (pos) {
366	u32 linkcap;	355	u32 linkcap;
367	u16 linksta;	356	u16 linksta;
368		357
369	pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);	358	pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
370	bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];	359	bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
371		360
372	pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);	361	pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
373	pcie_update_link_speed(bus, linksta);	362	pcie_update_link_speed(bus, linksta);
374	}	363	}
375	}	364	}
376		365
377	#endif	366	#endif
378		367
379		368
380	static struct pci_bus pci_alloc_child_bus(struct pci_bus parent,	369	static struct pci_bus pci_alloc_child_bus(struct pci_bus parent,
381	struct pci_dev *bridge, int busnr)	370	struct pci_dev *bridge, int busnr)
382	{	371	{
383	struct pci_bus *child;	372	struct pci_bus *child;
384	int i;	373	int i;
385		374
386	/*	375	/*
387	* Allocate a new bus, and inherit stuff from the parent..	376	* Allocate a new bus, and inherit stuff from the parent..
388	*/	377	*/
389	child = pci_alloc_bus();	378	child = pci_alloc_bus();
390	if (!child)	379	if (!child)
391	return NULL;	380	return NULL;
392		381
393	child->parent = parent;	382	child->parent = parent;
394	child->ops = parent->ops;	383	child->ops = parent->ops;
395	child->sysdata = parent->sysdata;	384	child->sysdata = parent->sysdata;
396	child->bus_flags = parent->bus_flags;	385	child->bus_flags = parent->bus_flags;
397		386
398	/* initialize some portions of the bus device, but don't register it	387	/* initialize some portions of the bus device, but don't register it
399	* now as the parent is not properly set up yet. This device will get	388	* now as the parent is not properly set up yet. This device will get
400	* registered later in pci_bus_add_devices()	389	* registered later in pci_bus_add_devices()
401	*/	390	*/
402	// child->dev.class = &pcibus_class;	391	// child->dev.class = &pcibus_class;
403	// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);	392	// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
404		393
405	/*	394	/*
406	* Set up the primary, secondary and subordinate	395	* Set up the primary, secondary and subordinate
407	* bus numbers.	396	* bus numbers.
408	*/	397	*/
409	child->number = child->secondary = busnr;	398	child->number = child->secondary = busnr;
410	child->primary = parent->secondary;	399	child->primary = parent->secondary;
411	child->subordinate = 0xff;	400	child->subordinate = 0xff;
412		401
413	if (!bridge)	402	if (!bridge)
414	return child;	403	return child;
415		404
416	child->self = bridge;	405	child->self = bridge;
417	// child->bridge = get_device(&bridge->dev);	406	// child->bridge = get_device(&bridge->dev);
418		407
419	// pci_set_bus_speed(child);	408	// pci_set_bus_speed(child);
420		409
421	/* Set up default resource pointers and names.. */	410	/* Set up default resource pointers and names.. */
422	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {	411	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
423	child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];	412	child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
424	child->resource[i]->name = child->name;	413	child->resource[i]->name = child->name;
425	}	414	}
426	bridge->subordinate = child;	415	bridge->subordinate = child;
427		416
428	return child;	417	return child;
429	}	418	}
430		419
431	struct pci_bus* pci_add_new_bus(struct pci_bus parent, struct pci_dev dev, int busnr)	420	struct pci_bus* pci_add_new_bus(struct pci_bus parent, struct pci_dev dev, int busnr)
432	{	421	{
433	struct pci_bus *child;	422	struct pci_bus *child;
434		423
435	child = pci_alloc_child_bus(parent, dev, busnr);	424	child = pci_alloc_child_bus(parent, dev, busnr);
436	if (child) {	425	if (child) {
437	// down_write(&pci_bus_sem);	426	// down_write(&pci_bus_sem);
438	list_add_tail(&child->node, &parent->children);	427	list_add_tail(&child->node, &parent->children);
439	// up_write(&pci_bus_sem);	428	// up_write(&pci_bus_sem);
440	}	429	}
441	return child;	430	return child;
442	}	431	}
443		432
444		433
445	static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)	434	static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
446	{	435	{
447	struct pci_bus *parent = child->parent;	436	struct pci_bus *parent = child->parent;
448		437
449	/* Attempts to fix that up are really dangerous unless	438	/* Attempts to fix that up are really dangerous unless
450	we're going to re-assign all bus numbers. */	439	we're going to re-assign all bus numbers. */
451	if (!pcibios_assign_all_busses())	440	if (!pcibios_assign_all_busses())
452	return;	441	return;
453		442
454	while (parent->parent && parent->subordinate < max) {	443	while (parent->parent && parent->subordinate < max) {
455	parent->subordinate = max;	444	parent->subordinate = max;
456	pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);	445	pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
457	parent = parent->parent;	446	parent = parent->parent;
458	}	447	}
459	}	448	}
460		449
461		450
462	/*	451	/*
463	* If it's a bridge, configure it and scan the bus behind it.	452	* If it's a bridge, configure it and scan the bus behind it.
464	* For CardBus bridges, we don't scan behind as the devices will	453	* For CardBus bridges, we don't scan behind as the devices will
465	* be handled by the bridge driver itself.	454	* be handled by the bridge driver itself.
466	*	455	*
467	* We need to process bridges in two passes -- first we scan those	456	* We need to process bridges in two passes -- first we scan those
468	* already configured by the BIOS and after we are done with all of	457	* already configured by the BIOS and after we are done with all of
469	* them, we proceed to assigning numbers to the remaining buses in	458	* them, we proceed to assigning numbers to the remaining buses in
470	* order to avoid overlaps between old and new bus numbers.	459	* order to avoid overlaps between old and new bus numbers.
471	*/	460	*/
472	int pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, int pass)	461	int pci_scan_bridge(struct pci_bus bus, struct pci_dev dev, int max, int pass)
473	{	462	{
474	struct pci_bus *child;	463	struct pci_bus *child;
475	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);	464	int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
476	u32 buses, i, j = 0;	465	u32 buses, i, j = 0;
477	u16 bctl;	466	u16 bctl;
478	u8 primary, secondary, subordinate;	467	u8 primary, secondary, subordinate;
479	int broken = 0;	468	int broken = 0;
480		469
481	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);	470	pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
482	primary = buses & 0xFF;	471	primary = buses & 0xFF;
483	secondary = (buses >> 8) & 0xFF;	472	secondary = (buses >> 8) & 0xFF;
484	subordinate = (buses >> 16) & 0xFF;	473	subordinate = (buses >> 16) & 0xFF;
485		474
486	dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",	475	dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
487	secondary, subordinate, pass);	476	secondary, subordinate, pass);
488		477
489	/* Check if setup is sensible at all */	478	/* Check if setup is sensible at all */
490	if (!pass &&	479	if (!pass &&
491	(primary != bus->number \|\| secondary <= bus->number)) {	480	(primary != bus->number \|\| secondary <= bus->number)) {
492	dbgprintf("bus configuration invalid, reconfiguring\n");	481	dbgprintf("bus configuration invalid, reconfiguring\n");
493	broken = 1;	482	broken = 1;
494	}	483	}
495		484
496	/* Disable MasterAbortMode during probing to avoid reporting	485	/* Disable MasterAbortMode during probing to avoid reporting
497	of bus errors (in some architectures) */	486	of bus errors (in some architectures) */
498	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);	487	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
499	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,	488	pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
500	bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);	489	bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);

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(root)/drivers/devman/pci/probe.c @ 1692 – Rev 2187 → 9499