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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include |
26 | #include |
27 | #include |
27 | #include |
28 | #include "radeon.h" |
28 | #include "radeon.h" |
29 | 29 | ||
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | #include |
31 | #include |
32 | 32 | ||
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include |
37 | 37 | ||
38 | #include |
38 | #include |
39 | 39 | ||
40 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
40 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
41 | { |
41 | { |
42 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
42 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
43 | struct drm_device *dev = crtc->dev; |
43 | struct drm_device *dev = crtc->dev; |
44 | struct radeon_device *rdev = dev->dev_private; |
44 | struct radeon_device *rdev = dev->dev_private; |
45 | int i; |
45 | int i; |
46 | 46 | ||
47 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
47 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
48 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
48 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
49 | 49 | ||
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
51 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
51 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
52 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
52 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
53 | 53 | ||
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
55 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
55 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
56 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
56 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
57 | 57 | ||
58 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
58 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
59 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
59 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
60 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
60 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
61 | 61 | ||
62 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
62 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
63 | for (i = 0; i < 256; i++) { |
63 | for (i = 0; i < 256; i++) { |
64 | WREG32(AVIVO_DC_LUT_30_COLOR, |
64 | WREG32(AVIVO_DC_LUT_30_COLOR, |
65 | (radeon_crtc->lut_r[i] << 20) | |
65 | (radeon_crtc->lut_r[i] << 20) | |
66 | (radeon_crtc->lut_g[i] << 10) | |
66 | (radeon_crtc->lut_g[i] << 10) | |
67 | (radeon_crtc->lut_b[i] << 0)); |
67 | (radeon_crtc->lut_b[i] << 0)); |
68 | } |
68 | } |
69 | 69 | ||
70 | /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ |
70 | /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ |
71 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); |
71 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); |
72 | } |
72 | } |
73 | 73 | ||
74 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
74 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
75 | { |
75 | { |
76 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
76 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
77 | struct drm_device *dev = crtc->dev; |
77 | struct drm_device *dev = crtc->dev; |
78 | struct radeon_device *rdev = dev->dev_private; |
78 | struct radeon_device *rdev = dev->dev_private; |
79 | int i; |
79 | int i; |
80 | 80 | ||
81 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
81 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
82 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
82 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
83 | 83 | ||
84 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
84 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
85 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
85 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
86 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
86 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
87 | 87 | ||
88 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
88 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
89 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
89 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
90 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
90 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
91 | 91 | ||
92 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
92 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
93 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
93 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
94 | 94 | ||
95 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
95 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
96 | for (i = 0; i < 256; i++) { |
96 | for (i = 0; i < 256; i++) { |
97 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
97 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
98 | (radeon_crtc->lut_r[i] << 20) | |
98 | (radeon_crtc->lut_r[i] << 20) | |
99 | (radeon_crtc->lut_g[i] << 10) | |
99 | (radeon_crtc->lut_g[i] << 10) | |
100 | (radeon_crtc->lut_b[i] << 0)); |
100 | (radeon_crtc->lut_b[i] << 0)); |
101 | } |
101 | } |
102 | } |
102 | } |
103 | 103 | ||
104 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
104 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
105 | { |
105 | { |
106 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
106 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
107 | struct drm_device *dev = crtc->dev; |
107 | struct drm_device *dev = crtc->dev; |
108 | struct radeon_device *rdev = dev->dev_private; |
108 | struct radeon_device *rdev = dev->dev_private; |
109 | int i; |
109 | int i; |
110 | 110 | ||
111 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
111 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
112 | 112 | ||
113 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
113 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
114 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
114 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
115 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
115 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
116 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
116 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
117 | NI_GRPH_PRESCALE_BYPASS); |
117 | NI_GRPH_PRESCALE_BYPASS); |
118 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
118 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
119 | NI_OVL_PRESCALE_BYPASS); |
119 | NI_OVL_PRESCALE_BYPASS); |
120 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
120 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
121 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
121 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
122 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
122 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
123 | 123 | ||
124 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
124 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
125 | 125 | ||
126 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
126 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
127 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
127 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
128 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
128 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
129 | 129 | ||
130 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
130 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
131 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
131 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
132 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
132 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
133 | 133 | ||
134 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
134 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
135 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
135 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
136 | 136 | ||
137 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
137 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
138 | for (i = 0; i < 256; i++) { |
138 | for (i = 0; i < 256; i++) { |
139 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
139 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
140 | (radeon_crtc->lut_r[i] << 20) | |
140 | (radeon_crtc->lut_r[i] << 20) | |
141 | (radeon_crtc->lut_g[i] << 10) | |
141 | (radeon_crtc->lut_g[i] << 10) | |
142 | (radeon_crtc->lut_b[i] << 0)); |
142 | (radeon_crtc->lut_b[i] << 0)); |
143 | } |
143 | } |
144 | 144 | ||
145 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
145 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
146 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
146 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
147 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
147 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
148 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
148 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
149 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
149 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
150 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
150 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
151 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
151 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
152 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
152 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
153 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
153 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
154 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
154 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
155 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
155 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
156 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
156 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
157 | (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | |
157 | (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | |
158 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
158 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
159 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
159 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
160 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
160 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
161 | if (ASIC_IS_DCE8(rdev)) { |
161 | if (ASIC_IS_DCE8(rdev)) { |
162 | /* XXX this only needs to be programmed once per crtc at startup, |
162 | /* XXX this only needs to be programmed once per crtc at startup, |
163 | * not sure where the best place for it is |
163 | * not sure where the best place for it is |
164 | */ |
164 | */ |
165 | WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, |
165 | WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, |
166 | CIK_CURSOR_ALPHA_BLND_ENA); |
166 | CIK_CURSOR_ALPHA_BLND_ENA); |
167 | } |
167 | } |
168 | } |
168 | } |
169 | 169 | ||
170 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
170 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
171 | { |
171 | { |
172 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
172 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
173 | struct drm_device *dev = crtc->dev; |
173 | struct drm_device *dev = crtc->dev; |
174 | struct radeon_device *rdev = dev->dev_private; |
174 | struct radeon_device *rdev = dev->dev_private; |
175 | int i; |
175 | int i; |
176 | uint32_t dac2_cntl; |
176 | uint32_t dac2_cntl; |
177 | 177 | ||
178 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
178 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
179 | if (radeon_crtc->crtc_id == 0) |
179 | if (radeon_crtc->crtc_id == 0) |
180 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
180 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
181 | else |
181 | else |
182 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
182 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
183 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
183 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
184 | 184 | ||
185 | WREG8(RADEON_PALETTE_INDEX, 0); |
185 | WREG8(RADEON_PALETTE_INDEX, 0); |
186 | for (i = 0; i < 256; i++) { |
186 | for (i = 0; i < 256; i++) { |
187 | WREG32(RADEON_PALETTE_30_DATA, |
187 | WREG32(RADEON_PALETTE_30_DATA, |
188 | (radeon_crtc->lut_r[i] << 20) | |
188 | (radeon_crtc->lut_r[i] << 20) | |
189 | (radeon_crtc->lut_g[i] << 10) | |
189 | (radeon_crtc->lut_g[i] << 10) | |
190 | (radeon_crtc->lut_b[i] << 0)); |
190 | (radeon_crtc->lut_b[i] << 0)); |
191 | } |
191 | } |
192 | } |
192 | } |
193 | 193 | ||
194 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
194 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
195 | { |
195 | { |
196 | struct drm_device *dev = crtc->dev; |
196 | struct drm_device *dev = crtc->dev; |
197 | struct radeon_device *rdev = dev->dev_private; |
197 | struct radeon_device *rdev = dev->dev_private; |
198 | 198 | ||
199 | if (!crtc->enabled) |
199 | if (!crtc->enabled) |
200 | return; |
200 | return; |
201 | 201 | ||
202 | if (ASIC_IS_DCE5(rdev)) |
202 | if (ASIC_IS_DCE5(rdev)) |
203 | dce5_crtc_load_lut(crtc); |
203 | dce5_crtc_load_lut(crtc); |
204 | else if (ASIC_IS_DCE4(rdev)) |
204 | else if (ASIC_IS_DCE4(rdev)) |
205 | dce4_crtc_load_lut(crtc); |
205 | dce4_crtc_load_lut(crtc); |
206 | else if (ASIC_IS_AVIVO(rdev)) |
206 | else if (ASIC_IS_AVIVO(rdev)) |
207 | avivo_crtc_load_lut(crtc); |
207 | avivo_crtc_load_lut(crtc); |
208 | else |
208 | else |
209 | legacy_crtc_load_lut(crtc); |
209 | legacy_crtc_load_lut(crtc); |
210 | } |
210 | } |
211 | 211 | ||
212 | /** Sets the color ramps on behalf of fbcon */ |
212 | /** Sets the color ramps on behalf of fbcon */ |
213 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
213 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
214 | u16 blue, int regno) |
214 | u16 blue, int regno) |
215 | { |
215 | { |
216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
217 | 217 | ||
218 | radeon_crtc->lut_r[regno] = red >> 6; |
218 | radeon_crtc->lut_r[regno] = red >> 6; |
219 | radeon_crtc->lut_g[regno] = green >> 6; |
219 | radeon_crtc->lut_g[regno] = green >> 6; |
220 | radeon_crtc->lut_b[regno] = blue >> 6; |
220 | radeon_crtc->lut_b[regno] = blue >> 6; |
221 | } |
221 | } |
222 | 222 | ||
223 | /** Gets the color ramps on behalf of fbcon */ |
223 | /** Gets the color ramps on behalf of fbcon */ |
224 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
224 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
225 | u16 *blue, int regno) |
225 | u16 *blue, int regno) |
226 | { |
226 | { |
227 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
227 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
228 | 228 | ||
229 | *red = radeon_crtc->lut_r[regno] << 6; |
229 | *red = radeon_crtc->lut_r[regno] << 6; |
230 | *green = radeon_crtc->lut_g[regno] << 6; |
230 | *green = radeon_crtc->lut_g[regno] << 6; |
231 | *blue = radeon_crtc->lut_b[regno] << 6; |
231 | *blue = radeon_crtc->lut_b[regno] << 6; |
232 | } |
232 | } |
233 | 233 | ||
234 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
234 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
235 | u16 *blue, uint32_t start, uint32_t size) |
235 | u16 *blue, uint32_t start, uint32_t size) |
236 | { |
236 | { |
237 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
237 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
238 | int end = (start + size > 256) ? 256 : start + size, i; |
238 | int end = (start + size > 256) ? 256 : start + size, i; |
239 | 239 | ||
240 | /* userspace palettes are always correct as is */ |
240 | /* userspace palettes are always correct as is */ |
241 | for (i = start; i < end; i++) { |
241 | for (i = start; i < end; i++) { |
242 | radeon_crtc->lut_r[i] = red[i] >> 6; |
242 | radeon_crtc->lut_r[i] = red[i] >> 6; |
243 | radeon_crtc->lut_g[i] = green[i] >> 6; |
243 | radeon_crtc->lut_g[i] = green[i] >> 6; |
244 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
244 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
245 | } |
245 | } |
246 | radeon_crtc_load_lut(crtc); |
246 | radeon_crtc_load_lut(crtc); |
247 | } |
247 | } |
248 | 248 | ||
249 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
249 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
250 | { |
250 | { |
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
252 | 252 | ||
253 | drm_crtc_cleanup(crtc); |
253 | drm_crtc_cleanup(crtc); |
254 | kfree(radeon_crtc); |
254 | kfree(radeon_crtc); |
255 | } |
255 | } |
256 | 256 | ||
257 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) |
257 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) |
258 | { |
258 | { |
259 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
259 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
260 | unsigned long flags; |
260 | unsigned long flags; |
261 | u32 update_pending; |
261 | u32 update_pending; |
262 | int vpos, hpos; |
262 | int vpos, hpos; |
263 | 263 | ||
264 | /* can happen during initialization */ |
264 | /* can happen during initialization */ |
265 | if (radeon_crtc == NULL) |
265 | if (radeon_crtc == NULL) |
266 | return; |
266 | return; |
267 | 267 | ||
268 | /* Skip the pageflip completion check below (based on polling) on |
268 | /* Skip the pageflip completion check below (based on polling) on |
269 | * asics which reliably support hw pageflip completion irqs. pflip |
269 | * asics which reliably support hw pageflip completion irqs. pflip |
270 | * irqs are a reliable and race-free method of handling pageflip |
270 | * irqs are a reliable and race-free method of handling pageflip |
271 | * completion detection. A use_pflipirq module parameter < 2 allows |
271 | * completion detection. A use_pflipirq module parameter < 2 allows |
272 | * to override this in case of asics with faulty pflip irqs. |
272 | * to override this in case of asics with faulty pflip irqs. |
273 | * A module parameter of 0 would only use this polling based path, |
273 | * A module parameter of 0 would only use this polling based path, |
274 | * a parameter of 1 would use pflip irq only as a backup to this |
274 | * a parameter of 1 would use pflip irq only as a backup to this |
275 | * path, as in Linux 3.16. |
275 | * path, as in Linux 3.16. |
276 | */ |
276 | */ |
277 | if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) |
277 | if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) |
278 | return; |
278 | return; |
279 | 279 | ||
280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); |
280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); |
281 | if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { |
281 | if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { |
282 | DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " |
282 | DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " |
283 | "RADEON_FLIP_SUBMITTED(%d)\n", |
283 | "RADEON_FLIP_SUBMITTED(%d)\n", |
284 | radeon_crtc->flip_status, |
284 | radeon_crtc->flip_status, |
285 | RADEON_FLIP_SUBMITTED); |
285 | RADEON_FLIP_SUBMITTED); |
286 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
286 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
287 | return; |
287 | return; |
288 | } |
288 | } |
289 | 289 | ||
290 | update_pending = radeon_page_flip_pending(rdev, crtc_id); |
290 | update_pending = radeon_page_flip_pending(rdev, crtc_id); |
291 | 291 | ||
292 | /* Has the pageflip already completed in crtc, or is it certain |
292 | /* Has the pageflip already completed in crtc, or is it certain |
293 | * to complete in this vblank? |
293 | * to complete in this vblank? |
294 | */ |
294 | */ |
295 | if (update_pending && |
295 | if (update_pending && |
296 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, |
296 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, |
297 | crtc_id, |
297 | crtc_id, |
298 | USE_REAL_VBLANKSTART, |
298 | USE_REAL_VBLANKSTART, |
299 | &vpos, &hpos, NULL, NULL, |
299 | &vpos, &hpos, NULL, NULL, |
300 | &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && |
300 | &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && |
301 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
301 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
302 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { |
302 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { |
303 | /* crtc didn't flip in this target vblank interval, |
303 | /* crtc didn't flip in this target vblank interval, |
304 | * but flip is pending in crtc. Based on the current |
304 | * but flip is pending in crtc. Based on the current |
305 | * scanout position we know that the current frame is |
305 | * scanout position we know that the current frame is |
306 | * (nearly) complete and the flip will (likely) |
306 | * (nearly) complete and the flip will (likely) |
307 | * complete before the start of the next frame. |
307 | * complete before the start of the next frame. |
308 | */ |
308 | */ |
309 | update_pending = 0; |
309 | update_pending = 0; |
310 | } |
310 | } |
311 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
311 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
312 | // if (!update_pending) |
312 | // if (!update_pending) |
313 | // radeon_crtc_handle_flip(rdev, crtc_id); |
313 | // radeon_crtc_handle_flip(rdev, crtc_id); |
314 | } |
314 | } |
315 | 315 | ||
316 | static int |
316 | static int |
317 | radeon_crtc_set_config(struct drm_mode_set *set) |
317 | radeon_crtc_set_config(struct drm_mode_set *set) |
318 | { |
318 | { |
319 | struct drm_device *dev; |
319 | struct drm_device *dev; |
320 | struct radeon_device *rdev; |
320 | struct radeon_device *rdev; |
321 | struct drm_crtc *crtc; |
321 | struct drm_crtc *crtc; |
322 | bool active = false; |
322 | bool active = false; |
323 | int ret; |
323 | int ret; |
324 | 324 | ||
325 | if (!set || !set->crtc) |
325 | if (!set || !set->crtc) |
326 | return -EINVAL; |
326 | return -EINVAL; |
327 | 327 | ||
328 | dev = set->crtc->dev; |
328 | dev = set->crtc->dev; |
329 | 329 | ||
330 | ret = drm_crtc_helper_set_config(set); |
330 | ret = drm_crtc_helper_set_config(set); |
331 | 331 | ||
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
333 | if (crtc->enabled) |
333 | if (crtc->enabled) |
334 | active = true; |
334 | active = true; |
335 | 335 | ||
336 | // pm_runtime_mark_last_busy(dev->dev); |
336 | // pm_runtime_mark_last_busy(dev->dev); |
337 | 337 | ||
338 | rdev = dev->dev_private; |
338 | rdev = dev->dev_private; |
339 | /* if we have active crtcs and we don't have a power ref, |
339 | /* if we have active crtcs and we don't have a power ref, |
340 | take the current one */ |
340 | take the current one */ |
341 | if (active && !rdev->have_disp_power_ref) { |
341 | if (active && !rdev->have_disp_power_ref) { |
342 | rdev->have_disp_power_ref = true; |
342 | rdev->have_disp_power_ref = true; |
343 | return ret; |
343 | return ret; |
344 | } |
344 | } |
345 | /* if we have no active crtcs, then drop the power ref |
345 | /* if we have no active crtcs, then drop the power ref |
346 | we got before */ |
346 | we got before */ |
347 | if (!active && rdev->have_disp_power_ref) { |
347 | if (!active && rdev->have_disp_power_ref) { |
348 | // pm_runtime_put_autosuspend(dev->dev); |
348 | // pm_runtime_put_autosuspend(dev->dev); |
349 | rdev->have_disp_power_ref = false; |
349 | rdev->have_disp_power_ref = false; |
350 | } |
350 | } |
351 | 351 | ||
352 | /* drop the power reference we got coming in here */ |
352 | /* drop the power reference we got coming in here */ |
353 | // pm_runtime_put_autosuspend(dev->dev); |
353 | // pm_runtime_put_autosuspend(dev->dev); |
- | 354 | ||
354 | return ret; |
355 | return ret; |
355 | } |
356 | } |
356 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
357 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
357 | .cursor_set = NULL, |
358 | .cursor_set = NULL, |
358 | .cursor_move = NULL, |
359 | .cursor_move = NULL, |
359 | .gamma_set = radeon_crtc_gamma_set, |
360 | .gamma_set = radeon_crtc_gamma_set, |
360 | .set_config = radeon_crtc_set_config, |
361 | .set_config = radeon_crtc_set_config, |
361 | .destroy = radeon_crtc_destroy, |
362 | .destroy = radeon_crtc_destroy, |
362 | .page_flip = NULL, |
363 | .page_flip = NULL, |
363 | }; |
364 | }; |
364 | 365 | ||
365 | static void radeon_crtc_init(struct drm_device *dev, int index) |
366 | static void radeon_crtc_init(struct drm_device *dev, int index) |
366 | { |
367 | { |
367 | struct radeon_device *rdev = dev->dev_private; |
368 | struct radeon_device *rdev = dev->dev_private; |
368 | struct radeon_crtc *radeon_crtc; |
369 | struct radeon_crtc *radeon_crtc; |
369 | int i; |
370 | int i; |
370 | 371 | ||
371 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
372 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
372 | if (radeon_crtc == NULL) |
373 | if (radeon_crtc == NULL) |
373 | return; |
374 | return; |
374 | 375 | ||
375 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
376 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
376 | 377 | ||
377 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
378 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
378 | radeon_crtc->crtc_id = index; |
379 | radeon_crtc->crtc_id = index; |
379 | rdev->mode_info.crtcs[index] = radeon_crtc; |
380 | rdev->mode_info.crtcs[index] = radeon_crtc; |
380 | 381 | ||
381 | if (rdev->family >= CHIP_BONAIRE) { |
382 | if (rdev->family >= CHIP_BONAIRE) { |
382 | radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; |
383 | radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; |
383 | radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; |
384 | radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; |
384 | } else { |
385 | } else { |
385 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; |
386 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; |
386 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; |
387 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; |
387 | } |
388 | } |
388 | dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; |
389 | dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; |
389 | dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; |
390 | dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; |
390 | 391 | ||
391 | #if 0 |
392 | #if 0 |
392 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
393 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
393 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
394 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
394 | radeon_crtc->mode_set.num_connectors = 0; |
395 | radeon_crtc->mode_set.num_connectors = 0; |
395 | #endif |
396 | #endif |
396 | 397 | ||
397 | for (i = 0; i < 256; i++) { |
398 | for (i = 0; i < 256; i++) { |
398 | radeon_crtc->lut_r[i] = i << 2; |
399 | radeon_crtc->lut_r[i] = i << 2; |
399 | radeon_crtc->lut_g[i] = i << 2; |
400 | radeon_crtc->lut_g[i] = i << 2; |
400 | radeon_crtc->lut_b[i] = i << 2; |
401 | radeon_crtc->lut_b[i] = i << 2; |
401 | } |
402 | } |
402 | 403 | ||
403 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
404 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
404 | radeon_atombios_init_crtc(dev, radeon_crtc); |
405 | radeon_atombios_init_crtc(dev, radeon_crtc); |
405 | else |
406 | else |
406 | radeon_legacy_init_crtc(dev, radeon_crtc); |
407 | radeon_legacy_init_crtc(dev, radeon_crtc); |
407 | } |
408 | } |
408 | 409 | ||
409 | static const char *encoder_names[38] = { |
410 | static const char *encoder_names[38] = { |
410 | "NONE", |
411 | "NONE", |
411 | "INTERNAL_LVDS", |
412 | "INTERNAL_LVDS", |
412 | "INTERNAL_TMDS1", |
413 | "INTERNAL_TMDS1", |
413 | "INTERNAL_TMDS2", |
414 | "INTERNAL_TMDS2", |
414 | "INTERNAL_DAC1", |
415 | "INTERNAL_DAC1", |
415 | "INTERNAL_DAC2", |
416 | "INTERNAL_DAC2", |
416 | "INTERNAL_SDVOA", |
417 | "INTERNAL_SDVOA", |
417 | "INTERNAL_SDVOB", |
418 | "INTERNAL_SDVOB", |
418 | "SI170B", |
419 | "SI170B", |
419 | "CH7303", |
420 | "CH7303", |
420 | "CH7301", |
421 | "CH7301", |
421 | "INTERNAL_DVO1", |
422 | "INTERNAL_DVO1", |
422 | "EXTERNAL_SDVOA", |
423 | "EXTERNAL_SDVOA", |
423 | "EXTERNAL_SDVOB", |
424 | "EXTERNAL_SDVOB", |
424 | "TITFP513", |
425 | "TITFP513", |
425 | "INTERNAL_LVTM1", |
426 | "INTERNAL_LVTM1", |
426 | "VT1623", |
427 | "VT1623", |
427 | "HDMI_SI1930", |
428 | "HDMI_SI1930", |
428 | "HDMI_INTERNAL", |
429 | "HDMI_INTERNAL", |
429 | "INTERNAL_KLDSCP_TMDS1", |
430 | "INTERNAL_KLDSCP_TMDS1", |
430 | "INTERNAL_KLDSCP_DVO1", |
431 | "INTERNAL_KLDSCP_DVO1", |
431 | "INTERNAL_KLDSCP_DAC1", |
432 | "INTERNAL_KLDSCP_DAC1", |
432 | "INTERNAL_KLDSCP_DAC2", |
433 | "INTERNAL_KLDSCP_DAC2", |
433 | "SI178", |
434 | "SI178", |
434 | "MVPU_FPGA", |
435 | "MVPU_FPGA", |
435 | "INTERNAL_DDI", |
436 | "INTERNAL_DDI", |
436 | "VT1625", |
437 | "VT1625", |
437 | "HDMI_SI1932", |
438 | "HDMI_SI1932", |
438 | "DP_AN9801", |
439 | "DP_AN9801", |
439 | "DP_DP501", |
440 | "DP_DP501", |
440 | "INTERNAL_UNIPHY", |
441 | "INTERNAL_UNIPHY", |
441 | "INTERNAL_KLDSCP_LVTMA", |
442 | "INTERNAL_KLDSCP_LVTMA", |
442 | "INTERNAL_UNIPHY1", |
443 | "INTERNAL_UNIPHY1", |
443 | "INTERNAL_UNIPHY2", |
444 | "INTERNAL_UNIPHY2", |
444 | "NUTMEG", |
445 | "NUTMEG", |
445 | "TRAVIS", |
446 | "TRAVIS", |
446 | "INTERNAL_VCE", |
447 | "INTERNAL_VCE", |
447 | "INTERNAL_UNIPHY3", |
448 | "INTERNAL_UNIPHY3", |
448 | }; |
449 | }; |
449 | 450 | ||
450 | static const char *hpd_names[6] = { |
451 | static const char *hpd_names[6] = { |
451 | "HPD1", |
452 | "HPD1", |
452 | "HPD2", |
453 | "HPD2", |
453 | "HPD3", |
454 | "HPD3", |
454 | "HPD4", |
455 | "HPD4", |
455 | "HPD5", |
456 | "HPD5", |
456 | "HPD6", |
457 | "HPD6", |
457 | }; |
458 | }; |
458 | 459 | ||
459 | static void radeon_print_display_setup(struct drm_device *dev) |
460 | static void radeon_print_display_setup(struct drm_device *dev) |
460 | { |
461 | { |
461 | struct drm_connector *connector; |
462 | struct drm_connector *connector; |
462 | struct radeon_connector *radeon_connector; |
463 | struct radeon_connector *radeon_connector; |
463 | struct drm_encoder *encoder; |
464 | struct drm_encoder *encoder; |
464 | struct radeon_encoder *radeon_encoder; |
465 | struct radeon_encoder *radeon_encoder; |
465 | uint32_t devices; |
466 | uint32_t devices; |
466 | int i = 0; |
467 | int i = 0; |
467 | 468 | ||
468 | DRM_INFO("Radeon Display Connectors\n"); |
469 | DRM_INFO("Radeon Display Connectors\n"); |
469 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
470 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
470 | radeon_connector = to_radeon_connector(connector); |
471 | radeon_connector = to_radeon_connector(connector); |
471 | DRM_INFO("Connector %d:\n", i); |
472 | DRM_INFO("Connector %d:\n", i); |
472 | DRM_INFO(" %s\n", connector->name); |
473 | DRM_INFO(" %s\n", connector->name); |
473 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
474 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
474 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
475 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
475 | if (radeon_connector->ddc_bus) { |
476 | if (radeon_connector->ddc_bus) { |
476 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
477 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
477 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
478 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
478 | radeon_connector->ddc_bus->rec.mask_data_reg, |
479 | radeon_connector->ddc_bus->rec.mask_data_reg, |
479 | radeon_connector->ddc_bus->rec.a_clk_reg, |
480 | radeon_connector->ddc_bus->rec.a_clk_reg, |
480 | radeon_connector->ddc_bus->rec.a_data_reg, |
481 | radeon_connector->ddc_bus->rec.a_data_reg, |
481 | radeon_connector->ddc_bus->rec.en_clk_reg, |
482 | radeon_connector->ddc_bus->rec.en_clk_reg, |
482 | radeon_connector->ddc_bus->rec.en_data_reg, |
483 | radeon_connector->ddc_bus->rec.en_data_reg, |
483 | radeon_connector->ddc_bus->rec.y_clk_reg, |
484 | radeon_connector->ddc_bus->rec.y_clk_reg, |
484 | radeon_connector->ddc_bus->rec.y_data_reg); |
485 | radeon_connector->ddc_bus->rec.y_data_reg); |
485 | if (radeon_connector->router.ddc_valid) |
486 | if (radeon_connector->router.ddc_valid) |
486 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
487 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
487 | radeon_connector->router.ddc_mux_control_pin, |
488 | radeon_connector->router.ddc_mux_control_pin, |
488 | radeon_connector->router.ddc_mux_state); |
489 | radeon_connector->router.ddc_mux_state); |
489 | if (radeon_connector->router.cd_valid) |
490 | if (radeon_connector->router.cd_valid) |
490 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
491 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
491 | radeon_connector->router.cd_mux_control_pin, |
492 | radeon_connector->router.cd_mux_control_pin, |
492 | radeon_connector->router.cd_mux_state); |
493 | radeon_connector->router.cd_mux_state); |
493 | } else { |
494 | } else { |
494 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
495 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
495 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
496 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
496 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
497 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
497 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
498 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
498 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
499 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
499 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
500 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
500 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
501 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
501 | } |
502 | } |
502 | DRM_INFO(" Encoders:\n"); |
503 | DRM_INFO(" Encoders:\n"); |
503 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
504 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
504 | radeon_encoder = to_radeon_encoder(encoder); |
505 | radeon_encoder = to_radeon_encoder(encoder); |
505 | devices = radeon_encoder->devices & radeon_connector->devices; |
506 | devices = radeon_encoder->devices & radeon_connector->devices; |
506 | if (devices) { |
507 | if (devices) { |
507 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
508 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
508 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
509 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
509 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
510 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
510 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
511 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
511 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
512 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
512 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
513 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
513 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
514 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
514 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
515 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
515 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
516 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
516 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
517 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
517 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
518 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
518 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
519 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
519 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
520 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
520 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
521 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
521 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
522 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
522 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
523 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
523 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
524 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
524 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
525 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
525 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
526 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
526 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
527 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
527 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
528 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
528 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
529 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
529 | } |
530 | } |
530 | } |
531 | } |
531 | i++; |
532 | i++; |
532 | } |
533 | } |
533 | } |
534 | } |
534 | 535 | ||
535 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
536 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
536 | { |
537 | { |
537 | struct radeon_device *rdev = dev->dev_private; |
538 | struct radeon_device *rdev = dev->dev_private; |
538 | bool ret = false; |
539 | bool ret = false; |
539 | 540 | ||
540 | if (rdev->bios) { |
541 | if (rdev->bios) { |
541 | if (rdev->is_atom_bios) { |
542 | if (rdev->is_atom_bios) { |
542 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
543 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
543 | if (ret == false) |
544 | if (ret == false) |
544 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
545 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
545 | } else { |
546 | } else { |
546 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
547 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
547 | if (ret == false) |
548 | if (ret == false) |
548 | ret = radeon_get_legacy_connector_info_from_table(dev); |
549 | ret = radeon_get_legacy_connector_info_from_table(dev); |
549 | } |
550 | } |
550 | } else { |
551 | } else { |
551 | if (!ASIC_IS_AVIVO(rdev)) |
552 | if (!ASIC_IS_AVIVO(rdev)) |
552 | ret = radeon_get_legacy_connector_info_from_table(dev); |
553 | ret = radeon_get_legacy_connector_info_from_table(dev); |
553 | } |
554 | } |
554 | if (ret) { |
555 | if (ret) { |
555 | radeon_setup_encoder_clones(dev); |
556 | radeon_setup_encoder_clones(dev); |
556 | radeon_print_display_setup(dev); |
557 | radeon_print_display_setup(dev); |
557 | } |
558 | } |
558 | 559 | ||
559 | return ret; |
560 | return ret; |
560 | } |
561 | } |
561 | 562 | ||
562 | /* avivo */ |
563 | /* avivo */ |
563 | 564 | ||
564 | /** |
565 | /** |
565 | * avivo_reduce_ratio - fractional number reduction |
566 | * avivo_reduce_ratio - fractional number reduction |
566 | * |
567 | * |
567 | * @nom: nominator |
568 | * @nom: nominator |
568 | * @den: denominator |
569 | * @den: denominator |
569 | * @nom_min: minimum value for nominator |
570 | * @nom_min: minimum value for nominator |
570 | * @den_min: minimum value for denominator |
571 | * @den_min: minimum value for denominator |
571 | * |
572 | * |
572 | * Find the greatest common divisor and apply it on both nominator and |
573 | * Find the greatest common divisor and apply it on both nominator and |
573 | * denominator, but make nominator and denominator are at least as large |
574 | * denominator, but make nominator and denominator are at least as large |
574 | * as their minimum values. |
575 | * as their minimum values. |
575 | */ |
576 | */ |
576 | static void avivo_reduce_ratio(unsigned *nom, unsigned *den, |
577 | static void avivo_reduce_ratio(unsigned *nom, unsigned *den, |
577 | unsigned nom_min, unsigned den_min) |
578 | unsigned nom_min, unsigned den_min) |
578 | { |
579 | { |
579 | unsigned tmp; |
580 | unsigned tmp; |
580 | 581 | ||
581 | /* reduce the numbers to a simpler ratio */ |
582 | /* reduce the numbers to a simpler ratio */ |
582 | tmp = gcd(*nom, *den); |
583 | tmp = gcd(*nom, *den); |
583 | *nom /= tmp; |
584 | *nom /= tmp; |
584 | *den /= tmp; |
585 | *den /= tmp; |
585 | 586 | ||
586 | /* make sure nominator is large enough */ |
587 | /* make sure nominator is large enough */ |
587 | if (*nom < nom_min) { |
588 | if (*nom < nom_min) { |
588 | tmp = DIV_ROUND_UP(nom_min, *nom); |
589 | tmp = DIV_ROUND_UP(nom_min, *nom); |
589 | *nom *= tmp; |
590 | *nom *= tmp; |
590 | *den *= tmp; |
591 | *den *= tmp; |
591 | } |
592 | } |
592 | 593 | ||
593 | /* make sure the denominator is large enough */ |
594 | /* make sure the denominator is large enough */ |
594 | if (*den < den_min) { |
595 | if (*den < den_min) { |
595 | tmp = DIV_ROUND_UP(den_min, *den); |
596 | tmp = DIV_ROUND_UP(den_min, *den); |
596 | *nom *= tmp; |
597 | *nom *= tmp; |
597 | *den *= tmp; |
598 | *den *= tmp; |
598 | } |
599 | } |
599 | } |
600 | } |
600 | 601 | ||
601 | /** |
602 | /** |
602 | * avivo_get_fb_ref_div - feedback and ref divider calculation |
603 | * avivo_get_fb_ref_div - feedback and ref divider calculation |
603 | * |
604 | * |
604 | * @nom: nominator |
605 | * @nom: nominator |
605 | * @den: denominator |
606 | * @den: denominator |
606 | * @post_div: post divider |
607 | * @post_div: post divider |
607 | * @fb_div_max: feedback divider maximum |
608 | * @fb_div_max: feedback divider maximum |
608 | * @ref_div_max: reference divider maximum |
609 | * @ref_div_max: reference divider maximum |
609 | * @fb_div: resulting feedback divider |
610 | * @fb_div: resulting feedback divider |
610 | * @ref_div: resulting reference divider |
611 | * @ref_div: resulting reference divider |
611 | * |
612 | * |
612 | * Calculate feedback and reference divider for a given post divider. Makes |
613 | * Calculate feedback and reference divider for a given post divider. Makes |
613 | * sure we stay within the limits. |
614 | * sure we stay within the limits. |
614 | */ |
615 | */ |
615 | static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, |
616 | static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, |
616 | unsigned fb_div_max, unsigned ref_div_max, |
617 | unsigned fb_div_max, unsigned ref_div_max, |
617 | unsigned *fb_div, unsigned *ref_div) |
618 | unsigned *fb_div, unsigned *ref_div) |
618 | { |
619 | { |
619 | /* limit reference * post divider to a maximum */ |
620 | /* limit reference * post divider to a maximum */ |
620 | ref_div_max = max(min(100 / post_div, ref_div_max), 1u); |
621 | ref_div_max = max(min(100 / post_div, ref_div_max), 1u); |
621 | 622 | ||
622 | /* get matching reference and feedback divider */ |
623 | /* get matching reference and feedback divider */ |
623 | *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); |
624 | *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); |
624 | *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); |
625 | *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); |
625 | 626 | ||
626 | /* limit fb divider to its maximum */ |
627 | /* limit fb divider to its maximum */ |
627 | if (*fb_div > fb_div_max) { |
628 | if (*fb_div > fb_div_max) { |
628 | *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); |
629 | *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); |
629 | *fb_div = fb_div_max; |
630 | *fb_div = fb_div_max; |
630 | } |
631 | } |
631 | } |
632 | } |
632 | 633 | ||
633 | /** |
634 | /** |
634 | * radeon_compute_pll_avivo - compute PLL paramaters |
635 | * radeon_compute_pll_avivo - compute PLL paramaters |
635 | * |
636 | * |
636 | * @pll: information about the PLL |
637 | * @pll: information about the PLL |
637 | * @dot_clock_p: resulting pixel clock |
638 | * @dot_clock_p: resulting pixel clock |
638 | * fb_div_p: resulting feedback divider |
639 | * fb_div_p: resulting feedback divider |
639 | * frac_fb_div_p: fractional part of the feedback divider |
640 | * frac_fb_div_p: fractional part of the feedback divider |
640 | * ref_div_p: resulting reference divider |
641 | * ref_div_p: resulting reference divider |
641 | * post_div_p: resulting reference divider |
642 | * post_div_p: resulting reference divider |
642 | * |
643 | * |
643 | * Try to calculate the PLL parameters to generate the given frequency: |
644 | * Try to calculate the PLL parameters to generate the given frequency: |
644 | * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) |
645 | * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) |
645 | */ |
646 | */ |
646 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
647 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
647 | u32 freq, |
648 | u32 freq, |
648 | u32 *dot_clock_p, |
649 | u32 *dot_clock_p, |
649 | u32 *fb_div_p, |
650 | u32 *fb_div_p, |
650 | u32 *frac_fb_div_p, |
651 | u32 *frac_fb_div_p, |
651 | u32 *ref_div_p, |
652 | u32 *ref_div_p, |
652 | u32 *post_div_p) |
653 | u32 *post_div_p) |
653 | { |
654 | { |
654 | unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? |
655 | unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? |
655 | freq : freq / 10; |
656 | freq : freq / 10; |
656 | 657 | ||
657 | unsigned fb_div_min, fb_div_max, fb_div; |
658 | unsigned fb_div_min, fb_div_max, fb_div; |
658 | unsigned post_div_min, post_div_max, post_div; |
659 | unsigned post_div_min, post_div_max, post_div; |
659 | unsigned ref_div_min, ref_div_max, ref_div; |
660 | unsigned ref_div_min, ref_div_max, ref_div; |
660 | unsigned post_div_best, diff_best; |
661 | unsigned post_div_best, diff_best; |
661 | unsigned nom, den; |
662 | unsigned nom, den; |
662 | 663 | ||
663 | /* determine allowed feedback divider range */ |
664 | /* determine allowed feedback divider range */ |
664 | fb_div_min = pll->min_feedback_div; |
665 | fb_div_min = pll->min_feedback_div; |
665 | fb_div_max = pll->max_feedback_div; |
666 | fb_div_max = pll->max_feedback_div; |
666 | 667 | ||
667 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
668 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
668 | fb_div_min *= 10; |
669 | fb_div_min *= 10; |
669 | fb_div_max *= 10; |
670 | fb_div_max *= 10; |
670 | } |
671 | } |
671 | 672 | ||
672 | /* determine allowed ref divider range */ |
673 | /* determine allowed ref divider range */ |
673 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
674 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
674 | ref_div_min = pll->reference_div; |
675 | ref_div_min = pll->reference_div; |
675 | else |
676 | else |
676 | ref_div_min = pll->min_ref_div; |
677 | ref_div_min = pll->min_ref_div; |
677 | 678 | ||
678 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && |
679 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && |
679 | pll->flags & RADEON_PLL_USE_REF_DIV) |
680 | pll->flags & RADEON_PLL_USE_REF_DIV) |
680 | ref_div_max = pll->reference_div; |
681 | ref_div_max = pll->reference_div; |
681 | else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
682 | else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
682 | /* fix for problems on RS880 */ |
683 | /* fix for problems on RS880 */ |
683 | ref_div_max = min(pll->max_ref_div, 7u); |
684 | ref_div_max = min(pll->max_ref_div, 7u); |
684 | else |
685 | else |
685 | ref_div_max = pll->max_ref_div; |
686 | ref_div_max = pll->max_ref_div; |
686 | 687 | ||
687 | /* determine allowed post divider range */ |
688 | /* determine allowed post divider range */ |
688 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
689 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
689 | post_div_min = pll->post_div; |
690 | post_div_min = pll->post_div; |
690 | post_div_max = pll->post_div; |
691 | post_div_max = pll->post_div; |
691 | } else { |
692 | } else { |
692 | unsigned vco_min, vco_max; |
693 | unsigned vco_min, vco_max; |
693 | 694 | ||
694 | if (pll->flags & RADEON_PLL_IS_LCD) { |
695 | if (pll->flags & RADEON_PLL_IS_LCD) { |
695 | vco_min = pll->lcd_pll_out_min; |
696 | vco_min = pll->lcd_pll_out_min; |
696 | vco_max = pll->lcd_pll_out_max; |
697 | vco_max = pll->lcd_pll_out_max; |
697 | } else { |
698 | } else { |
698 | vco_min = pll->pll_out_min; |
699 | vco_min = pll->pll_out_min; |
699 | vco_max = pll->pll_out_max; |
700 | vco_max = pll->pll_out_max; |
700 | } |
701 | } |
701 | 702 | ||
702 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
703 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
703 | vco_min *= 10; |
704 | vco_min *= 10; |
704 | vco_max *= 10; |
705 | vco_max *= 10; |
705 | } |
706 | } |
706 | 707 | ||
707 | post_div_min = vco_min / target_clock; |
708 | post_div_min = vco_min / target_clock; |
708 | if ((target_clock * post_div_min) < vco_min) |
709 | if ((target_clock * post_div_min) < vco_min) |
709 | ++post_div_min; |
710 | ++post_div_min; |
710 | if (post_div_min < pll->min_post_div) |
711 | if (post_div_min < pll->min_post_div) |
711 | post_div_min = pll->min_post_div; |
712 | post_div_min = pll->min_post_div; |
712 | 713 | ||
713 | post_div_max = vco_max / target_clock; |
714 | post_div_max = vco_max / target_clock; |
714 | if ((target_clock * post_div_max) > vco_max) |
715 | if ((target_clock * post_div_max) > vco_max) |
715 | --post_div_max; |
716 | --post_div_max; |
716 | if (post_div_max > pll->max_post_div) |
717 | if (post_div_max > pll->max_post_div) |
717 | post_div_max = pll->max_post_div; |
718 | post_div_max = pll->max_post_div; |
718 | } |
719 | } |
719 | 720 | ||
720 | /* represent the searched ratio as fractional number */ |
721 | /* represent the searched ratio as fractional number */ |
721 | nom = target_clock; |
722 | nom = target_clock; |
722 | den = pll->reference_freq; |
723 | den = pll->reference_freq; |
723 | 724 | ||
724 | /* reduce the numbers to a simpler ratio */ |
725 | /* reduce the numbers to a simpler ratio */ |
725 | avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); |
726 | avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); |
726 | 727 | ||
727 | /* now search for a post divider */ |
728 | /* now search for a post divider */ |
728 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
729 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
729 | post_div_best = post_div_min; |
730 | post_div_best = post_div_min; |
730 | else |
731 | else |
731 | post_div_best = post_div_max; |
732 | post_div_best = post_div_max; |
732 | diff_best = ~0; |
733 | diff_best = ~0; |
733 | 734 | ||
734 | for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { |
735 | for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { |
735 | unsigned diff; |
736 | unsigned diff; |
736 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, |
737 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, |
737 | ref_div_max, &fb_div, &ref_div); |
738 | ref_div_max, &fb_div, &ref_div); |
738 | diff = abs(target_clock - (pll->reference_freq * fb_div) / |
739 | diff = abs(target_clock - (pll->reference_freq * fb_div) / |
739 | (ref_div * post_div)); |
740 | (ref_div * post_div)); |
740 | 741 | ||
741 | if (diff < diff_best || (diff == diff_best && |
742 | if (diff < diff_best || (diff == diff_best && |
742 | !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { |
743 | !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { |
743 | 744 | ||
744 | post_div_best = post_div; |
745 | post_div_best = post_div; |
745 | diff_best = diff; |
746 | diff_best = diff; |
746 | } |
747 | } |
747 | } |
748 | } |
748 | post_div = post_div_best; |
749 | post_div = post_div_best; |
749 | 750 | ||
750 | /* get the feedback and reference divider for the optimal value */ |
751 | /* get the feedback and reference divider for the optimal value */ |
751 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, |
752 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, |
752 | &fb_div, &ref_div); |
753 | &fb_div, &ref_div); |
753 | 754 | ||
754 | /* reduce the numbers to a simpler ratio once more */ |
755 | /* reduce the numbers to a simpler ratio once more */ |
755 | /* this also makes sure that the reference divider is large enough */ |
756 | /* this also makes sure that the reference divider is large enough */ |
756 | avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); |
757 | avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); |
757 | 758 | ||
758 | /* avoid high jitter with small fractional dividers */ |
759 | /* avoid high jitter with small fractional dividers */ |
759 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { |
760 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { |
760 | fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); |
761 | fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); |
761 | if (fb_div < fb_div_min) { |
762 | if (fb_div < fb_div_min) { |
762 | unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); |
763 | unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); |
763 | fb_div *= tmp; |
764 | fb_div *= tmp; |
764 | ref_div *= tmp; |
765 | ref_div *= tmp; |
765 | } |
766 | } |
766 | } |
767 | } |
767 | 768 | ||
768 | /* and finally save the result */ |
769 | /* and finally save the result */ |
769 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
770 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
770 | *fb_div_p = fb_div / 10; |
771 | *fb_div_p = fb_div / 10; |
771 | *frac_fb_div_p = fb_div % 10; |
772 | *frac_fb_div_p = fb_div % 10; |
772 | } else { |
773 | } else { |
773 | *fb_div_p = fb_div; |
774 | *fb_div_p = fb_div; |
774 | *frac_fb_div_p = 0; |
775 | *frac_fb_div_p = 0; |
775 | } |
776 | } |
776 | 777 | ||
777 | *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + |
778 | *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + |
778 | (pll->reference_freq * *frac_fb_div_p)) / |
779 | (pll->reference_freq * *frac_fb_div_p)) / |
779 | (ref_div * post_div * 10); |
780 | (ref_div * post_div * 10); |
780 | *ref_div_p = ref_div; |
781 | *ref_div_p = ref_div; |
781 | *post_div_p = post_div; |
782 | *post_div_p = post_div; |
782 | 783 | ||
783 | DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
784 | DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
784 | freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, |
785 | freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, |
785 | ref_div, post_div); |
786 | ref_div, post_div); |
786 | } |
787 | } |
787 | 788 | ||
788 | /* pre-avivo */ |
789 | /* pre-avivo */ |
789 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
790 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
790 | { |
791 | { |
791 | uint64_t mod; |
792 | uint64_t mod; |
792 | 793 | ||
793 | n += d / 2; |
794 | n += d / 2; |
794 | 795 | ||
795 | mod = do_div(n, d); |
796 | mod = do_div(n, d); |
796 | return n; |
797 | return n; |
797 | } |
798 | } |
798 | 799 | ||
799 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
800 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
800 | uint64_t freq, |
801 | uint64_t freq, |
801 | uint32_t *dot_clock_p, |
802 | uint32_t *dot_clock_p, |
802 | uint32_t *fb_div_p, |
803 | uint32_t *fb_div_p, |
803 | uint32_t *frac_fb_div_p, |
804 | uint32_t *frac_fb_div_p, |
804 | uint32_t *ref_div_p, |
805 | uint32_t *ref_div_p, |
805 | uint32_t *post_div_p) |
806 | uint32_t *post_div_p) |
806 | { |
807 | { |
807 | uint32_t min_ref_div = pll->min_ref_div; |
808 | uint32_t min_ref_div = pll->min_ref_div; |
808 | uint32_t max_ref_div = pll->max_ref_div; |
809 | uint32_t max_ref_div = pll->max_ref_div; |
809 | uint32_t min_post_div = pll->min_post_div; |
810 | uint32_t min_post_div = pll->min_post_div; |
810 | uint32_t max_post_div = pll->max_post_div; |
811 | uint32_t max_post_div = pll->max_post_div; |
811 | uint32_t min_fractional_feed_div = 0; |
812 | uint32_t min_fractional_feed_div = 0; |
812 | uint32_t max_fractional_feed_div = 0; |
813 | uint32_t max_fractional_feed_div = 0; |
813 | uint32_t best_vco = pll->best_vco; |
814 | uint32_t best_vco = pll->best_vco; |
814 | uint32_t best_post_div = 1; |
815 | uint32_t best_post_div = 1; |
815 | uint32_t best_ref_div = 1; |
816 | uint32_t best_ref_div = 1; |
816 | uint32_t best_feedback_div = 1; |
817 | uint32_t best_feedback_div = 1; |
817 | uint32_t best_frac_feedback_div = 0; |
818 | uint32_t best_frac_feedback_div = 0; |
818 | uint32_t best_freq = -1; |
819 | uint32_t best_freq = -1; |
819 | uint32_t best_error = 0xffffffff; |
820 | uint32_t best_error = 0xffffffff; |
820 | uint32_t best_vco_diff = 1; |
821 | uint32_t best_vco_diff = 1; |
821 | uint32_t post_div; |
822 | uint32_t post_div; |
822 | u32 pll_out_min, pll_out_max; |
823 | u32 pll_out_min, pll_out_max; |
823 | 824 | ||
824 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
825 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
825 | freq = freq * 1000; |
826 | freq = freq * 1000; |
826 | 827 | ||
827 | if (pll->flags & RADEON_PLL_IS_LCD) { |
828 | if (pll->flags & RADEON_PLL_IS_LCD) { |
828 | pll_out_min = pll->lcd_pll_out_min; |
829 | pll_out_min = pll->lcd_pll_out_min; |
829 | pll_out_max = pll->lcd_pll_out_max; |
830 | pll_out_max = pll->lcd_pll_out_max; |
830 | } else { |
831 | } else { |
831 | pll_out_min = pll->pll_out_min; |
832 | pll_out_min = pll->pll_out_min; |
832 | pll_out_max = pll->pll_out_max; |
833 | pll_out_max = pll->pll_out_max; |
833 | } |
834 | } |
834 | 835 | ||
835 | if (pll_out_min > 64800) |
836 | if (pll_out_min > 64800) |
836 | pll_out_min = 64800; |
837 | pll_out_min = 64800; |
837 | 838 | ||
838 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
839 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
839 | min_ref_div = max_ref_div = pll->reference_div; |
840 | min_ref_div = max_ref_div = pll->reference_div; |
840 | else { |
841 | else { |
841 | while (min_ref_div < max_ref_div-1) { |
842 | while (min_ref_div < max_ref_div-1) { |
842 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
843 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
843 | uint32_t pll_in = pll->reference_freq / mid; |
844 | uint32_t pll_in = pll->reference_freq / mid; |
844 | if (pll_in < pll->pll_in_min) |
845 | if (pll_in < pll->pll_in_min) |
845 | max_ref_div = mid; |
846 | max_ref_div = mid; |
846 | else if (pll_in > pll->pll_in_max) |
847 | else if (pll_in > pll->pll_in_max) |
847 | min_ref_div = mid; |
848 | min_ref_div = mid; |
848 | else |
849 | else |
849 | break; |
850 | break; |
850 | } |
851 | } |
851 | } |
852 | } |
852 | 853 | ||
853 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
854 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
854 | min_post_div = max_post_div = pll->post_div; |
855 | min_post_div = max_post_div = pll->post_div; |
855 | 856 | ||
856 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
857 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
857 | min_fractional_feed_div = pll->min_frac_feedback_div; |
858 | min_fractional_feed_div = pll->min_frac_feedback_div; |
858 | max_fractional_feed_div = pll->max_frac_feedback_div; |
859 | max_fractional_feed_div = pll->max_frac_feedback_div; |
859 | } |
860 | } |
860 | 861 | ||
861 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
862 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
862 | uint32_t ref_div; |
863 | uint32_t ref_div; |
863 | 864 | ||
864 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
865 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
865 | continue; |
866 | continue; |
866 | 867 | ||
867 | /* legacy radeons only have a few post_divs */ |
868 | /* legacy radeons only have a few post_divs */ |
868 | if (pll->flags & RADEON_PLL_LEGACY) { |
869 | if (pll->flags & RADEON_PLL_LEGACY) { |
869 | if ((post_div == 5) || |
870 | if ((post_div == 5) || |
870 | (post_div == 7) || |
871 | (post_div == 7) || |
871 | (post_div == 9) || |
872 | (post_div == 9) || |
872 | (post_div == 10) || |
873 | (post_div == 10) || |
873 | (post_div == 11) || |
874 | (post_div == 11) || |
874 | (post_div == 13) || |
875 | (post_div == 13) || |
875 | (post_div == 14) || |
876 | (post_div == 14) || |
876 | (post_div == 15)) |
877 | (post_div == 15)) |
877 | continue; |
878 | continue; |
878 | } |
879 | } |
879 | 880 | ||
880 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
881 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
881 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
882 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
882 | uint32_t pll_in = pll->reference_freq / ref_div; |
883 | uint32_t pll_in = pll->reference_freq / ref_div; |
883 | uint32_t min_feed_div = pll->min_feedback_div; |
884 | uint32_t min_feed_div = pll->min_feedback_div; |
884 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
885 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
885 | 886 | ||
886 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
887 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
887 | continue; |
888 | continue; |
888 | 889 | ||
889 | while (min_feed_div < max_feed_div) { |
890 | while (min_feed_div < max_feed_div) { |
890 | uint32_t vco; |
891 | uint32_t vco; |
891 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
892 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
892 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
893 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
893 | uint32_t frac_feedback_div; |
894 | uint32_t frac_feedback_div; |
894 | uint64_t tmp; |
895 | uint64_t tmp; |
895 | 896 | ||
896 | feedback_div = (min_feed_div + max_feed_div) / 2; |
897 | feedback_div = (min_feed_div + max_feed_div) / 2; |
897 | 898 | ||
898 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
899 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
899 | vco = radeon_div(tmp, ref_div); |
900 | vco = radeon_div(tmp, ref_div); |
900 | 901 | ||
901 | if (vco < pll_out_min) { |
902 | if (vco < pll_out_min) { |
902 | min_feed_div = feedback_div + 1; |
903 | min_feed_div = feedback_div + 1; |
903 | continue; |
904 | continue; |
904 | } else if (vco > pll_out_max) { |
905 | } else if (vco > pll_out_max) { |
905 | max_feed_div = feedback_div; |
906 | max_feed_div = feedback_div; |
906 | continue; |
907 | continue; |
907 | } |
908 | } |
908 | 909 | ||
909 | while (min_frac_feed_div < max_frac_feed_div) { |
910 | while (min_frac_feed_div < max_frac_feed_div) { |
910 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
911 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
911 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
912 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
912 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
913 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
913 | current_freq = radeon_div(tmp, ref_div * post_div); |
914 | current_freq = radeon_div(tmp, ref_div * post_div); |
914 | 915 | ||
915 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
916 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
916 | if (freq < current_freq) |
917 | if (freq < current_freq) |
917 | error = 0xffffffff; |
918 | error = 0xffffffff; |
918 | else |
919 | else |
919 | error = freq - current_freq; |
920 | error = freq - current_freq; |
920 | } else |
921 | } else |
921 | error = abs(current_freq - freq); |
922 | error = abs(current_freq - freq); |
922 | vco_diff = abs(vco - best_vco); |
923 | vco_diff = abs(vco - best_vco); |
923 | 924 | ||
924 | if ((best_vco == 0 && error < best_error) || |
925 | if ((best_vco == 0 && error < best_error) || |
925 | (best_vco != 0 && |
926 | (best_vco != 0 && |
926 | ((best_error > 100 && error < best_error - 100) || |
927 | ((best_error > 100 && error < best_error - 100) || |
927 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
928 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
928 | best_post_div = post_div; |
929 | best_post_div = post_div; |
929 | best_ref_div = ref_div; |
930 | best_ref_div = ref_div; |
930 | best_feedback_div = feedback_div; |
931 | best_feedback_div = feedback_div; |
931 | best_frac_feedback_div = frac_feedback_div; |
932 | best_frac_feedback_div = frac_feedback_div; |
932 | best_freq = current_freq; |
933 | best_freq = current_freq; |
933 | best_error = error; |
934 | best_error = error; |
934 | best_vco_diff = vco_diff; |
935 | best_vco_diff = vco_diff; |
935 | } else if (current_freq == freq) { |
936 | } else if (current_freq == freq) { |
936 | if (best_freq == -1) { |
937 | if (best_freq == -1) { |
937 | best_post_div = post_div; |
938 | best_post_div = post_div; |
938 | best_ref_div = ref_div; |
939 | best_ref_div = ref_div; |
939 | best_feedback_div = feedback_div; |
940 | best_feedback_div = feedback_div; |
940 | best_frac_feedback_div = frac_feedback_div; |
941 | best_frac_feedback_div = frac_feedback_div; |
941 | best_freq = current_freq; |
942 | best_freq = current_freq; |
942 | best_error = error; |
943 | best_error = error; |
943 | best_vco_diff = vco_diff; |
944 | best_vco_diff = vco_diff; |
944 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
945 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
945 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
946 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
946 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
947 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
947 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
948 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
948 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
949 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
949 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
950 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
950 | best_post_div = post_div; |
951 | best_post_div = post_div; |
951 | best_ref_div = ref_div; |
952 | best_ref_div = ref_div; |
952 | best_feedback_div = feedback_div; |
953 | best_feedback_div = feedback_div; |
953 | best_frac_feedback_div = frac_feedback_div; |
954 | best_frac_feedback_div = frac_feedback_div; |
954 | best_freq = current_freq; |
955 | best_freq = current_freq; |
955 | best_error = error; |
956 | best_error = error; |
956 | best_vco_diff = vco_diff; |
957 | best_vco_diff = vco_diff; |
957 | } |
958 | } |
958 | } |
959 | } |
959 | if (current_freq < freq) |
960 | if (current_freq < freq) |
960 | min_frac_feed_div = frac_feedback_div + 1; |
961 | min_frac_feed_div = frac_feedback_div + 1; |
961 | else |
962 | else |
962 | max_frac_feed_div = frac_feedback_div; |
963 | max_frac_feed_div = frac_feedback_div; |
963 | } |
964 | } |
964 | if (current_freq < freq) |
965 | if (current_freq < freq) |
965 | min_feed_div = feedback_div + 1; |
966 | min_feed_div = feedback_div + 1; |
966 | else |
967 | else |
967 | max_feed_div = feedback_div; |
968 | max_feed_div = feedback_div; |
968 | } |
969 | } |
969 | } |
970 | } |
970 | } |
971 | } |
971 | 972 | ||
972 | *dot_clock_p = best_freq / 10000; |
973 | *dot_clock_p = best_freq / 10000; |
973 | *fb_div_p = best_feedback_div; |
974 | *fb_div_p = best_feedback_div; |
974 | *frac_fb_div_p = best_frac_feedback_div; |
975 | *frac_fb_div_p = best_frac_feedback_div; |
975 | *ref_div_p = best_ref_div; |
976 | *ref_div_p = best_ref_div; |
976 | *post_div_p = best_post_div; |
977 | *post_div_p = best_post_div; |
977 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
978 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
978 | (long long)freq, |
979 | (long long)freq, |
979 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
980 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
980 | best_ref_div, best_post_div); |
981 | best_ref_div, best_post_div); |
981 | 982 | ||
982 | } |
983 | } |
983 | 984 | ||
984 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
985 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
985 | { |
986 | { |
986 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
987 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
987 | 988 | ||
988 | if (radeon_fb->obj) { |
989 | if (radeon_fb->obj) { |
989 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
990 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
990 | } |
991 | } |
991 | drm_framebuffer_cleanup(fb); |
992 | drm_framebuffer_cleanup(fb); |
992 | kfree(radeon_fb); |
993 | kfree(radeon_fb); |
993 | } |
994 | } |
994 | 995 | ||
995 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
996 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
996 | struct drm_file *file_priv, |
997 | struct drm_file *file_priv, |
997 | unsigned int *handle) |
998 | unsigned int *handle) |
998 | { |
999 | { |
999 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
1000 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
1000 | 1001 | ||
1001 | return 0; |
1002 | return 0; |
1002 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
1003 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
1003 | } |
1004 | } |
1004 | 1005 | ||
1005 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
1006 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
1006 | .destroy = radeon_user_framebuffer_destroy, |
1007 | .destroy = radeon_user_framebuffer_destroy, |
1007 | .create_handle = radeon_user_framebuffer_create_handle, |
1008 | .create_handle = radeon_user_framebuffer_create_handle, |
1008 | }; |
1009 | }; |
1009 | 1010 | ||
1010 | int |
1011 | int |
1011 | radeon_framebuffer_init(struct drm_device *dev, |
1012 | radeon_framebuffer_init(struct drm_device *dev, |
1012 | struct radeon_framebuffer *rfb, |
1013 | struct radeon_framebuffer *rfb, |
1013 | const struct drm_mode_fb_cmd2 *mode_cmd, |
1014 | const struct drm_mode_fb_cmd2 *mode_cmd, |
1014 | struct drm_gem_object *obj) |
1015 | struct drm_gem_object *obj) |
1015 | { |
1016 | { |
1016 | int ret; |
1017 | int ret; |
1017 | rfb->obj = obj; |
1018 | rfb->obj = obj; |
1018 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
1019 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
1019 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
1020 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
1020 | if (ret) { |
1021 | if (ret) { |
1021 | rfb->obj = NULL; |
1022 | rfb->obj = NULL; |
1022 | return ret; |
1023 | return ret; |
1023 | } |
1024 | } |
1024 | return 0; |
1025 | return 0; |
1025 | } |
1026 | } |
1026 | 1027 | ||
1027 | 1028 | ||
1028 | 1029 | ||
1029 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1030 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
1030 | // .fb_create = radeon_user_framebuffer_create, |
1031 | // .fb_create = radeon_user_framebuffer_create, |
1031 | // .output_poll_changed = radeon_output_poll_changed |
1032 | // .output_poll_changed = radeon_output_poll_changed |
1032 | }; |
1033 | }; |
1033 | 1034 | ||
1034 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
1035 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
1035 | { { 0, "driver" }, |
1036 | { { 0, "driver" }, |
1036 | { 1, "bios" }, |
1037 | { 1, "bios" }, |
1037 | }; |
1038 | }; |
1038 | 1039 | ||
1039 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
1040 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
1040 | { { TV_STD_NTSC, "ntsc" }, |
1041 | { { TV_STD_NTSC, "ntsc" }, |
1041 | { TV_STD_PAL, "pal" }, |
1042 | { TV_STD_PAL, "pal" }, |
1042 | { TV_STD_PAL_M, "pal-m" }, |
1043 | { TV_STD_PAL_M, "pal-m" }, |
1043 | { TV_STD_PAL_60, "pal-60" }, |
1044 | { TV_STD_PAL_60, "pal-60" }, |
1044 | { TV_STD_NTSC_J, "ntsc-j" }, |
1045 | { TV_STD_NTSC_J, "ntsc-j" }, |
1045 | { TV_STD_SCART_PAL, "scart-pal" }, |
1046 | { TV_STD_SCART_PAL, "scart-pal" }, |
1046 | { TV_STD_PAL_CN, "pal-cn" }, |
1047 | { TV_STD_PAL_CN, "pal-cn" }, |
1047 | { TV_STD_SECAM, "secam" }, |
1048 | { TV_STD_SECAM, "secam" }, |
1048 | }; |
1049 | }; |
1049 | 1050 | ||
1050 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1051 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1051 | { { UNDERSCAN_OFF, "off" }, |
1052 | { { UNDERSCAN_OFF, "off" }, |
1052 | { UNDERSCAN_ON, "on" }, |
1053 | { UNDERSCAN_ON, "on" }, |
1053 | { UNDERSCAN_AUTO, "auto" }, |
1054 | { UNDERSCAN_AUTO, "auto" }, |
1054 | }; |
1055 | }; |
1055 | 1056 | ||
1056 | static struct drm_prop_enum_list radeon_audio_enum_list[] = |
1057 | static struct drm_prop_enum_list radeon_audio_enum_list[] = |
1057 | { { RADEON_AUDIO_DISABLE, "off" }, |
1058 | { { RADEON_AUDIO_DISABLE, "off" }, |
1058 | { RADEON_AUDIO_ENABLE, "on" }, |
1059 | { RADEON_AUDIO_ENABLE, "on" }, |
1059 | { RADEON_AUDIO_AUTO, "auto" }, |
1060 | { RADEON_AUDIO_AUTO, "auto" }, |
1060 | }; |
1061 | }; |
1061 | 1062 | ||
1062 | /* XXX support different dither options? spatial, temporal, both, etc. */ |
1063 | /* XXX support different dither options? spatial, temporal, both, etc. */ |
1063 | static struct drm_prop_enum_list radeon_dither_enum_list[] = |
1064 | static struct drm_prop_enum_list radeon_dither_enum_list[] = |
1064 | { { RADEON_FMT_DITHER_DISABLE, "off" }, |
1065 | { { RADEON_FMT_DITHER_DISABLE, "off" }, |
1065 | { RADEON_FMT_DITHER_ENABLE, "on" }, |
1066 | { RADEON_FMT_DITHER_ENABLE, "on" }, |
1066 | }; |
1067 | }; |
1067 | 1068 | ||
1068 | static struct drm_prop_enum_list radeon_output_csc_enum_list[] = |
1069 | static struct drm_prop_enum_list radeon_output_csc_enum_list[] = |
1069 | { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, |
1070 | { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, |
1070 | { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, |
1071 | { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, |
1071 | { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, |
1072 | { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, |
1072 | { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, |
1073 | { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, |
1073 | }; |
1074 | }; |
1074 | 1075 | ||
1075 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
1076 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
1076 | { |
1077 | { |
1077 | int sz; |
1078 | int sz; |
1078 | 1079 | ||
1079 | if (rdev->is_atom_bios) { |
1080 | if (rdev->is_atom_bios) { |
1080 | rdev->mode_info.coherent_mode_property = |
1081 | rdev->mode_info.coherent_mode_property = |
1081 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
1082 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
1082 | if (!rdev->mode_info.coherent_mode_property) |
1083 | if (!rdev->mode_info.coherent_mode_property) |
1083 | return -ENOMEM; |
1084 | return -ENOMEM; |
1084 | } |
1085 | } |
1085 | 1086 | ||
1086 | if (!ASIC_IS_AVIVO(rdev)) { |
1087 | if (!ASIC_IS_AVIVO(rdev)) { |
1087 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
1088 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
1088 | rdev->mode_info.tmds_pll_property = |
1089 | rdev->mode_info.tmds_pll_property = |
1089 | drm_property_create_enum(rdev->ddev, 0, |
1090 | drm_property_create_enum(rdev->ddev, 0, |
1090 | "tmds_pll", |
1091 | "tmds_pll", |
1091 | radeon_tmds_pll_enum_list, sz); |
1092 | radeon_tmds_pll_enum_list, sz); |
1092 | } |
1093 | } |
1093 | 1094 | ||
1094 | rdev->mode_info.load_detect_property = |
1095 | rdev->mode_info.load_detect_property = |
1095 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
1096 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
1096 | if (!rdev->mode_info.load_detect_property) |
1097 | if (!rdev->mode_info.load_detect_property) |
1097 | return -ENOMEM; |
1098 | return -ENOMEM; |
1098 | 1099 | ||
1099 | drm_mode_create_scaling_mode_property(rdev->ddev); |
1100 | drm_mode_create_scaling_mode_property(rdev->ddev); |
1100 | 1101 | ||
1101 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
1102 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
1102 | rdev->mode_info.tv_std_property = |
1103 | rdev->mode_info.tv_std_property = |
1103 | drm_property_create_enum(rdev->ddev, 0, |
1104 | drm_property_create_enum(rdev->ddev, 0, |
1104 | "tv standard", |
1105 | "tv standard", |
1105 | radeon_tv_std_enum_list, sz); |
1106 | radeon_tv_std_enum_list, sz); |
1106 | 1107 | ||
1107 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1108 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1108 | rdev->mode_info.underscan_property = |
1109 | rdev->mode_info.underscan_property = |
1109 | drm_property_create_enum(rdev->ddev, 0, |
1110 | drm_property_create_enum(rdev->ddev, 0, |
1110 | "underscan", |
1111 | "underscan", |
1111 | radeon_underscan_enum_list, sz); |
1112 | radeon_underscan_enum_list, sz); |
1112 | 1113 | ||
1113 | rdev->mode_info.underscan_hborder_property = |
1114 | rdev->mode_info.underscan_hborder_property = |
1114 | drm_property_create_range(rdev->ddev, 0, |
1115 | drm_property_create_range(rdev->ddev, 0, |
1115 | "underscan hborder", 0, 128); |
1116 | "underscan hborder", 0, 128); |
1116 | if (!rdev->mode_info.underscan_hborder_property) |
1117 | if (!rdev->mode_info.underscan_hborder_property) |
1117 | return -ENOMEM; |
1118 | return -ENOMEM; |
1118 | 1119 | ||
1119 | rdev->mode_info.underscan_vborder_property = |
1120 | rdev->mode_info.underscan_vborder_property = |
1120 | drm_property_create_range(rdev->ddev, 0, |
1121 | drm_property_create_range(rdev->ddev, 0, |
1121 | "underscan vborder", 0, 128); |
1122 | "underscan vborder", 0, 128); |
1122 | if (!rdev->mode_info.underscan_vborder_property) |
1123 | if (!rdev->mode_info.underscan_vborder_property) |
1123 | return -ENOMEM; |
1124 | return -ENOMEM; |
1124 | 1125 | ||
1125 | sz = ARRAY_SIZE(radeon_audio_enum_list); |
1126 | sz = ARRAY_SIZE(radeon_audio_enum_list); |
1126 | rdev->mode_info.audio_property = |
1127 | rdev->mode_info.audio_property = |
1127 | drm_property_create_enum(rdev->ddev, 0, |
1128 | drm_property_create_enum(rdev->ddev, 0, |
1128 | "audio", |
1129 | "audio", |
1129 | radeon_audio_enum_list, sz); |
1130 | radeon_audio_enum_list, sz); |
1130 | 1131 | ||
1131 | sz = ARRAY_SIZE(radeon_dither_enum_list); |
1132 | sz = ARRAY_SIZE(radeon_dither_enum_list); |
1132 | rdev->mode_info.dither_property = |
1133 | rdev->mode_info.dither_property = |
1133 | drm_property_create_enum(rdev->ddev, 0, |
1134 | drm_property_create_enum(rdev->ddev, 0, |
1134 | "dither", |
1135 | "dither", |
1135 | radeon_dither_enum_list, sz); |
1136 | radeon_dither_enum_list, sz); |
1136 | 1137 | ||
1137 | sz = ARRAY_SIZE(radeon_output_csc_enum_list); |
1138 | sz = ARRAY_SIZE(radeon_output_csc_enum_list); |
1138 | rdev->mode_info.output_csc_property = |
1139 | rdev->mode_info.output_csc_property = |
1139 | drm_property_create_enum(rdev->ddev, 0, |
1140 | drm_property_create_enum(rdev->ddev, 0, |
1140 | "output_csc", |
1141 | "output_csc", |
1141 | radeon_output_csc_enum_list, sz); |
1142 | radeon_output_csc_enum_list, sz); |
1142 | 1143 | ||
1143 | return 0; |
1144 | return 0; |
1144 | } |
1145 | } |
1145 | 1146 | ||
1146 | void radeon_update_display_priority(struct radeon_device *rdev) |
1147 | void radeon_update_display_priority(struct radeon_device *rdev) |
1147 | { |
1148 | { |
1148 | /* adjustment options for the display watermarks */ |
1149 | /* adjustment options for the display watermarks */ |
1149 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
1150 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
1150 | /* set display priority to high for r3xx, rv515 chips |
1151 | /* set display priority to high for r3xx, rv515 chips |
1151 | * this avoids flickering due to underflow to the |
1152 | * this avoids flickering due to underflow to the |
1152 | * display controllers during heavy acceleration. |
1153 | * display controllers during heavy acceleration. |
1153 | * Don't force high on rs4xx igp chips as it seems to |
1154 | * Don't force high on rs4xx igp chips as it seems to |
1154 | * affect the sound card. See kernel bug 15982. |
1155 | * affect the sound card. See kernel bug 15982. |
1155 | */ |
1156 | */ |
1156 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1157 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1157 | !(rdev->flags & RADEON_IS_IGP)) |
1158 | !(rdev->flags & RADEON_IS_IGP)) |
1158 | rdev->disp_priority = 2; |
1159 | rdev->disp_priority = 2; |
1159 | else |
1160 | else |
1160 | rdev->disp_priority = 0; |
1161 | rdev->disp_priority = 0; |
1161 | } else |
1162 | } else |
1162 | rdev->disp_priority = radeon_disp_priority; |
1163 | rdev->disp_priority = radeon_disp_priority; |
1163 | 1164 | ||
1164 | } |
1165 | } |
1165 | 1166 | ||
1166 | /* |
1167 | /* |
1167 | * Allocate hdmi structs and determine register offsets |
1168 | * Allocate hdmi structs and determine register offsets |
1168 | */ |
1169 | */ |
1169 | static void radeon_afmt_init(struct radeon_device *rdev) |
1170 | static void radeon_afmt_init(struct radeon_device *rdev) |
1170 | { |
1171 | { |
1171 | int i; |
1172 | int i; |
1172 | 1173 | ||
1173 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) |
1174 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) |
1174 | rdev->mode_info.afmt[i] = NULL; |
1175 | rdev->mode_info.afmt[i] = NULL; |
1175 | 1176 | ||
1176 | if (ASIC_IS_NODCE(rdev)) { |
1177 | if (ASIC_IS_NODCE(rdev)) { |
1177 | /* nothing to do */ |
1178 | /* nothing to do */ |
1178 | } else if (ASIC_IS_DCE4(rdev)) { |
1179 | } else if (ASIC_IS_DCE4(rdev)) { |
1179 | static uint32_t eg_offsets[] = { |
1180 | static uint32_t eg_offsets[] = { |
1180 | EVERGREEN_CRTC0_REGISTER_OFFSET, |
1181 | EVERGREEN_CRTC0_REGISTER_OFFSET, |
1181 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
1182 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
1182 | EVERGREEN_CRTC2_REGISTER_OFFSET, |
1183 | EVERGREEN_CRTC2_REGISTER_OFFSET, |
1183 | EVERGREEN_CRTC3_REGISTER_OFFSET, |
1184 | EVERGREEN_CRTC3_REGISTER_OFFSET, |
1184 | EVERGREEN_CRTC4_REGISTER_OFFSET, |
1185 | EVERGREEN_CRTC4_REGISTER_OFFSET, |
1185 | EVERGREEN_CRTC5_REGISTER_OFFSET, |
1186 | EVERGREEN_CRTC5_REGISTER_OFFSET, |
1186 | 0x13830 - 0x7030, |
1187 | 0x13830 - 0x7030, |
1187 | }; |
1188 | }; |
1188 | int num_afmt; |
1189 | int num_afmt; |
1189 | 1190 | ||
1190 | /* DCE8 has 7 audio blocks tied to DIG encoders */ |
1191 | /* DCE8 has 7 audio blocks tied to DIG encoders */ |
1191 | /* DCE6 has 6 audio blocks tied to DIG encoders */ |
1192 | /* DCE6 has 6 audio blocks tied to DIG encoders */ |
1192 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ |
1193 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ |
1193 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ |
1194 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ |
1194 | if (ASIC_IS_DCE8(rdev)) |
1195 | if (ASIC_IS_DCE8(rdev)) |
1195 | num_afmt = 7; |
1196 | num_afmt = 7; |
1196 | else if (ASIC_IS_DCE6(rdev)) |
1197 | else if (ASIC_IS_DCE6(rdev)) |
1197 | num_afmt = 6; |
1198 | num_afmt = 6; |
1198 | else if (ASIC_IS_DCE5(rdev)) |
1199 | else if (ASIC_IS_DCE5(rdev)) |
1199 | num_afmt = 6; |
1200 | num_afmt = 6; |
1200 | else if (ASIC_IS_DCE41(rdev)) |
1201 | else if (ASIC_IS_DCE41(rdev)) |
1201 | num_afmt = 2; |
1202 | num_afmt = 2; |
1202 | else /* DCE4 */ |
1203 | else /* DCE4 */ |
1203 | num_afmt = 6; |
1204 | num_afmt = 6; |
1204 | 1205 | ||
1205 | BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); |
1206 | BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); |
1206 | for (i = 0; i < num_afmt; i++) { |
1207 | for (i = 0; i < num_afmt; i++) { |
1207 | rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1208 | rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1208 | if (rdev->mode_info.afmt[i]) { |
1209 | if (rdev->mode_info.afmt[i]) { |
1209 | rdev->mode_info.afmt[i]->offset = eg_offsets[i]; |
1210 | rdev->mode_info.afmt[i]->offset = eg_offsets[i]; |
1210 | rdev->mode_info.afmt[i]->id = i; |
1211 | rdev->mode_info.afmt[i]->id = i; |
1211 | } |
1212 | } |
1212 | } |
1213 | } |
1213 | } else if (ASIC_IS_DCE3(rdev)) { |
1214 | } else if (ASIC_IS_DCE3(rdev)) { |
1214 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ |
1215 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ |
1215 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1216 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1216 | if (rdev->mode_info.afmt[0]) { |
1217 | if (rdev->mode_info.afmt[0]) { |
1217 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; |
1218 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; |
1218 | rdev->mode_info.afmt[0]->id = 0; |
1219 | rdev->mode_info.afmt[0]->id = 0; |
1219 | } |
1220 | } |
1220 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1221 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1221 | if (rdev->mode_info.afmt[1]) { |
1222 | if (rdev->mode_info.afmt[1]) { |
1222 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; |
1223 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; |
1223 | rdev->mode_info.afmt[1]->id = 1; |
1224 | rdev->mode_info.afmt[1]->id = 1; |
1224 | } |
1225 | } |
1225 | } else if (ASIC_IS_DCE2(rdev)) { |
1226 | } else if (ASIC_IS_DCE2(rdev)) { |
1226 | /* DCE2 has at least 1 routable audio block */ |
1227 | /* DCE2 has at least 1 routable audio block */ |
1227 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1228 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1228 | if (rdev->mode_info.afmt[0]) { |
1229 | if (rdev->mode_info.afmt[0]) { |
1229 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; |
1230 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; |
1230 | rdev->mode_info.afmt[0]->id = 0; |
1231 | rdev->mode_info.afmt[0]->id = 0; |
1231 | } |
1232 | } |
1232 | /* r6xx has 2 routable audio blocks */ |
1233 | /* r6xx has 2 routable audio blocks */ |
1233 | if (rdev->family >= CHIP_R600) { |
1234 | if (rdev->family >= CHIP_R600) { |
1234 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1235 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
1235 | if (rdev->mode_info.afmt[1]) { |
1236 | if (rdev->mode_info.afmt[1]) { |
1236 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; |
1237 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; |
1237 | rdev->mode_info.afmt[1]->id = 1; |
1238 | rdev->mode_info.afmt[1]->id = 1; |
1238 | } |
1239 | } |
1239 | } |
1240 | } |
1240 | } |
1241 | } |
1241 | } |
1242 | } |
1242 | 1243 | ||
1243 | static void radeon_afmt_fini(struct radeon_device *rdev) |
1244 | static void radeon_afmt_fini(struct radeon_device *rdev) |
1244 | { |
1245 | { |
1245 | int i; |
1246 | int i; |
1246 | 1247 | ||
1247 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { |
1248 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { |
1248 | kfree(rdev->mode_info.afmt[i]); |
1249 | kfree(rdev->mode_info.afmt[i]); |
1249 | rdev->mode_info.afmt[i] = NULL; |
1250 | rdev->mode_info.afmt[i] = NULL; |
1250 | } |
1251 | } |
1251 | } |
1252 | } |
1252 | 1253 | ||
1253 | int radeon_modeset_init(struct radeon_device *rdev) |
1254 | int radeon_modeset_init(struct radeon_device *rdev) |
1254 | { |
1255 | { |
1255 | int i; |
1256 | int i; |
1256 | int ret; |
1257 | int ret; |
1257 | 1258 | ||
1258 | ENTER(); |
1259 | ENTER(); |
1259 | 1260 | ||
1260 | drm_mode_config_init(rdev->ddev); |
1261 | drm_mode_config_init(rdev->ddev); |
1261 | rdev->mode_info.mode_config_initialized = true; |
1262 | rdev->mode_info.mode_config_initialized = true; |
1262 | 1263 | ||
1263 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
1264 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
1264 | 1265 | ||
1265 | if (ASIC_IS_DCE5(rdev)) { |
1266 | if (ASIC_IS_DCE5(rdev)) { |
1266 | rdev->ddev->mode_config.max_width = 16384; |
1267 | rdev->ddev->mode_config.max_width = 16384; |
1267 | rdev->ddev->mode_config.max_height = 16384; |
1268 | rdev->ddev->mode_config.max_height = 16384; |
1268 | } else if (ASIC_IS_AVIVO(rdev)) { |
1269 | } else if (ASIC_IS_AVIVO(rdev)) { |
1269 | rdev->ddev->mode_config.max_width = 8192; |
1270 | rdev->ddev->mode_config.max_width = 8192; |
1270 | rdev->ddev->mode_config.max_height = 8192; |
1271 | rdev->ddev->mode_config.max_height = 8192; |
1271 | } else { |
1272 | } else { |
1272 | rdev->ddev->mode_config.max_width = 4096; |
1273 | rdev->ddev->mode_config.max_width = 4096; |
1273 | rdev->ddev->mode_config.max_height = 4096; |
1274 | rdev->ddev->mode_config.max_height = 4096; |
1274 | } |
1275 | } |
1275 | 1276 | ||
1276 | rdev->ddev->mode_config.preferred_depth = 24; |
1277 | rdev->ddev->mode_config.preferred_depth = 24; |
1277 | rdev->ddev->mode_config.prefer_shadow = 1; |
1278 | rdev->ddev->mode_config.prefer_shadow = 1; |
1278 | 1279 | ||
1279 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1280 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1280 | 1281 | ||
1281 | ret = radeon_modeset_create_props(rdev); |
1282 | ret = radeon_modeset_create_props(rdev); |
1282 | if (ret) { |
1283 | if (ret) { |
1283 | return ret; |
1284 | return ret; |
1284 | } |
1285 | } |
1285 | 1286 | ||
1286 | /* init i2c buses */ |
1287 | /* init i2c buses */ |
1287 | radeon_i2c_init(rdev); |
1288 | radeon_i2c_init(rdev); |
1288 | 1289 | ||
1289 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1290 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1290 | if (!rdev->is_atom_bios) { |
1291 | if (!rdev->is_atom_bios) { |
1291 | /* check for hardcoded EDID in BIOS */ |
1292 | /* check for hardcoded EDID in BIOS */ |
1292 | radeon_combios_check_hardcoded_edid(rdev); |
1293 | radeon_combios_check_hardcoded_edid(rdev); |
1293 | } |
1294 | } |
1294 | 1295 | ||
1295 | /* allocate crtcs */ |
1296 | /* allocate crtcs */ |
1296 | for (i = 0; i < rdev->num_crtc; i++) { |
1297 | for (i = 0; i < rdev->num_crtc; i++) { |
1297 | radeon_crtc_init(rdev->ddev, i); |
1298 | radeon_crtc_init(rdev->ddev, i); |
1298 | } |
1299 | } |
1299 | 1300 | ||
1300 | /* okay we should have all the bios connectors */ |
1301 | /* okay we should have all the bios connectors */ |
1301 | ret = radeon_setup_enc_conn(rdev->ddev); |
1302 | ret = radeon_setup_enc_conn(rdev->ddev); |
1302 | if (!ret) { |
1303 | if (!ret) { |
1303 | return ret; |
1304 | return ret; |
1304 | } |
1305 | } |
1305 | 1306 | ||
1306 | /* init dig PHYs, disp eng pll */ |
1307 | /* init dig PHYs, disp eng pll */ |
1307 | if (rdev->is_atom_bios) { |
1308 | if (rdev->is_atom_bios) { |
1308 | radeon_atom_encoder_init(rdev); |
1309 | radeon_atom_encoder_init(rdev); |
1309 | radeon_atom_disp_eng_pll_init(rdev); |
1310 | radeon_atom_disp_eng_pll_init(rdev); |
1310 | } |
1311 | } |
1311 | 1312 | ||
1312 | /* initialize hpd */ |
1313 | /* initialize hpd */ |
1313 | // radeon_hpd_init(rdev); |
1314 | // radeon_hpd_init(rdev); |
1314 | 1315 | ||
1315 | /* setup afmt */ |
1316 | /* setup afmt */ |
1316 | radeon_afmt_init(rdev); |
1317 | radeon_afmt_init(rdev); |
1317 | 1318 | ||
1318 | radeon_fbdev_init(rdev); |
1319 | radeon_fbdev_init(rdev); |
1319 | 1320 | ||
1320 | LEAVE(); |
1321 | LEAVE(); |
1321 | 1322 | ||
1322 | return 0; |
1323 | return 0; |
1323 | } |
1324 | } |
1324 | 1325 | ||
1325 | void radeon_modeset_fini(struct radeon_device *rdev) |
1326 | void radeon_modeset_fini(struct radeon_device *rdev) |
1326 | { |
1327 | { |
1327 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1328 | kfree(rdev->mode_info.bios_hardcoded_edid); |
- | 1329 | ||
- | 1330 | /* free i2c buses */ |
|
- | 1331 | radeon_i2c_fini(rdev); |
|
1328 | 1332 | ||
1329 | if (rdev->mode_info.mode_config_initialized) { |
1333 | if (rdev->mode_info.mode_config_initialized) { |
1330 | // radeon_afmt_fini(rdev); |
1334 | // radeon_afmt_fini(rdev); |
1331 | // drm_kms_helper_poll_fini(rdev->ddev); |
1335 | // drm_kms_helper_poll_fini(rdev->ddev); |
1332 | // radeon_hpd_fini(rdev); |
1336 | // radeon_hpd_fini(rdev); |
1333 | // drm_mode_config_cleanup(rdev->ddev); |
1337 | // drm_mode_config_cleanup(rdev->ddev); |
1334 | rdev->mode_info.mode_config_initialized = false; |
1338 | rdev->mode_info.mode_config_initialized = false; |
1335 | } |
1339 | } |
1336 | /* free i2c buses */ |
- | |
1337 | radeon_i2c_fini(rdev); |
- | |
1338 | } |
1340 | } |
1339 | 1341 | ||
1340 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
1342 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
1341 | { |
1343 | { |
1342 | /* try and guess if this is a tv or a monitor */ |
1344 | /* try and guess if this is a tv or a monitor */ |
1343 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
1345 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
1344 | (mode->vdisplay == 576) || /* 576p */ |
1346 | (mode->vdisplay == 576) || /* 576p */ |
1345 | (mode->vdisplay == 720) || /* 720p */ |
1347 | (mode->vdisplay == 720) || /* 720p */ |
1346 | (mode->vdisplay == 1080)) /* 1080p */ |
1348 | (mode->vdisplay == 1080)) /* 1080p */ |
1347 | return true; |
1349 | return true; |
1348 | else |
1350 | else |
1349 | return false; |
1351 | return false; |
1350 | } |
1352 | } |
1351 | 1353 | ||
1352 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1354 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1353 | const struct drm_display_mode *mode, |
1355 | const struct drm_display_mode *mode, |
1354 | struct drm_display_mode *adjusted_mode) |
1356 | struct drm_display_mode *adjusted_mode) |
1355 | { |
1357 | { |
1356 | struct drm_device *dev = crtc->dev; |
1358 | struct drm_device *dev = crtc->dev; |
1357 | struct radeon_device *rdev = dev->dev_private; |
1359 | struct radeon_device *rdev = dev->dev_private; |
1358 | struct drm_encoder *encoder; |
1360 | struct drm_encoder *encoder; |
1359 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1361 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1360 | struct radeon_encoder *radeon_encoder; |
1362 | struct radeon_encoder *radeon_encoder; |
1361 | struct drm_connector *connector; |
1363 | struct drm_connector *connector; |
1362 | struct radeon_connector *radeon_connector; |
1364 | struct radeon_connector *radeon_connector; |
1363 | bool first = true; |
1365 | bool first = true; |
1364 | u32 src_v = 1, dst_v = 1; |
1366 | u32 src_v = 1, dst_v = 1; |
1365 | u32 src_h = 1, dst_h = 1; |
1367 | u32 src_h = 1, dst_h = 1; |
1366 | 1368 | ||
1367 | radeon_crtc->h_border = 0; |
1369 | radeon_crtc->h_border = 0; |
1368 | radeon_crtc->v_border = 0; |
1370 | radeon_crtc->v_border = 0; |
1369 | 1371 | ||
1370 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1372 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1371 | if (encoder->crtc != crtc) |
1373 | if (encoder->crtc != crtc) |
1372 | continue; |
1374 | continue; |
1373 | radeon_encoder = to_radeon_encoder(encoder); |
1375 | radeon_encoder = to_radeon_encoder(encoder); |
1374 | connector = radeon_get_connector_for_encoder(encoder); |
1376 | connector = radeon_get_connector_for_encoder(encoder); |
1375 | radeon_connector = to_radeon_connector(connector); |
1377 | radeon_connector = to_radeon_connector(connector); |
1376 | 1378 | ||
1377 | if (first) { |
1379 | if (first) { |
1378 | /* set scaling */ |
1380 | /* set scaling */ |
1379 | if (radeon_encoder->rmx_type == RMX_OFF) |
1381 | if (radeon_encoder->rmx_type == RMX_OFF) |
1380 | radeon_crtc->rmx_type = RMX_OFF; |
1382 | radeon_crtc->rmx_type = RMX_OFF; |
1381 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1383 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1382 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1384 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1383 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1385 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1384 | else |
1386 | else |
1385 | radeon_crtc->rmx_type = RMX_OFF; |
1387 | radeon_crtc->rmx_type = RMX_OFF; |
1386 | /* copy native mode */ |
1388 | /* copy native mode */ |
1387 | memcpy(&radeon_crtc->native_mode, |
1389 | memcpy(&radeon_crtc->native_mode, |
1388 | &radeon_encoder->native_mode, |
1390 | &radeon_encoder->native_mode, |
1389 | sizeof(struct drm_display_mode)); |
1391 | sizeof(struct drm_display_mode)); |
1390 | src_v = crtc->mode.vdisplay; |
1392 | src_v = crtc->mode.vdisplay; |
1391 | dst_v = radeon_crtc->native_mode.vdisplay; |
1393 | dst_v = radeon_crtc->native_mode.vdisplay; |
1392 | src_h = crtc->mode.hdisplay; |
1394 | src_h = crtc->mode.hdisplay; |
1393 | dst_h = radeon_crtc->native_mode.hdisplay; |
1395 | dst_h = radeon_crtc->native_mode.hdisplay; |
1394 | 1396 | ||
1395 | /* fix up for overscan on hdmi */ |
1397 | /* fix up for overscan on hdmi */ |
1396 | if (ASIC_IS_AVIVO(rdev) && |
1398 | if (ASIC_IS_AVIVO(rdev) && |
1397 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
1399 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
1398 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1400 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1399 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
1401 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
1400 | drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
1402 | drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
1401 | is_hdtv_mode(mode)))) { |
1403 | is_hdtv_mode(mode)))) { |
1402 | if (radeon_encoder->underscan_hborder != 0) |
1404 | if (radeon_encoder->underscan_hborder != 0) |
1403 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
1405 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
1404 | else |
1406 | else |
1405 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
1407 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
1406 | if (radeon_encoder->underscan_vborder != 0) |
1408 | if (radeon_encoder->underscan_vborder != 0) |
1407 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
1409 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
1408 | else |
1410 | else |
1409 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
1411 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
1410 | radeon_crtc->rmx_type = RMX_FULL; |
1412 | radeon_crtc->rmx_type = RMX_FULL; |
1411 | src_v = crtc->mode.vdisplay; |
1413 | src_v = crtc->mode.vdisplay; |
1412 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
1414 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
1413 | src_h = crtc->mode.hdisplay; |
1415 | src_h = crtc->mode.hdisplay; |
1414 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
1416 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
1415 | } |
1417 | } |
1416 | first = false; |
1418 | first = false; |
1417 | } else { |
1419 | } else { |
1418 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1420 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1419 | /* WARNING: Right now this can't happen but |
1421 | /* WARNING: Right now this can't happen but |
1420 | * in the future we need to check that scaling |
1422 | * in the future we need to check that scaling |
1421 | * are consistent across different encoder |
1423 | * are consistent across different encoder |
1422 | * (ie all encoder can work with the same |
1424 | * (ie all encoder can work with the same |
1423 | * scaling). |
1425 | * scaling). |
1424 | */ |
1426 | */ |
1425 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1427 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1426 | return false; |
1428 | return false; |
1427 | } |
1429 | } |
1428 | } |
1430 | } |
1429 | } |
1431 | } |
1430 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1432 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1431 | fixed20_12 a, b; |
1433 | fixed20_12 a, b; |
1432 | a.full = dfixed_const(src_v); |
1434 | a.full = dfixed_const(src_v); |
1433 | b.full = dfixed_const(dst_v); |
1435 | b.full = dfixed_const(dst_v); |
1434 | radeon_crtc->vsc.full = dfixed_div(a, b); |
1436 | radeon_crtc->vsc.full = dfixed_div(a, b); |
1435 | a.full = dfixed_const(src_h); |
1437 | a.full = dfixed_const(src_h); |
1436 | b.full = dfixed_const(dst_h); |
1438 | b.full = dfixed_const(dst_h); |
1437 | radeon_crtc->hsc.full = dfixed_div(a, b); |
1439 | radeon_crtc->hsc.full = dfixed_div(a, b); |
1438 | } else { |
1440 | } else { |
1439 | radeon_crtc->vsc.full = dfixed_const(1); |
1441 | radeon_crtc->vsc.full = dfixed_const(1); |
1440 | radeon_crtc->hsc.full = dfixed_const(1); |
1442 | radeon_crtc->hsc.full = dfixed_const(1); |
1441 | } |
1443 | } |
1442 | return true; |
1444 | return true; |
1443 | } |
1445 | } |
1444 | 1446 | ||
1445 | /* |
1447 | /* |
1446 | * Retrieve current video scanout position of crtc on a given gpu, and |
1448 | * Retrieve current video scanout position of crtc on a given gpu, and |
1447 | * an optional accurate timestamp of when query happened. |
1449 | * an optional accurate timestamp of when query happened. |
1448 | * |
1450 | * |
1449 | * \param dev Device to query. |
1451 | * \param dev Device to query. |
1450 | * \param crtc Crtc to query. |
1452 | * \param crtc Crtc to query. |
1451 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
1453 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
1452 | * For driver internal use only also supports these flags: |
1454 | * For driver internal use only also supports these flags: |
1453 | * |
1455 | * |
1454 | * USE_REAL_VBLANKSTART to use the real start of vblank instead |
1456 | * USE_REAL_VBLANKSTART to use the real start of vblank instead |
1455 | * of a fudged earlier start of vblank. |
1457 | * of a fudged earlier start of vblank. |
1456 | * |
1458 | * |
1457 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the |
1459 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the |
1458 | * fudged earlier start of vblank in *vpos and the distance |
1460 | * fudged earlier start of vblank in *vpos and the distance |
1459 | * to true start of vblank in *hpos. |
1461 | * to true start of vblank in *hpos. |
1460 | * |
1462 | * |
1461 | * \param *vpos Location where vertical scanout position should be stored. |
1463 | * \param *vpos Location where vertical scanout position should be stored. |
1462 | * \param *hpos Location where horizontal scanout position should go. |
1464 | * \param *hpos Location where horizontal scanout position should go. |
1463 | * \param *stime Target location for timestamp taken immediately before |
1465 | * \param *stime Target location for timestamp taken immediately before |
1464 | * scanout position query. Can be NULL to skip timestamp. |
1466 | * scanout position query. Can be NULL to skip timestamp. |
1465 | * \param *etime Target location for timestamp taken immediately after |
1467 | * \param *etime Target location for timestamp taken immediately after |
1466 | * scanout position query. Can be NULL to skip timestamp. |
1468 | * scanout position query. Can be NULL to skip timestamp. |
1467 | * |
1469 | * |
1468 | * Returns vpos as a positive number while in active scanout area. |
1470 | * Returns vpos as a positive number while in active scanout area. |
1469 | * Returns vpos as a negative number inside vblank, counting the number |
1471 | * Returns vpos as a negative number inside vblank, counting the number |
1470 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
1472 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
1471 | * until start of active scanout / end of vblank." |
1473 | * until start of active scanout / end of vblank." |
1472 | * |
1474 | * |
1473 | * \return Flags, or'ed together as follows: |
1475 | * \return Flags, or'ed together as follows: |
1474 | * |
1476 | * |
1475 | * DRM_SCANOUTPOS_VALID = Query successful. |
1477 | * DRM_SCANOUTPOS_VALID = Query successful. |
1476 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1478 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1477 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
1479 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
1478 | * this flag means that returned position may be offset by a constant but |
1480 | * this flag means that returned position may be offset by a constant but |
1479 | * unknown small number of scanlines wrt. real scanout position. |
1481 | * unknown small number of scanlines wrt. real scanout position. |
1480 | * |
1482 | * |
1481 | */ |
1483 | */ |
1482 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
1484 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
1483 | unsigned int flags, int *vpos, int *hpos, |
1485 | unsigned int flags, int *vpos, int *hpos, |
1484 | ktime_t *stime, ktime_t *etime, |
1486 | ktime_t *stime, ktime_t *etime, |
1485 | const struct drm_display_mode *mode) |
1487 | const struct drm_display_mode *mode) |
1486 | { |
1488 | { |
1487 | u32 stat_crtc = 0, vbl = 0, position = 0; |
1489 | u32 stat_crtc = 0, vbl = 0, position = 0; |
1488 | int vbl_start, vbl_end, vtotal, ret = 0; |
1490 | int vbl_start, vbl_end, vtotal, ret = 0; |
1489 | bool in_vbl = true; |
1491 | bool in_vbl = true; |
1490 | 1492 | ||
1491 | struct radeon_device *rdev = dev->dev_private; |
1493 | struct radeon_device *rdev = dev->dev_private; |
1492 | 1494 | ||
1493 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
1495 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
1494 | 1496 | ||
1495 | /* Get optional system timestamp before query. */ |
1497 | /* Get optional system timestamp before query. */ |
1496 | if (stime) |
1498 | if (stime) |
1497 | *stime = ktime_get(); |
1499 | *stime = ktime_get(); |
1498 | 1500 | ||
1499 | if (ASIC_IS_DCE4(rdev)) { |
1501 | if (ASIC_IS_DCE4(rdev)) { |
1500 | if (pipe == 0) { |
1502 | if (pipe == 0) { |
1501 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1503 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1502 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1504 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1503 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1505 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1504 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1506 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1505 | ret |= DRM_SCANOUTPOS_VALID; |
1507 | ret |= DRM_SCANOUTPOS_VALID; |
1506 | } |
1508 | } |
1507 | if (pipe == 1) { |
1509 | if (pipe == 1) { |
1508 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1510 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1509 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1511 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1510 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1512 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1511 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1513 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1512 | ret |= DRM_SCANOUTPOS_VALID; |
1514 | ret |= DRM_SCANOUTPOS_VALID; |
1513 | } |
1515 | } |
1514 | if (pipe == 2) { |
1516 | if (pipe == 2) { |
1515 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1517 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1516 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1518 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1517 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1519 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1518 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1520 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1519 | ret |= DRM_SCANOUTPOS_VALID; |
1521 | ret |= DRM_SCANOUTPOS_VALID; |
1520 | } |
1522 | } |
1521 | if (pipe == 3) { |
1523 | if (pipe == 3) { |
1522 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1524 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1523 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1525 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1524 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1526 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1525 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1527 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1526 | ret |= DRM_SCANOUTPOS_VALID; |
1528 | ret |= DRM_SCANOUTPOS_VALID; |
1527 | } |
1529 | } |
1528 | if (pipe == 4) { |
1530 | if (pipe == 4) { |
1529 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1531 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1530 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1532 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1531 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1533 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1532 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1534 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1533 | ret |= DRM_SCANOUTPOS_VALID; |
1535 | ret |= DRM_SCANOUTPOS_VALID; |
1534 | } |
1536 | } |
1535 | if (pipe == 5) { |
1537 | if (pipe == 5) { |
1536 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1538 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1537 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1539 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1538 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1540 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1539 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1541 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1540 | ret |= DRM_SCANOUTPOS_VALID; |
1542 | ret |= DRM_SCANOUTPOS_VALID; |
1541 | } |
1543 | } |
1542 | } else if (ASIC_IS_AVIVO(rdev)) { |
1544 | } else if (ASIC_IS_AVIVO(rdev)) { |
1543 | if (pipe == 0) { |
1545 | if (pipe == 0) { |
1544 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
1546 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
1545 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
1547 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
1546 | ret |= DRM_SCANOUTPOS_VALID; |
1548 | ret |= DRM_SCANOUTPOS_VALID; |
1547 | } |
1549 | } |
1548 | if (pipe == 1) { |
1550 | if (pipe == 1) { |
1549 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
1551 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
1550 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
1552 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
1551 | ret |= DRM_SCANOUTPOS_VALID; |
1553 | ret |= DRM_SCANOUTPOS_VALID; |
1552 | } |
1554 | } |
1553 | } else { |
1555 | } else { |
1554 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
1556 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
1555 | if (pipe == 0) { |
1557 | if (pipe == 0) { |
1556 | /* Assume vbl_end == 0, get vbl_start from |
1558 | /* Assume vbl_end == 0, get vbl_start from |
1557 | * upper 16 bits. |
1559 | * upper 16 bits. |
1558 | */ |
1560 | */ |
1559 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
1561 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
1560 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1562 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1561 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
1563 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
1562 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1564 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1563 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
1565 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
1564 | if (!(stat_crtc & 1)) |
1566 | if (!(stat_crtc & 1)) |
1565 | in_vbl = false; |
1567 | in_vbl = false; |
1566 | 1568 | ||
1567 | ret |= DRM_SCANOUTPOS_VALID; |
1569 | ret |= DRM_SCANOUTPOS_VALID; |
1568 | } |
1570 | } |
1569 | if (pipe == 1) { |
1571 | if (pipe == 1) { |
1570 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
1572 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
1571 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1573 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1572 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1574 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1573 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
1575 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
1574 | if (!(stat_crtc & 1)) |
1576 | if (!(stat_crtc & 1)) |
1575 | in_vbl = false; |
1577 | in_vbl = false; |
1576 | 1578 | ||
1577 | ret |= DRM_SCANOUTPOS_VALID; |
1579 | ret |= DRM_SCANOUTPOS_VALID; |
1578 | } |
1580 | } |
1579 | } |
1581 | } |
1580 | 1582 | ||
1581 | /* Get optional system timestamp after query. */ |
1583 | /* Get optional system timestamp after query. */ |
1582 | if (etime) |
1584 | if (etime) |
1583 | *etime = ktime_get(); |
1585 | *etime = ktime_get(); |
1584 | 1586 | ||
1585 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
1587 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
1586 | 1588 | ||
1587 | /* Decode into vertical and horizontal scanout position. */ |
1589 | /* Decode into vertical and horizontal scanout position. */ |
1588 | *vpos = position & 0x1fff; |
1590 | *vpos = position & 0x1fff; |
1589 | *hpos = (position >> 16) & 0x1fff; |
1591 | *hpos = (position >> 16) & 0x1fff; |
1590 | 1592 | ||
1591 | /* Valid vblank area boundaries from gpu retrieved? */ |
1593 | /* Valid vblank area boundaries from gpu retrieved? */ |
1592 | if (vbl > 0) { |
1594 | if (vbl > 0) { |
1593 | /* Yes: Decode. */ |
1595 | /* Yes: Decode. */ |
1594 | ret |= DRM_SCANOUTPOS_ACCURATE; |
1596 | ret |= DRM_SCANOUTPOS_ACCURATE; |
1595 | vbl_start = vbl & 0x1fff; |
1597 | vbl_start = vbl & 0x1fff; |
1596 | vbl_end = (vbl >> 16) & 0x1fff; |
1598 | vbl_end = (vbl >> 16) & 0x1fff; |
1597 | } |
1599 | } |
1598 | else { |
1600 | else { |
1599 | /* No: Fake something reasonable which gives at least ok results. */ |
1601 | /* No: Fake something reasonable which gives at least ok results. */ |
1600 | vbl_start = mode->crtc_vdisplay; |
1602 | vbl_start = mode->crtc_vdisplay; |
1601 | vbl_end = 0; |
1603 | vbl_end = 0; |
1602 | } |
1604 | } |
1603 | 1605 | ||
1604 | /* Called from driver internal vblank counter query code? */ |
1606 | /* Called from driver internal vblank counter query code? */ |
1605 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { |
1607 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { |
1606 | /* Caller wants distance from real vbl_start in *hpos */ |
1608 | /* Caller wants distance from real vbl_start in *hpos */ |
1607 | *hpos = *vpos - vbl_start; |
1609 | *hpos = *vpos - vbl_start; |
1608 | } |
1610 | } |
1609 | 1611 | ||
1610 | /* Fudge vblank to start a few scanlines earlier to handle the |
1612 | /* Fudge vblank to start a few scanlines earlier to handle the |
1611 | * problem that vblank irqs fire a few scanlines before start |
1613 | * problem that vblank irqs fire a few scanlines before start |
1612 | * of vblank. Some driver internal callers need the true vblank |
1614 | * of vblank. Some driver internal callers need the true vblank |
1613 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. |
1615 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. |
1614 | * |
1616 | * |
1615 | * The cause of the "early" vblank irq is that the irq is triggered |
1617 | * The cause of the "early" vblank irq is that the irq is triggered |
1616 | * by the line buffer logic when the line buffer read position enters |
1618 | * by the line buffer logic when the line buffer read position enters |
1617 | * the vblank, whereas our crtc scanout position naturally lags the |
1619 | * the vblank, whereas our crtc scanout position naturally lags the |
1618 | * line buffer read position. |
1620 | * line buffer read position. |
1619 | */ |
1621 | */ |
1620 | if (!(flags & USE_REAL_VBLANKSTART)) |
1622 | if (!(flags & USE_REAL_VBLANKSTART)) |
1621 | vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; |
1623 | vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; |
1622 | 1624 | ||
1623 | /* Test scanout position against vblank region. */ |
1625 | /* Test scanout position against vblank region. */ |
1624 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
1626 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
1625 | in_vbl = false; |
1627 | in_vbl = false; |
1626 | 1628 | ||
1627 | /* In vblank? */ |
1629 | /* In vblank? */ |
1628 | if (in_vbl) |
1630 | if (in_vbl) |
1629 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
1631 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
1630 | 1632 | ||
1631 | /* Called from driver internal vblank counter query code? */ |
1633 | /* Called from driver internal vblank counter query code? */ |
1632 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { |
1634 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { |
1633 | /* Caller wants distance from fudged earlier vbl_start */ |
1635 | /* Caller wants distance from fudged earlier vbl_start */ |
1634 | *vpos -= vbl_start; |
1636 | *vpos -= vbl_start; |
1635 | return ret; |
1637 | return ret; |
1636 | } |
1638 | } |
1637 | 1639 | ||
1638 | /* Check if inside vblank area and apply corrective offsets: |
1640 | /* Check if inside vblank area and apply corrective offsets: |
1639 | * vpos will then be >=0 in video scanout area, but negative |
1641 | * vpos will then be >=0 in video scanout area, but negative |
1640 | * within vblank area, counting down the number of lines until |
1642 | * within vblank area, counting down the number of lines until |
1641 | * start of scanout. |
1643 | * start of scanout. |
1642 | */ |
1644 | */ |
1643 | 1645 | ||
1644 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
1646 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
1645 | if (in_vbl && (*vpos >= vbl_start)) { |
1647 | if (in_vbl && (*vpos >= vbl_start)) { |
1646 | vtotal = mode->crtc_vtotal; |
1648 | vtotal = mode->crtc_vtotal; |
1647 | *vpos = *vpos - vtotal; |
1649 | *vpos = *vpos - vtotal; |
1648 | } |
1650 | } |
1649 | 1651 | ||
1650 | /* Correct for shifted end of vbl at vbl_end. */ |
1652 | /* Correct for shifted end of vbl at vbl_end. */ |
1651 | *vpos = *vpos - vbl_end; |
1653 | *vpos = *vpos - vbl_end; |
1652 | 1654 | ||
1653 | return ret; |
1655 | return ret; |
1654 | }>>>>>>>>>>>>>>>>>>>>>=>>>>>=>>>>>><>><>><>>>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |
1656 | }>>>>>>>>>>>>>>>>>>>>>=>>>>>=>>>>>><>><>><>>>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |