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Regard whitespace Rev 880 → Rev 881

/programs/system/drivers/ati2d/accel_3d.inc
1,5 → 1,4
#include "radeon_reg.h"
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
//#define FINISH_ACCEL() ADVANCE_RING()

/programs/system/drivers/ati2d/ati2d.c
5,8 → 5,12
#include <malloc.h>
#include <memory.h>
#include "pci.h"
#include "syscall.h"
#include "radeon_reg.h"
#include "ati2d.h"
#include "accel_2d.h"

/programs/system/drivers/ati2d/ati2d.h
1,7 → 1,6
typedef void *pointer;
typedef unsigned int Bool;
typedef unsigned int memType;
8,104 → 7,123
typedef struct { float hi, lo; } range;
#include "pci.h"
#include "rhd_regs.h"
#define R300_PIO 1
#define IS_R300_3D 0
#define IS_R500_3D 1
#define PCI_CMD_STAT_REG 0x04
#define R300_PIO 1
typedef enum
{
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
CHIP_FAMILY_RADEON,
CHIP_FAMILY_RV100,
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
CHIP_FAMILY_RV200,
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
CHIP_FAMILY_RS300, /* RS300/RS350 */
CHIP_FAMILY_RV280,
CHIP_FAMILY_R300,
CHIP_FAMILY_R350,
CHIP_FAMILY_RV350,
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_RV410, /* RV410, M26 */
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
CHIP_FAMILY_RV515, /* rv515 */
CHIP_FAMILY_R520, /* r520 */
CHIP_FAMILY_RV530, /* rv530 */
CHIP_FAMILY_R580, /* r580 */
CHIP_FAMILY_RV560, /* rv560 */
CHIP_FAMILY_RV570, /* rv570 */
CHIP_FAMILY_RS600,
CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
CHIP_FAMILY_R600, /* r600 */
CHIP_FAMILY_R630,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
CHIP_FAMILY_RV670,
CHIP_FAMILY_RV620,
CHIP_FAMILY_RV635,
CHIP_FAMILY_RS780,
CHIP_FAMILY_RV770,
CHIP_FAMILY_LAST
} RADEONChipFamily;
enum RHD_CHIPSETS {
RHD_UNKNOWN = 0,
RHD_R300,
RHD_R350,
RHD_RV350,
RHD_RV370,
RHD_RV380,
/* R500 */
RHD_RV505,
RHD_RV515,
RHD_RV516,
RHD_R520,
RHD_RV530,
RHD_RV535,
RHD_RV550,
RHD_RV560,
RHD_RV570,
RHD_R580,
/* R500 Mobility */
RHD_M52,
RHD_M54,
RHD_M56,
RHD_M58,
RHD_M62,
RHD_M64,
RHD_M66,
RHD_M68,
RHD_M71,
/* R500 integrated */
RHD_RS600,
RHD_RS690,
RHD_RS740,
/* R600 */
RHD_R600,
RHD_RV610,
RHD_RV630,
/* R600 Mobility */
RHD_M72,
RHD_M74,
RHD_M76,
/* RV670 came into existence after RV6x0 and M7x */
RHD_RV670,
RHD_R680,
RHD_RV620,
RHD_M82,
RHD_RV635,
RHD_M86,
RHD_RS780,
RHD_CHIP_END
};
#define IS_RV100_VARIANT ((rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300))
enum RHD_FAMILIES {
RHD_FAMILY_UNKNOWN = 0,
RHD_FAMILY_RADEON,
#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \
(info->ChipFamily == CHIP_FAMILY_RV350) || \
(info->ChipFamily == CHIP_FAMILY_R350) || \
(info->ChipFamily == CHIP_FAMILY_RV380) || \
(info->ChipFamily == CHIP_FAMILY_R420) || \
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS400) || \
(info->ChipFamily == CHIP_FAMILY_RS480))
RHD_FAMILY_RV100,
RHD_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
RHD_FAMILY_RV200,
RHD_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
RHD_FAMILY_R200,
RHD_FAMILY_RV250,
RHD_FAMILY_RS300, /* RS300/RS350 */
RHD_FAMILY_RV280,
#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
RHD_FAMILY_R300,
RHD_FAMILY_R350,
RHD_FAMILY_RV350,
RHD_FAMILY_RV380, /* RV370/RV380/M22/M24 */
RHD_FAMILY_R420, /* R420/R423/M18 */
RHD_FAMILY_RV410, /* RV410, M26 */
RHD_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
RHD_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
RHD_FAMILY_RV515,
RHD_FAMILY_R520,
RHD_FAMILY_RV530,
RHD_FAMILY_RV560,
RHD_FAMILY_RV570,
RHD_FAMILY_R580,
RHD_FAMILY_RS690,
RHD_FAMILY_R600,
RHD_FAMILY_RV610,
RHD_FAMILY_RV630,
RHD_FAMILY_RV670,
RHD_FAMILY_RV620,
RHD_FAMILY_RV635,
RHD_FAMILY_RS780
};
#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
(info->ChipFamily == CHIP_FAMILY_R520) || \
(info->ChipFamily == CHIP_FAMILY_RV530) || \
(info->ChipFamily == CHIP_FAMILY_R580) || \
(info->ChipFamily == CHIP_FAMILY_RV560) || \
(info->ChipFamily == CHIP_FAMILY_RV570))
#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \
(info->ChipFamily == CHIP_FAMILY_RV350) || \
(info->ChipFamily == CHIP_FAMILY_R350) || \
(info->ChipFamily == CHIP_FAMILY_RV380) || \
(info->ChipFamily == CHIP_FAMILY_R420) || \
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS690) || \
(info->ChipFamily == CHIP_FAMILY_RS600) || \
(info->ChipFamily == CHIP_FAMILY_RS740) || \
(info->ChipFamily == CHIP_FAMILY_RS400) || \
(info->ChipFamily == CHIP_FAMILY_RS480))
typedef enum {
CARD_PCI,
CARD_AGP,
CARD_PCIE
} RADEONCardType;
/*
* Errata workarounds
*/
typedef enum {
CHIP_ERRATA_R300_CG = 0x00000001,
CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
CHIP_ERRATA_PLL_DELAY = 0x00000004
} RADEONErrata;
typedef struct
{
u32_t pci_device_id;
RADEONChipFamily chip_family;
int mobility;
int igp;
int nocrtc2;
int nointtvout;
int singledac;
} RADEONCardInfo;
#define RHD_FB_BAR 0
#define RHD_MMIO_BAR 2
116,27 → 134,43
{
u32_t MMIOBase;
u32_t MMIOMapSize;
u32_t videoRam;
// CARD32 FbBase; /* map base of fb */
u32_t PhisBase;
u32_t FbIntAddress; /* card internal address of FB */
u32_t FbMapSize;
// u32_t PhisBase;
// u32_t FbIntAddress; /* card internal address of FB */
// u32_t FbMapSize;
u32_t FbFreeStart;
u32_t FbFreeSize;
/* visible part of the framebuffer */
unsigned int FbScanoutStart;
unsigned int FbScanoutSize;
// unsigned int FbScanoutStart;
// unsigned int FbScanoutSize;
enum RHD_CHIPSETS ChipSet;
enum RHD_FAMILIES ChipFamily;
u32_t LinearAddr; /* Frame buffer physical address */
char *ChipName;
u32_t fbLocation;
u32_t mc_fb_location;
u32_t mc_agp_location;
u32_t mc_agp_location_hi;
Bool IsIGP;
u32_t videoRam;
u32_t MemCntl;
u32_t BusCntl;
unsigned long FbMapSize; /* Size of frame buffer, in bytes */
unsigned long FbSecureSize; /* Size of secured fb area at end of
framebuffer */
RADEONChipFamily ChipFamily;
RADEONErrata ChipErrata;
char *chipset;
int IsIGP;
int IsMobility;
u32_t bus;
u32_t devfn;
146,6 → 180,8
u16_t subvendor_id;
u16_t subdevice_id;
RADEONCardType cardType; /* Current card is a PCI card */
u32_t memBase[6];
u32_t ioBase[6];
u32_t memtype[6];
170,8 → 206,11
u32_t ring_rp;
u32_t ring_wp;
int RamWidth;
Bool IsDDR;
int num_gb_pipes;
Bool has_tcl;
int has_tcl;
}RHD_t, *RHDPtr;
extern RHD_t rhd;
273,14 → 312,13
return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset));
}
//#define INREG(offset) *(volatile CARD32 *)((CARD8*)(rhd.MMIOBase + (offset)))
extern inline void
OUTREG(u16_t offset, u32_t value)
extern inline void OUTREG(u16_t offset, u32_t value)
{
*(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
}
extern inline u32_t _RHDRegRead(RHDPtr rhdPtr, u16_t offset)
{
return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset));
314,8 → 352,6
_RHDRegWrite(rhdPtr, offset, tmp);
};
enum RHD_FAMILIES RHDFamily(enum RHD_CHIPSETS chipset);
#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset))
#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value))
#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))

/programs/system/drivers/ati2d/ati_pciids_gen.h
0,0 → 1,385
#define PCI_CHIP_RV380_3150 0x3150
#define PCI_CHIP_RV380_3151 0x3151
#define PCI_CHIP_RV380_3152 0x3152
#define PCI_CHIP_RV380_3154 0x3154
#define PCI_CHIP_RV380_3E50 0x3E50
#define PCI_CHIP_RV380_3E54 0x3E54
#define PCI_CHIP_RS100_4136 0x4136
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_R300_AD 0x4144
#define PCI_CHIP_R300_AE 0x4145
#define PCI_CHIP_R300_AF 0x4146
#define PCI_CHIP_R300_AG 0x4147
#define PCI_CHIP_R350_AH 0x4148
#define PCI_CHIP_R350_AI 0x4149
#define PCI_CHIP_R350_AJ 0x414A
#define PCI_CHIP_R350_AK 0x414B
#define PCI_CHIP_RV350_AP 0x4150
#define PCI_CHIP_RV350_AQ 0x4151
#define PCI_CHIP_RV360_AR 0x4152
#define PCI_CHIP_RV350_AS 0x4153
#define PCI_CHIP_RV350_AT 0x4154
#define PCI_CHIP_RV350_4155 0x4155
#define PCI_CHIP_RV350_AV 0x4156
#define PCI_CHIP_MACH32 0x4158
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_R200_BB 0x4242
#define PCI_CHIP_R200_BC 0x4243
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_MACH64CT 0x4354
#define PCI_CHIP_MACH64CX 0x4358
#define PCI_CHIP_RS250_4437 0x4437
#define PCI_CHIP_MACH64ET 0x4554
#define PCI_CHIP_MACH64GB 0x4742
#define PCI_CHIP_MACH64GD 0x4744
#define PCI_CHIP_MACH64GI 0x4749
#define PCI_CHIP_MACH64GL 0x474C
#define PCI_CHIP_MACH64GM 0x474D
#define PCI_CHIP_MACH64GN 0x474E
#define PCI_CHIP_MACH64GO 0x474F
#define PCI_CHIP_MACH64GP 0x4750
#define PCI_CHIP_MACH64GQ 0x4751
#define PCI_CHIP_MACH64GR 0x4752
#define PCI_CHIP_MACH64GS 0x4753
#define PCI_CHIP_MACH64GT 0x4754
#define PCI_CHIP_MACH64GU 0x4755
#define PCI_CHIP_MACH64GV 0x4756
#define PCI_CHIP_MACH64GW 0x4757
#define PCI_CHIP_MACH64GX 0x4758
#define PCI_CHIP_MACH64GY 0x4759
#define PCI_CHIP_MACH64GZ 0x475A
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
#define PCI_CHIP_R420_JH 0x4A48
#define PCI_CHIP_R420_JI 0x4A49
#define PCI_CHIP_R420_JJ 0x4A4A
#define PCI_CHIP_R420_JK 0x4A4B
#define PCI_CHIP_R420_JL 0x4A4C
#define PCI_CHIP_R420_JM 0x4A4D
#define PCI_CHIP_R420_JN 0x4A4E
#define PCI_CHIP_R420_4A4F 0x4A4F
#define PCI_CHIP_R420_JP 0x4A50
#define PCI_CHIP_R481_4B49 0x4B49
#define PCI_CHIP_R481_4B4A 0x4B4A
#define PCI_CHIP_R481_4B4B 0x4B4B
#define PCI_CHIP_R481_4B4C 0x4B4C
#define PCI_CHIP_MACH64LB 0x4C42
#define PCI_CHIP_MACH64LD 0x4C44
#define PCI_CHIP_RAGE128LE 0x4C45
#define PCI_CHIP_RAGE128LF 0x4C46
#define PCI_CHIP_MACH64LG 0x4C47
#define PCI_CHIP_MACH64LI 0x4C49
#define PCI_CHIP_MACH64LM 0x4C4D
#define PCI_CHIP_MACH64LN 0x4C4E
#define PCI_CHIP_MACH64LP 0x4C50
#define PCI_CHIP_MACH64LQ 0x4C51
#define PCI_CHIP_MACH64LR 0x4C52
#define PCI_CHIP_MACH64LS 0x4C53
#define PCI_CHIP_RADEON_LW 0x4C57
#define PCI_CHIP_RADEON_LX 0x4C58
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
#define PCI_CHIP_RAGE128MF 0x4D46
#define PCI_CHIP_RAGE128ML 0x4D4C
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
#define PCI_CHIP_R350_NH 0x4E48
#define PCI_CHIP_R350_NI 0x4E49
#define PCI_CHIP_R360_NJ 0x4E4A
#define PCI_CHIP_R350_NK 0x4E4B
#define PCI_CHIP_RV350_NP 0x4E50
#define PCI_CHIP_RV350_NQ 0x4E51
#define PCI_CHIP_RV350_NR 0x4E52
#define PCI_CHIP_RV350_NS 0x4E53
#define PCI_CHIP_RV350_NT 0x4E54
#define PCI_CHIP_RV350_NV 0x4E56
#define PCI_CHIP_RAGE128PA 0x5041
#define PCI_CHIP_RAGE128PB 0x5042
#define PCI_CHIP_RAGE128PC 0x5043
#define PCI_CHIP_RAGE128PD 0x5044
#define PCI_CHIP_RAGE128PE 0x5045
#define PCI_CHIP_RAGE128PF 0x5046
#define PCI_CHIP_RAGE128PG 0x5047
#define PCI_CHIP_RAGE128PH 0x5048
#define PCI_CHIP_RAGE128PI 0x5049
#define PCI_CHIP_RAGE128PJ 0x504A
#define PCI_CHIP_RAGE128PK 0x504B
#define PCI_CHIP_RAGE128PL 0x504C
#define PCI_CHIP_RAGE128PM 0x504D
#define PCI_CHIP_RAGE128PN 0x504E
#define PCI_CHIP_RAGE128PO 0x504F
#define PCI_CHIP_RAGE128PP 0x5050
#define PCI_CHIP_RAGE128PQ 0x5051
#define PCI_CHIP_RAGE128PR 0x5052
#define PCI_CHIP_RAGE128PS 0x5053
#define PCI_CHIP_RAGE128PT 0x5054
#define PCI_CHIP_RAGE128PU 0x5055
#define PCI_CHIP_RAGE128PV 0x5056
#define PCI_CHIP_RAGE128PW 0x5057
#define PCI_CHIP_RAGE128PX 0x5058
#define PCI_CHIP_RADEON_QD 0x5144
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
#define PCI_CHIP_R200_QH 0x5148
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
#define PCI_CHIP_RV200_QW 0x5157
#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RV100_QY 0x5159
#define PCI_CHIP_RV100_QZ 0x515A
#define PCI_CHIP_RN50_515E 0x515E
#define PCI_CHIP_RAGE128RE 0x5245
#define PCI_CHIP_RAGE128RF 0x5246
#define PCI_CHIP_RAGE128RG 0x5247
#define PCI_CHIP_RAGE128RK 0x524B
#define PCI_CHIP_RAGE128RL 0x524C
#define PCI_CHIP_RAGE128SE 0x5345
#define PCI_CHIP_RAGE128SF 0x5346
#define PCI_CHIP_RAGE128SG 0x5347
#define PCI_CHIP_RAGE128SH 0x5348
#define PCI_CHIP_RAGE128SK 0x534B
#define PCI_CHIP_RAGE128SL 0x534C
#define PCI_CHIP_RAGE128SM 0x534D
#define PCI_CHIP_RAGE128SN 0x534E
#define PCI_CHIP_RAGE128TF 0x5446
#define PCI_CHIP_RAGE128TL 0x544C
#define PCI_CHIP_RAGE128TR 0x5452
#define PCI_CHIP_RAGE128TS 0x5453
#define PCI_CHIP_RAGE128TT 0x5454
#define PCI_CHIP_RAGE128TU 0x5455
#define PCI_CHIP_RV370_5460 0x5460
#define PCI_CHIP_RV370_5462 0x5462
#define PCI_CHIP_RV370_5464 0x5464
#define PCI_CHIP_R423_UH 0x5548
#define PCI_CHIP_R423_UI 0x5549
#define PCI_CHIP_R423_UJ 0x554A
#define PCI_CHIP_R423_UK 0x554B
#define PCI_CHIP_R430_554C 0x554C
#define PCI_CHIP_R430_554D 0x554D
#define PCI_CHIP_R430_554E 0x554E
#define PCI_CHIP_R430_554F 0x554F
#define PCI_CHIP_R423_5550 0x5550
#define PCI_CHIP_R423_UQ 0x5551
#define PCI_CHIP_R423_UR 0x5552
#define PCI_CHIP_R423_UT 0x5554
#define PCI_CHIP_RV410_564A 0x564A
#define PCI_CHIP_RV410_564B 0x564B
#define PCI_CHIP_RV410_564F 0x564F
#define PCI_CHIP_RV410_5652 0x5652
#define PCI_CHIP_RV410_5653 0x5653
#define PCI_CHIP_RV410_5657 0x5657
#define PCI_CHIP_MACH64VT 0x5654
#define PCI_CHIP_MACH64VU 0x5655
#define PCI_CHIP_MACH64VV 0x5656
#define PCI_CHIP_RS300_5834 0x5834
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS480_5954 0x5954
#define PCI_CHIP_RS480_5955 0x5955
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5964 0x5964
#define PCI_CHIP_RV280_5965 0x5965
#define PCI_CHIP_RN50_5969 0x5969
#define PCI_CHIP_RS482_5974 0x5974
#define PCI_CHIP_RS485_5975 0x5975
#define PCI_CHIP_RS400_5A41 0x5A41
#define PCI_CHIP_RS400_5A42 0x5A42
#define PCI_CHIP_RC410_5A61 0x5A61
#define PCI_CHIP_RC410_5A62 0x5A62
#define PCI_CHIP_RV370_5B60 0x5B60
#define PCI_CHIP_RV370_5B62 0x5B62
#define PCI_CHIP_RV370_5B63 0x5B63
#define PCI_CHIP_RV370_5B64 0x5B64
#define PCI_CHIP_RV370_5B65 0x5B65
#define PCI_CHIP_RV280_5C61 0x5C61
#define PCI_CHIP_RV280_5C63 0x5C63
#define PCI_CHIP_R430_5D48 0x5D48
#define PCI_CHIP_R430_5D49 0x5D49
#define PCI_CHIP_R430_5D4A 0x5D4A
#define PCI_CHIP_R480_5D4C 0x5D4C
#define PCI_CHIP_R480_5D4D 0x5D4D
#define PCI_CHIP_R480_5D4E 0x5D4E
#define PCI_CHIP_R480_5D4F 0x5D4F
#define PCI_CHIP_R480_5D50 0x5D50
#define PCI_CHIP_R480_5D52 0x5D52
#define PCI_CHIP_R423_5D57 0x5D57
#define PCI_CHIP_RV410_5E48 0x5E48
#define PCI_CHIP_RV410_5E4A 0x5E4A
#define PCI_CHIP_RV410_5E4B 0x5E4B
#define PCI_CHIP_RV410_5E4C 0x5E4C
#define PCI_CHIP_RV410_5E4D 0x5E4D
#define PCI_CHIP_RV410_5E4F 0x5E4F
#define PCI_CHIP_R520_7100 0x7100
#define PCI_CHIP_R520_7101 0x7101
#define PCI_CHIP_R520_7102 0x7102
#define PCI_CHIP_R520_7103 0x7103
#define PCI_CHIP_R520_7104 0x7104
#define PCI_CHIP_R520_7105 0x7105
#define PCI_CHIP_R520_7106 0x7106
#define PCI_CHIP_R520_7108 0x7108
#define PCI_CHIP_R520_7109 0x7109
#define PCI_CHIP_R520_710A 0x710A
#define PCI_CHIP_R520_710B 0x710B
#define PCI_CHIP_R520_710C 0x710C
#define PCI_CHIP_R520_710E 0x710E
#define PCI_CHIP_R520_710F 0x710F
#define PCI_CHIP_RV515_7140 0x7140
#define PCI_CHIP_RV515_7141 0x7141
#define PCI_CHIP_RV515_7142 0x7142
#define PCI_CHIP_RV515_7143 0x7143
#define PCI_CHIP_RV515_7144 0x7144
#define PCI_CHIP_RV515_7145 0x7145
#define PCI_CHIP_RV515_7146 0x7146
#define PCI_CHIP_RV515_7147 0x7147
#define PCI_CHIP_RV515_7149 0x7149
#define PCI_CHIP_RV515_714A 0x714A
#define PCI_CHIP_RV515_714B 0x714B
#define PCI_CHIP_RV515_714C 0x714C
#define PCI_CHIP_RV515_714D 0x714D
#define PCI_CHIP_RV515_714E 0x714E
#define PCI_CHIP_RV515_714F 0x714F
#define PCI_CHIP_RV515_7151 0x7151
#define PCI_CHIP_RV515_7152 0x7152
#define PCI_CHIP_RV515_7153 0x7153
#define PCI_CHIP_RV515_715E 0x715E
#define PCI_CHIP_RV515_715F 0x715F
#define PCI_CHIP_RV515_7180 0x7180
#define PCI_CHIP_RV515_7181 0x7181
#define PCI_CHIP_RV515_7183 0x7183
#define PCI_CHIP_RV515_7186 0x7186
#define PCI_CHIP_RV515_7187 0x7187
#define PCI_CHIP_RV515_7188 0x7188
#define PCI_CHIP_RV515_718A 0x718A
#define PCI_CHIP_RV515_718B 0x718B
#define PCI_CHIP_RV515_718C 0x718C
#define PCI_CHIP_RV515_718D 0x718D
#define PCI_CHIP_RV515_718F 0x718F
#define PCI_CHIP_RV515_7193 0x7193
#define PCI_CHIP_RV515_7196 0x7196
#define PCI_CHIP_RV515_719B 0x719B
#define PCI_CHIP_RV515_719F 0x719F
#define PCI_CHIP_RV530_71C0 0x71C0
#define PCI_CHIP_RV530_71C1 0x71C1
#define PCI_CHIP_RV530_71C2 0x71C2
#define PCI_CHIP_RV530_71C3 0x71C3
#define PCI_CHIP_RV530_71C4 0x71C4
#define PCI_CHIP_RV530_71C5 0x71C5
#define PCI_CHIP_RV530_71C6 0x71C6
#define PCI_CHIP_RV530_71C7 0x71C7
#define PCI_CHIP_RV530_71CD 0x71CD
#define PCI_CHIP_RV530_71CE 0x71CE
#define PCI_CHIP_RV530_71D2 0x71D2
#define PCI_CHIP_RV530_71D4 0x71D4
#define PCI_CHIP_RV530_71D5 0x71D5
#define PCI_CHIP_RV530_71D6 0x71D6
#define PCI_CHIP_RV530_71DA 0x71DA
#define PCI_CHIP_RV530_71DE 0x71DE
#define PCI_CHIP_RV515_7200 0x7200
#define PCI_CHIP_RV515_7210 0x7210
#define PCI_CHIP_RV515_7211 0x7211
#define PCI_CHIP_R580_7240 0x7240
#define PCI_CHIP_R580_7243 0x7243
#define PCI_CHIP_R580_7244 0x7244
#define PCI_CHIP_R580_7245 0x7245
#define PCI_CHIP_R580_7246 0x7246
#define PCI_CHIP_R580_7247 0x7247
#define PCI_CHIP_R580_7248 0x7248
#define PCI_CHIP_R580_7249 0x7249
#define PCI_CHIP_R580_724A 0x724A
#define PCI_CHIP_R580_724B 0x724B
#define PCI_CHIP_R580_724C 0x724C
#define PCI_CHIP_R580_724D 0x724D
#define PCI_CHIP_R580_724E 0x724E
#define PCI_CHIP_R580_724F 0x724F
#define PCI_CHIP_RV570_7280 0x7280
#define PCI_CHIP_RV560_7281 0x7281
#define PCI_CHIP_RV560_7283 0x7283
#define PCI_CHIP_R580_7284 0x7284
#define PCI_CHIP_RV560_7287 0x7287
#define PCI_CHIP_RV570_7288 0x7288
#define PCI_CHIP_RV570_7289 0x7289
#define PCI_CHIP_RV570_728B 0x728B
#define PCI_CHIP_RV570_728C 0x728C
#define PCI_CHIP_RV560_7290 0x7290
#define PCI_CHIP_RV560_7291 0x7291
#define PCI_CHIP_RV560_7293 0x7293
#define PCI_CHIP_RV560_7297 0x7297
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
#define PCI_CHIP_RS690_791E 0x791E
#define PCI_CHIP_RS690_791F 0x791F
#define PCI_CHIP_RS600_793F 0x793F
#define PCI_CHIP_RS600_7941 0x7941
#define PCI_CHIP_RS600_7942 0x7942
#define PCI_CHIP_RS740_796C 0x796C
#define PCI_CHIP_RS740_796D 0x796D
#define PCI_CHIP_RS740_796E 0x796E
#define PCI_CHIP_RS740_796F 0x796F
#define PCI_CHIP_R600_9400 0x9400
#define PCI_CHIP_R600_9401 0x9401
#define PCI_CHIP_R600_9402 0x9402
#define PCI_CHIP_R600_9403 0x9403
#define PCI_CHIP_R600_9405 0x9405
#define PCI_CHIP_R600_940A 0x940A
#define PCI_CHIP_R600_940B 0x940B
#define PCI_CHIP_R600_940F 0x940F
#define PCI_CHIP_RV770_9440 0x9440
#define PCI_CHIP_RV770_9441 0x9441
#define PCI_CHIP_RV770_9442 0x9442
#define PCI_CHIP_RV610_94C0 0x94C0
#define PCI_CHIP_RV610_94C1 0x94C1
#define PCI_CHIP_RV610_94C3 0x94C3
#define PCI_CHIP_RV610_94C4 0x94C4
#define PCI_CHIP_RV610_94C5 0x94C5
#define PCI_CHIP_RV610_94C6 0x94C6
#define PCI_CHIP_RV610_94C7 0x94C7
#define PCI_CHIP_RV610_94C8 0x94C8
#define PCI_CHIP_RV610_94C9 0x94C9
#define PCI_CHIP_RV610_94CB 0x94CB
#define PCI_CHIP_RV610_94CC 0x94CC
#define PCI_CHIP_RV670_9500 0x9500
#define PCI_CHIP_RV670_9501 0x9501
#define PCI_CHIP_RV670_9505 0x9505
#define PCI_CHIP_RV670_9507 0x9507
#define PCI_CHIP_RV670_950F 0x950F
#define PCI_CHIP_RV670_9511 0x9511
#define PCI_CHIP_RV670_9515 0x9515
#define PCI_CHIP_RV630_9580 0x9580
#define PCI_CHIP_RV630_9581 0x9581
#define PCI_CHIP_RV630_9583 0x9583
#define PCI_CHIP_RV630_9586 0x9586
#define PCI_CHIP_RV630_9587 0x9587
#define PCI_CHIP_RV630_9588 0x9588
#define PCI_CHIP_RV630_9589 0x9589
#define PCI_CHIP_RV630_958A 0x958A
#define PCI_CHIP_RV630_958B 0x958B
#define PCI_CHIP_RV630_958C 0x958C
#define PCI_CHIP_RV630_958D 0x958D
#define PCI_CHIP_RV630_958E 0x958E
#define PCI_CHIP_RV620_95C0 0x95C0
#define PCI_CHIP_RV620_95C5 0x95C5
#define PCI_CHIP_RV620_95C7 0x95C7
#define PCI_CHIP_RV620_95C2 0x95C2
#define PCI_CHIP_RV620_95C4 0x95C4
#define PCI_CHIP_RV620_95CD 0x95CD
#define PCI_CHIP_RV620_95CE 0x95CE
#define PCI_CHIP_RV620_95CF 0x95CF
#define PCI_CHIP_RV635_9590 0x9590
#define PCI_CHIP_RV635_9596 0x9596
#define PCI_CHIP_RV635_9597 0x9597
#define PCI_CHIP_RV635_9598 0x9598
#define PCI_CHIP_RV635_9599 0x9599
#define PCI_CHIP_RV635_9591 0x9591
#define PCI_CHIP_RV635_9593 0x9593
#define PCI_CHIP_RS780_9610 0x9610
#define PCI_CHIP_RS780_9611 0x9611
#define PCI_CHIP_RS780_9612 0x9612
#define PCI_CHIP_RS780_9613 0x9613

/programs/system/drivers/ati2d/init.c
1,7 → 1,6
static Bool
rhdMapMMIO(RHDPtr rhdPtr)
static Bool rhdMapMMIO(RHDPtr rhdPtr)
{
rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
13,6 → 12,424
return 1;
}
/* Read MC register */
unsigned INMC(RHDPtr info, int addr)
{
u32_t data;
if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
data = INREG(RS690_MC_DATA);
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
data = INREG(RS600_MC_DATA);
} else if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
(void)INREG(AVIVO_MC_INDEX);
data = INREG(AVIVO_MC_DATA);
OUTREG(AVIVO_MC_INDEX, 0);
(void)INREG(AVIVO_MC_INDEX);
} else {
OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
(void)INREG(R300_MC_IND_INDEX);
data = INREG(R300_MC_IND_DATA);
OUTREG(R300_MC_IND_INDEX, 0);
(void)INREG(R300_MC_IND_INDEX);
}
return data;
}
#define LOC_FB 0x1
#define LOC_AGP 0x2
static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
{
if (info->ChipFamily >= CHIP_FAMILY_RV770) {
if (mask & LOC_FB)
*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
} else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (mask & LOC_FB)
*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RV515_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RS600_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RS690_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if (info->ChipFamily >= CHIP_FAMILY_R520) {
if (mask & LOC_FB)
*fb_loc = INMC(info, R520_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, R520_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else {
if (mask & LOC_FB)
*fb_loc = INREG(RADEON_MC_FB_LOCATION);
if (mask & LOC_AGP)
*agp_loc = INREG(RADEON_MC_AGP_LOCATION);
}
}
static void RADEONInitMemoryMap(RHDPtr info)
{
u32_t mem_size;
u32_t aper_size;
radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
&info->mc_agp_location, &info->mc_agp_location_hi);
/* We shouldn't use info->videoRam here which might have been clipped
* but the real video RAM instead
*/
if (info->ChipFamily >= CHIP_FAMILY_R600){
mem_size = INREG(R600_CONFIG_MEMSIZE);
aper_size = INREG(R600_CONFIG_APER_SIZE);
}
else {
mem_size = INREG(RADEON_CONFIG_MEMSIZE);
aper_size = INREG(RADEON_CONFIG_APER_SIZE);
}
if (mem_size == 0)
mem_size = 0x800000;
/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
Novell bug 204882 + along with lots of ubuntu ones */
if (aper_size > mem_size)
mem_size = aper_size;
if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
(info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740)) {
if (info->IsIGP)
info->mc_fb_location = INREG(RADEON_NB_TOM);
else
{
u32_t aper0_base;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
aper0_base = INREG(R600_CONFIG_F0_BASE);
}
else {
aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
}
/* Recent chips have an "issue" with the memory controller, the
* location must be aligned to the size. We just align it down,
* too bad if we walk over the top of system memory, we don't
* use DMA without a remapped anyway.
* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
*/
if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
info->ChipFamily == CHIP_FAMILY_R300 ||
info->ChipFamily == CHIP_FAMILY_R350 ||
info->ChipFamily == CHIP_FAMILY_RV350 ||
info->ChipFamily == CHIP_FAMILY_RV380 ||
info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410)
aper0_base &= ~(mem_size - 1);
if ( info->ChipFamily >= CHIP_FAMILY_R600) {
info->mc_fb_location = (aper0_base >> 24) |
(((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
}
else {
info->mc_fb_location = (aper0_base >> 16) |
((aper0_base + mem_size - 1) & 0xffff0000U);
}
}
}
if (info->ChipFamily >= CHIP_FAMILY_R600) {
info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
}
else {
info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
}
/* Just disable the damn AGP apertures for now, it may be
* re-enabled later by the DRM
*/
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
}
else {
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
}
info->mc_agp_location = 0x003f0000;
}
else
info->mc_agp_location = 0xffffffc0;
dbgprintf("RADEONInitMemoryMap() : \n");
dbgprintf(" mem_size : 0x%08x\n", (unsigned)mem_size);
dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location);
}
static void RADEONGetVRamType(RHDPtr info)
{
u32_t tmp;
if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
info->IsDDR = TRUE;
else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
info->IsDDR = TRUE;
else
info->IsDDR = FALSE;
if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
(info->ChipFamily <= CHIP_FAMILY_RV635))
{
int chansize;
/* r6xx */
tmp = INREG(R600_RAMCFG);
if (tmp & R600_CHANSIZE_OVERRIDE)
chansize = 16;
else if (tmp & R600_CHANSIZE)
chansize = 64;
else
chansize = 32;
if (info->ChipFamily == CHIP_FAMILY_R600)
info->RamWidth = 8 * chansize;
else if (info->ChipFamily == CHIP_FAMILY_RV670)
info->RamWidth = 4 * chansize;
else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
(info->ChipFamily == CHIP_FAMILY_RV620))
info->RamWidth = chansize;
else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
(info->ChipFamily == CHIP_FAMILY_RV635))
info->RamWidth = 2 * chansize;
}
else if (info->ChipFamily == CHIP_FAMILY_RV515) {
/* rv515/rv550 */
tmp = INMC(info, RV515_MC_CNTL);
tmp &= RV515_MEM_NUM_CHANNELS_MASK;
switch (tmp) {
case 0: info->RamWidth = 64; break;
case 1: info->RamWidth = 128; break;
default: info->RamWidth = 128; break;
}
}
else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
(info->ChipFamily <= CHIP_FAMILY_RV570)){
/* r520/rv530/rv560/rv570/r580 */
tmp = INMC(info, R520_MC_CNTL0);
switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
case 0: info->RamWidth = 32; break;
case 1: info->RamWidth = 64; break;
case 2: info->RamWidth = 128; break;
case 3: info->RamWidth = 256; break;
default: info->RamWidth = 64; break;
}
if (tmp & R520_MC_CHANNEL_SIZE) {
info->RamWidth *= 2;
}
}
else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
(info->ChipFamily <= CHIP_FAMILY_RV410)) {
/* r3xx, r4xx */
tmp = INREG(RADEON_MEM_CNTL);
tmp &= R300_MEM_NUM_CHANNELS_MASK;
switch (tmp) {
case 0: info->RamWidth = 64; break;
case 1: info->RamWidth = 128; break;
case 2: info->RamWidth = 256; break;
default: info->RamWidth = 128; break;
}
}
else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200)){
tmp = INREG(RADEON_MEM_CNTL);
if (tmp & RV100_HALF_MODE)
info->RamWidth = 32;
else
info->RamWidth = 64;
/// if (!info->HasCRTC2) {
/// info->RamWidth /= 4;
/// info->IsDDR = TRUE;
/// }
}
else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
tmp = INREG(RADEON_MEM_CNTL);
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
info->RamWidth = 128;
else
info->RamWidth = 64;
} else {
/* newer IGPs */
info->RamWidth = 128;
}
/* This may not be correct, as some cards can have half of channel disabled
* ToDo: identify these cases
*/
}
/*
* Depending on card genertation, chipset bugs, etc... the amount of vram
* accessible to the CPU can vary. This function is our best shot at figuring
* it out. Returns a value in KB.
*/
static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
{
u32_t aper_size;
unsigned char byte;
if (info->ChipFamily >= CHIP_FAMILY_R600)
aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
else
aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
/* Set HDP_APER_CNTL only on cards that are known not to be broken,
* that is has the 2nd generation multifunction PCI interface
*/
if (info->ChipFamily == CHIP_FAMILY_RV280 ||
info->ChipFamily == CHIP_FAMILY_RV350 ||
info->ChipFamily == CHIP_FAMILY_RV380 ||
info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410 ||
IS_AVIVO_VARIANT) {
MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
~RADEON_HDP_APER_CNTL);
dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
return aper_size * 2;
}
/* Older cards have all sorts of funny issues to deal with. First
* check if it's a multifunction card by reading the PCI config
* header type... Limit those to one aperture size
*/
// PCI_READ_BYTE(info->PciInfo, &byte, 0xe);
// if (byte & 0x80) {
// xf86DrvMsg(pScrn->scrnIndex, X_INFO,
// "Generation 1 PCI interface in multifunction mode"
// ", accessible memory limited to one aperture\n");
// return aper_size;
// }
/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
* have set it up. We don't write this as it's broken on some ASICs but
* we expect the BIOS to have done the right thing (might be too optimistic...)
*/
// if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
// return aper_size * 2;
return aper_size;
}
static Bool RADEONPreInitVRAM(RHDPtr info)
{
u32_t accessible, bar_size;
if ((!IS_AVIVO_VARIANT) && info->IsIGP)
{
u32_t tom = INREG(RADEON_NB_TOM);
info->videoRam = (((tom >> 16) -
(tom & 0xffff) + 1) << 6);
OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
}
else
{
if (info->ChipFamily >= CHIP_FAMILY_R600)
info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
else
{
/* Read VRAM size from card */
info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
/* Some production boards of m6 will return 0 if it's 8 MB */
if (info->videoRam == 0)
{
info->videoRam = 8192;
OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
}
}
}
RADEONGetVRamType(info);
/* Get accessible memory */
accessible = RADEONGetAccessibleVRAM(info);
/* Crop it to the size of the PCI BAR */
// bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
if (bar_size == 0)
bar_size = 0x20000;
if (accessible > bar_size)
accessible = bar_size;
dbgprintf("Detected total video RAM=%dK width=%dbit,"
"accessible=%uK (PCI BAR=%uK)\n",
info->videoRam, info->RamWidth,
(unsigned)accessible, (unsigned)bar_size);
if (info->videoRam > accessible)
info->videoRam = accessible;
if (!IS_AVIVO_VARIANT)
info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
info->BusCntl = INREG(RADEON_BUS_CNTL);
info->videoRam &= ~1023;
info->FbMapSize = info->videoRam * 1024;
/* if the card is PCI Express reserve the last 32k for the gart table */
// if (info->cardType == CARD_PCIE )
/* work out the size of pcie aperture */
// info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
// else
// info->FbSecureSize = 0;
return TRUE;
}
/*
#define RADEON_NB_TOM 0x15c
static size_t rhdGetVideoRamSize(RHDPtr rhdPtr)
19,7 → 436,7
{
size_t RamSize, BARSize;
if (rhdPtr->ChipSet == RHD_RS690)
if (rhdPtr->ChipFamily == CHIP_FAMILY_RS690)
RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE))>>10;
else
if (rhdPtr->IsIGP)
30,7 → 447,7
}
else
{
if (rhdPtr->ChipSet < RHD_R600)
if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
{
RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE)) >> 10;
if(RamSize==0) RamSize=8192;
52,7 → 469,9
}
else return RamSize;
}
*/
#if 0
static Bool
rhdMapFB(RHDPtr rhdPtr)
{
67,7 → 486,7
/* These devices have an internal address reference, which some other
* address registers in there also use. This can be different from the
* address in the BAR */
if (rhdPtr->ChipSet < RHD_R600)
if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, HDP_FB_LOCATION)<< 16;
else
rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE);
82,7 → 501,80
// dbgprintf("Mapped FB at %p (size 0x%08X)\n",rhdPtr->FbBase, rhdPtr->FbMapSize);
return TRUE;
}
#endif
static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
{
u32_t cmd_stat;
rhdPtr->ChipErrata = 0;
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
== RADEON_CFG_ATI_REV_A11))
rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
rhdPtr->cardType = CARD_PCI;
cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
if (cmd_stat & RADEON_CAP_LIST)
{
u32_t cap_ptr, cap_id;
cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
cap_ptr &= RADEON_CAP_PTR_MASK;
while(cap_ptr != RADEON_CAP_ID_NULL)
{
cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
rhdPtr->cardType = CARD_AGP;
break;
}
if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
rhdPtr->cardType = CARD_PCIE;
break;
}
cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
}
}
dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
(rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
/* treat PCIE IGP cards as PCI */
if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
rhdPtr->cardType = CARD_PCI;
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
(rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
rhdPtr->has_tcl = FALSE;
else {
rhdPtr->has_tcl = TRUE;
}
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
return TRUE;
}
Bool RHDPreInit()
{
/* We need access to IO space already */
91,7 → 583,15
return FALSE;
};
rhd.videoRam = rhdGetVideoRamSize(&rhd);
if( !RADEONPreInitChipType(&rhd))
return FALSE;
if (!RADEONPreInitVRAM(&rhd))
return FALSE;
RADEONInitMemoryMap(&rhd);
if (!rhd.videoRam)
{
dbgprintf("No Video RAM detected.\n");
102,13 → 602,14
rhd.FbFreeStart = 0;
rhd.FbFreeSize = rhd.videoRam << 10;
if( !rhdMapFB(&rhd))
return FALSE;
// if( !rhdMapFB(&rhd))
// return FALSE;
rhd.FbScanoutStart = 0;
rhd.FbScanoutSize = 8*1024*1024;
// rhd.FbScanoutStart = 0;
// rhd.FbScanoutSize = 8*1024*1024;
rhd.FbFreeStart = 10*1024*1024;
rhd.FbFreeSize = rhd.FbMapSize - 10*1024*1024;
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart;
rhdInitHeap(&rhd);
return TRUE;

/programs/system/drivers/ati2d/pci.c
1,304 → 1,10
SymTabRec RHDChipsets[] = {
/* R500 */
{ RHD_RV505, "RV505" },
{ RHD_RV515, "RV515" },
{ RHD_RV516, "RV516" },
{ RHD_R520, "R520" },
{ RHD_RV530, "RV530" },
{ RHD_RV535, "RV535" },
{ RHD_RV550, "RV550" },
{ RHD_RV560, "RV560" },
{ RHD_RV570, "RV570" },
{ RHD_R580, "R580" },
/* R500 Mobility */
{ RHD_M52, "M52" },
{ RHD_M54, "M54" },
{ RHD_M56, "M56" },
{ RHD_M58, "M58" },
{ RHD_M62, "M62" },
{ RHD_M64, "M64" },
{ RHD_M66, "M66" },
{ RHD_M68, "M68" },
{ RHD_M71, "M71" },
/* R500 integrated */
{ RHD_RS600, "RS600" },
{ RHD_RS690, "RS690" },
{ RHD_RS740, "RS740" },
/* R600 */
{ RHD_R600, "R600" },
{ RHD_RV610, "RV610" },
{ RHD_RV630, "RV630" },
/* R600 Mobility */
{ RHD_M72, "M72" },
{ RHD_M74, "M74" },
{ RHD_M76, "M76" },
/* RV670 came into existence after RV6x0 and M7x */
{ RHD_RV670, "RV670" },
{ RHD_R680, "R680" },
{ RHD_RV620, "RV620" },
{ RHD_RV635, "RV635" },
{ -1, NULL }
};
#include "ati_pciids_gen.h"
#include "radeon_chipset_gen.h"
#include "radeon_chipinfo_gen.h"
static struct rhdChipsetMapStruct {
enum RHD_FAMILIES family;
Bool IGP;
} rhdChipsetMap[] = {
{ RHD_FAMILY_UNKNOWN, 0 }, /* RHD_UNKNOWN */
{ RHD_FAMILY_R300, 0 }, /* RHD_R300 */
{ RHD_FAMILY_R350, 0 }, /* RHD_R350 */
{ RHD_FAMILY_RV350, 0 }, /* RHD_RV350 */
{ RHD_FAMILY_RV380, 0 }, /* RHD_RV370 */
{ RHD_FAMILY_RV380, 0 }, /* RHD_RV380 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_RV505 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_RV515 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_RV516 */
{ RHD_FAMILY_R520, 0 }, /* RHD_R520 */
{ RHD_FAMILY_RV530, 0 }, /* RHD_RV530 */
{ RHD_FAMILY_RV530, 0 }, /* RHD_RV535 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_RV550 */
{ RHD_FAMILY_RV560, 0 }, /* RHD_RV560 */
{ RHD_FAMILY_RV570, 0 }, /* RHD_RV570 */
{ RHD_FAMILY_R580, 0 }, /* RHD_R580 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_M52 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_M54 */
{ RHD_FAMILY_RV530, 0 }, /* RHD_M56 */
{ RHD_FAMILY_R520, 0 }, /* RHD_M58 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_M62 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_M64 */
{ RHD_FAMILY_RV530, 0 }, /* RHD_M66 */
{ RHD_FAMILY_R580, 0 }, /* RHD_M68 */
{ RHD_FAMILY_RV515, 0 }, /* RHD_M71 */
{ RHD_FAMILY_RS690, 1 }, /* RHD_RS600 */
{ RHD_FAMILY_RS690, 1 }, /* RHD_RS690 */
{ RHD_FAMILY_RS690, 1 }, /* RHD_RS740 */
{ RHD_FAMILY_R600, 0 }, /* RHD_R600 */
{ RHD_FAMILY_RV610, 0 }, /* RHD_RV610 */
{ RHD_FAMILY_RV630, 0 }, /* RHD_RV630 */
{ RHD_FAMILY_RV610, 0 }, /* RHD_M72 */
{ RHD_FAMILY_RV610, 0 }, /* RHD_M74 */
{ RHD_FAMILY_RV630, 0 }, /* RHD_M76 */
{ RHD_FAMILY_RV670, 0 }, /* RHD_RV670 */
{ RHD_FAMILY_RV670, 0 }, /* RHD_R680 */
{ RHD_FAMILY_RV620, 0 }, /* RHD_RV620 */
{ RHD_FAMILY_RV620, 0 }, /* RHD_M82 */
{ RHD_FAMILY_RV635, 0 }, /* RHD_RV635 */
{ RHD_FAMILY_UNKNOWN, 0 }, /* RHD_M86 */
{ RHD_FAMILY_RS780, 1 } /* RHD_RS780 */
/* RHD_CHIP_END */
};
# define RHD_DEVICE_MATCH(d, i) { (d),(i) }
# define PCI_ID_LIST PciChipset_t RHDPCIchipsets[]
# define LIST_END { 0, 0}
const PCI_ID_LIST = {
RHD_DEVICE_MATCH( 0x4144, RHD_R300 ), /* ATI Radeon 9500 */
RHD_DEVICE_MATCH( 0x4145, RHD_R300 ), /* ATI Radeon 9500 */
RHD_DEVICE_MATCH( 0x4146, RHD_R300 ), /* ATI Radeon 9600TX */
RHD_DEVICE_MATCH( 0x4147, RHD_R300 ), /* ATI FireGL Z1 */
RHD_DEVICE_MATCH( 0x4148, RHD_R350 ), /* ATI Radeon 9800SE */
RHD_DEVICE_MATCH( 0x4149, RHD_R350 ), /* ATI Radeon 9800 */
RHD_DEVICE_MATCH( 0x414A, RHD_R350 ), /* ATI Radeon 9800 */
RHD_DEVICE_MATCH( 0x414B, RHD_R350 ), /* ATI FireGL X2 */
RHD_DEVICE_MATCH( 0x4150, RHD_RV350 ), /* ATI Radeon 9600 */
RHD_DEVICE_MATCH( 0x4151, RHD_RV350 ), /* ATI Radeon 9600SE */
RHD_DEVICE_MATCH( 0x4152, RHD_RV350 ), /* ATI Radeon 9600XT */
RHD_DEVICE_MATCH( 0x4153, RHD_RV350 ), /* ATI Radeon 9600 */
RHD_DEVICE_MATCH( 0x4154, RHD_RV350 ), /* ATI FireGL T2 */
RHD_DEVICE_MATCH( 0x4155, RHD_RV350 ), /* ATI Radeon 9650 */
RHD_DEVICE_MATCH( 0x4156, RHD_RV350 ), /* ATI FireGL RV360 */
RHD_DEVICE_MATCH( 0x4E44, RHD_R300 ),
RHD_DEVICE_MATCH( 0x4E45, RHD_R300 ),
RHD_DEVICE_MATCH( 0x4E46, RHD_R300 ),
RHD_DEVICE_MATCH( 0x4E47, RHD_R300 ),
RHD_DEVICE_MATCH( 0x4E48, RHD_R350 ),
RHD_DEVICE_MATCH( 0x4E49, RHD_R350 ),
RHD_DEVICE_MATCH( 0x4E4A, RHD_R350 ),
RHD_DEVICE_MATCH( 0x4E4B, RHD_R350 ),
RHD_DEVICE_MATCH( 0x4E50, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x4E51, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x4E52, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x4E53, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x4E54, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x4E56, RHD_RV350 ),
RHD_DEVICE_MATCH( 0x5B60, RHD_RV380 ),
RHD_DEVICE_MATCH( 0x5B62, RHD_RV380 ),
RHD_DEVICE_MATCH( 0x5B63, RHD_RV380 ),
RHD_DEVICE_MATCH( 0x5B64, RHD_RV380 ),
RHD_DEVICE_MATCH( 0x5B65, RHD_RV380 ),
RHD_DEVICE_MATCH( 0x7100, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x7101, RHD_M58 ), /* Mobility Radeon X1800 XT */
RHD_DEVICE_MATCH( 0x7102, RHD_M58 ), /* Mobility Radeon X1800 */
RHD_DEVICE_MATCH( 0x7103, RHD_M58 ), /* Mobility FireGL V7200 */
RHD_DEVICE_MATCH( 0x7104, RHD_R520 ), /* FireGL V7200 */
RHD_DEVICE_MATCH( 0x7105, RHD_R520 ), /* FireGL V5300 */
RHD_DEVICE_MATCH( 0x7106, RHD_M58 ), /* Mobility FireGL V7100 */
RHD_DEVICE_MATCH( 0x7108, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x7109, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x710A, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x710B, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x710C, RHD_R520 ), /* Radeon X1800 */
RHD_DEVICE_MATCH( 0x710E, RHD_R520 ), /* FireGL V7300 */
RHD_DEVICE_MATCH( 0x710F, RHD_R520 ), /* FireGL V7350 */
RHD_DEVICE_MATCH( 0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */
RHD_DEVICE_MATCH( 0x7141, RHD_RV505 ), /* RV505 */
RHD_DEVICE_MATCH( 0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */
RHD_DEVICE_MATCH( 0x7143, RHD_RV505 ), /* Radeon X1550 */
RHD_DEVICE_MATCH( 0x7144, RHD_M54 ), /* M54-GL */
RHD_DEVICE_MATCH( 0x7145, RHD_M54 ), /* Mobility Radeon X1400 */
RHD_DEVICE_MATCH( 0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */
RHD_DEVICE_MATCH( 0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */
RHD_DEVICE_MATCH( 0x7149, RHD_M52 ), /* Mobility Radeon X1300 */
RHD_DEVICE_MATCH( 0x714A, RHD_M52 ), /* Mobility Radeon X1300 */
RHD_DEVICE_MATCH( 0x714B, RHD_M52 ), /* Mobility Radeon X1300 */
RHD_DEVICE_MATCH( 0x714C, RHD_M52 ), /* Mobility Radeon X1300 */
RHD_DEVICE_MATCH( 0x714D, RHD_RV515 ), /* Radeon X1300 */
RHD_DEVICE_MATCH( 0x714E, RHD_RV515 ), /* Radeon X1300 */
RHD_DEVICE_MATCH( 0x714F, RHD_RV505 ), /* RV505 */
RHD_DEVICE_MATCH( 0x7151, RHD_RV505 ), /* RV505 */
RHD_DEVICE_MATCH( 0x7152, RHD_RV515 ), /* FireGL V3300 */
RHD_DEVICE_MATCH( 0x7153, RHD_RV515 ), /* FireGL V3350 */
RHD_DEVICE_MATCH( 0x715E, RHD_RV515 ), /* Radeon X1300 */
RHD_DEVICE_MATCH( 0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */
RHD_DEVICE_MATCH( 0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */
RHD_DEVICE_MATCH( 0x7181, RHD_RV516 ), /* Radeon X1600 */
RHD_DEVICE_MATCH( 0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */
RHD_DEVICE_MATCH( 0x7186, RHD_M64 ), /* Mobility Radeon X1450 */
RHD_DEVICE_MATCH( 0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */
RHD_DEVICE_MATCH( 0x7188, RHD_M64 ), /* Mobility Radeon X2300 */
RHD_DEVICE_MATCH( 0x718A, RHD_M64 ), /* Mobility Radeon X2300 */
RHD_DEVICE_MATCH( 0x718B, RHD_M62 ), /* Mobility Radeon X1350 */
RHD_DEVICE_MATCH( 0x718C, RHD_M62 ), /* Mobility Radeon X1350 */
RHD_DEVICE_MATCH( 0x718D, RHD_M64 ), /* Mobility Radeon X1450 */
RHD_DEVICE_MATCH( 0x718F, RHD_RV516 ), /* Radeon X1300 */
RHD_DEVICE_MATCH( 0x7193, RHD_RV516 ), /* Radeon X1550 */
RHD_DEVICE_MATCH( 0x7196, RHD_M62 ), /* Mobility Radeon X1350 */
RHD_DEVICE_MATCH( 0x719B, RHD_RV516 ), /* FireMV 2250 */
RHD_DEVICE_MATCH( 0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */
RHD_DEVICE_MATCH( 0x71C0, RHD_RV530 ), /* Radeon X1600 */
RHD_DEVICE_MATCH( 0x71C1, RHD_RV535 ), /* Radeon X1650 */
RHD_DEVICE_MATCH( 0x71C2, RHD_RV530 ), /* Radeon X1600 */
RHD_DEVICE_MATCH( 0x71C3, RHD_RV535 ), /* Radeon X1600 */
RHD_DEVICE_MATCH( 0x71C4, RHD_M56 ), /* Mobility FireGL V5200 */
RHD_DEVICE_MATCH( 0x71C5, RHD_M56 ), /* Mobility Radeon X1600 */
RHD_DEVICE_MATCH( 0x71C6, RHD_RV530 ), /* Radeon X1650 */
RHD_DEVICE_MATCH( 0x71C7, RHD_RV535 ), /* Radeon X1650 */
RHD_DEVICE_MATCH( 0x71CD, RHD_RV530 ), /* Radeon X1600 */
RHD_DEVICE_MATCH( 0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */
RHD_DEVICE_MATCH( 0x71D2, RHD_RV530 ), /* FireGL V3400 */
RHD_DEVICE_MATCH( 0x71D4, RHD_M66 ), /* Mobility FireGL V5250 */
RHD_DEVICE_MATCH( 0x71D5, RHD_M66 ), /* Mobility Radeon X1700 */
RHD_DEVICE_MATCH( 0x71D6, RHD_M66 ), /* Mobility Radeon X1700 XT */
RHD_DEVICE_MATCH( 0x71DA, RHD_RV530 ), /* FireGL V5200 */
RHD_DEVICE_MATCH( 0x71DE, RHD_M66 ), /* Mobility Radeon X1700 */
RHD_DEVICE_MATCH( 0x7200, RHD_RV550 ), /* Radeon X2300HD */
RHD_DEVICE_MATCH( 0x7210, RHD_M71 ), /* Mobility Radeon HD 2300 */
RHD_DEVICE_MATCH( 0x7211, RHD_M71 ), /* Mobility Radeon HD 2300 */
RHD_DEVICE_MATCH( 0x7240, RHD_R580 ), /* Radeon X1950 */
RHD_DEVICE_MATCH( 0x7243, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7244, RHD_R580 ), /* Radeon X1950 */
RHD_DEVICE_MATCH( 0x7245, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7246, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7247, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7248, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7249, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x724A, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x724B, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x724C, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x724D, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x724E, RHD_R580 ), /* AMD Stream Processor */
RHD_DEVICE_MATCH( 0x724F, RHD_R580 ), /* Radeon X1900 */
RHD_DEVICE_MATCH( 0x7280, RHD_RV570 ), /* Radeon X1950 */
RHD_DEVICE_MATCH( 0x7281, RHD_RV560 ), /* RV560 */
RHD_DEVICE_MATCH( 0x7283, RHD_RV560 ), /* RV560 */
RHD_DEVICE_MATCH( 0x7284, RHD_M68 ), /* Mobility Radeon X1900 */
RHD_DEVICE_MATCH( 0x7287, RHD_RV560 ), /* RV560 */
RHD_DEVICE_MATCH( 0x7288, RHD_RV570 ), /* Radeon X1950 GT */
RHD_DEVICE_MATCH( 0x7289, RHD_RV570 ), /* RV570 */
RHD_DEVICE_MATCH( 0x728B, RHD_RV570 ), /* RV570 */
RHD_DEVICE_MATCH( 0x728C, RHD_RV570 ), /* ATI FireGL V7400 */
RHD_DEVICE_MATCH( 0x7290, RHD_RV560 ), /* RV560 */
RHD_DEVICE_MATCH( 0x7291, RHD_RV560 ), /* Radeon X1650 */
RHD_DEVICE_MATCH( 0x7293, RHD_RV560 ), /* Radeon X1650 */
RHD_DEVICE_MATCH( 0x7297, RHD_RV560 ), /* RV560 */
RHD_DEVICE_MATCH( 0x791E, RHD_RS690 ), /* Radeon X1200 */
RHD_DEVICE_MATCH( 0x791F, RHD_RS690 ), /* Radeon X1200 */
RHD_DEVICE_MATCH( 0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */
RHD_DEVICE_MATCH( 0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */
RHD_DEVICE_MATCH( 0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */
RHD_DEVICE_MATCH( 0x796C, RHD_RS740 ), /* RS740 */
RHD_DEVICE_MATCH( 0x796D, RHD_RS740 ), /* RS740M */
RHD_DEVICE_MATCH( 0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */
RHD_DEVICE_MATCH( 0x796F, RHD_RS740 ), /* RS740M */
RHD_DEVICE_MATCH( 0x9400, RHD_R600 ), /* Radeon HD 2900 XT */
RHD_DEVICE_MATCH( 0x9401, RHD_R600 ), /* Radeon HD 2900 XT */
RHD_DEVICE_MATCH( 0x9402, RHD_R600 ), /* Radeon HD 2900 XT */
RHD_DEVICE_MATCH( 0x9403, RHD_R600 ), /* Radeon HD 2900 Pro */
RHD_DEVICE_MATCH( 0x9405, RHD_R600 ), /* Radeon HD 2900 GT */
RHD_DEVICE_MATCH( 0x940A, RHD_R600 ), /* FireGL V8650 */
RHD_DEVICE_MATCH( 0x940B, RHD_R600 ), /* FireGL V8600 */
RHD_DEVICE_MATCH( 0x940F, RHD_R600 ), /* FireGL V7600 */
RHD_DEVICE_MATCH( 0x94C0, RHD_RV610 ), /* RV610 */
RHD_DEVICE_MATCH( 0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */
RHD_DEVICE_MATCH( 0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */
RHD_DEVICE_MATCH( 0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */
RHD_DEVICE_MATCH( 0x94C5, RHD_RV610 ), /* FireGL V4000 */
RHD_DEVICE_MATCH( 0x94C6, RHD_RV610 ), /* RV610 */
RHD_DEVICE_MATCH( 0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */
RHD_DEVICE_MATCH( 0x94C8, RHD_M74 ), /* Mobility Radeon HD 2400 XT */
RHD_DEVICE_MATCH( 0x94C9, RHD_M72 ), /* Mobility Radeon HD 2400 */
RHD_DEVICE_MATCH( 0x94CB, RHD_M72 ), /* ATI RADEON E2400 */
RHD_DEVICE_MATCH( 0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */
RHD_DEVICE_MATCH( 0x9500, RHD_RV670 ), /* RV670 */
RHD_DEVICE_MATCH( 0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */
RHD_DEVICE_MATCH( 0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */
RHD_DEVICE_MATCH( 0x9507, RHD_RV670 ), /* RV670 */
RHD_DEVICE_MATCH( 0x950F, RHD_R680 ), /* ATI Radeon HD3870 X2 */
RHD_DEVICE_MATCH( 0x9511, RHD_RV670 ), /* ATI FireGL V7700 */
RHD_DEVICE_MATCH( 0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */
RHD_DEVICE_MATCH( 0x9580, RHD_RV630 ), /* RV630 */
RHD_DEVICE_MATCH( 0x9581, RHD_M76 ), /* Mobility Radeon HD 2600 */
RHD_DEVICE_MATCH( 0x9583, RHD_M76 ), /* Mobility Radeon HD 2600 XT */
RHD_DEVICE_MATCH( 0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */
RHD_DEVICE_MATCH( 0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */
RHD_DEVICE_MATCH( 0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */
RHD_DEVICE_MATCH( 0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */
RHD_DEVICE_MATCH( 0x958A, RHD_RV630 ), /* Gemini RV630 */
RHD_DEVICE_MATCH( 0x958B, RHD_M76 ), /* Gemini ATI Mobility Radeon HD 2600 XT */
RHD_DEVICE_MATCH( 0x958C, RHD_RV630 ), /* FireGL V5600 */
RHD_DEVICE_MATCH( 0x958D, RHD_RV630 ), /* FireGL V3600 */
RHD_DEVICE_MATCH( 0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */
RHD_DEVICE_MATCH( 0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
RHD_DEVICE_MATCH( 0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */
RHD_DEVICE_MATCH( 0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */
RHD_DEVICE_MATCH( 0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
RHD_DEVICE_MATCH( 0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */
RHD_DEVICE_MATCH( 0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
RHD_DEVICE_MATCH( 0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */
RHD_DEVICE_MATCH( 0x95C2, RHD_M82 ), /* ATI Mobility Radeon HD 3430 (M82) */
RHD_DEVICE_MATCH( 0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82) */
RHD_DEVICE_MATCH( 0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */
RHD_DEVICE_MATCH( 0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */
RHD_DEVICE_MATCH( 0x95CD, RHD_RV620 ), /* ATI FireMV 2450 */
RHD_DEVICE_MATCH( 0x95CE, RHD_RV620 ), /* ATI FireMV 2260 */
RHD_DEVICE_MATCH( 0x95CF, RHD_RV620 ), /* ATI FireMV 2260 */
LIST_END
};
const char *
xf86TokenToString(SymTabPtr table, int token)
{
312,9 → 18,23
return(table[i].name);
}
const RADEONCardInfo *RadeonDevMatch(u16_t dev,const RADEONCardInfo *list)
{
while(list->pci_device_id)
{
if(dev == list->pci_device_id)
return list;
list++;
}
return 0;
}
RHDPtr FindPciDevice()
{
const PciChipset_t *dev;
const RADEONCardInfo *dev;
u32_t bus, last_bus;
if( (last_bus = PciApi(1))==-1)
332,18 → 52,28
if( (u16_t)id != VENDOR_ATI)
continue;
if( (dev=PciDevMatch(id>>16,RHDPCIchipsets))!=NULL)
rhd.PciDeviceID = (id>>16);
if( (dev = RadeonDevMatch(rhd.PciDeviceID, RADEONCards))!=NULL)
{
u32_t reg2C;
int i;
rhd.PciDeviceID = (id>>16);
rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID);
if (!rhd.chipset)
{
dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID);
return FALSE;
}
dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",rhd.chipset,rhd.PciDeviceID);
rhd.bus = bus;
rhd.devfn = devfn;
rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
rhd.ChipSet = dev->ChipSet;
rhd.ChipFamily = dev->chip_family;
rhd.IsMobility = dev->mobility;
rhd.IsIGP = dev->igp;
reg2C = PciRead32(bus,devfn, 0x2C);
350,6 → 80,10
rhd.subvendor_id = reg2C & 0xFFFF;;
rhd.subdevice_id = reg2C >> 16;
if (rhd.ChipFamily >= CHIP_FAMILY_R600)
dbgprintf("R600 unsupported yet.\nExit\n");
for (i = 0; i < 6; i++)
{
u32_t base;
371,8 → 105,6
}
rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize);
}
rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID);
return &rhd;
}
};
380,16 → 112,6
return NULL;
}
const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list)
{
while(list->device)
{
if(dev==list->device)
return list;
list++;
}
return 0;
}
u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)

/programs/system/drivers/ati2d/pixmap.inc
41,7 → 41,7
if (mapped = UserAlloc(size))
{
CommitPages(mapped, ((u32_t)local+rhd.PhisBase)|7|(1<<9), size);
CommitPages(mapped, ((u32_t)local+rhd.LinearAddr)|7|(1<<9), size);
io->mapped = mapped;
io->pitch = pitch;
53,7 → 53,7
pixmap->flags = io->flags;
pixmap->pitch = pitch;
pixmap->mapped = mapped;
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.FbIntAddress)>>10);
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10);
pixmap->local = local;
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset);

/programs/system/drivers/ati2d/r500.inc
80,7 → 80,7
* CLOCK_CNTL_INDEX register access. If not, register reads afterward
* may not be correct.
*/
if (rhd.ChipSet <= RHD_RV380)
if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
{
u32_t save, tmp;
312,13 → 312,11
R5xx2DIdleLocal();
switch(rhd.ChipSet)
switch(rhd.ChipFamily)
{
case RHD_R300:
case RHD_R350:
case RHD_RV350:
case RHD_RV370:
case RHD_RV380:
case CHIP_FAMILY_R300:
case CHIP_FAMILY_R350:
case CHIP_FAMILY_RV350:
dbgprintf("Loading R300 microcode\n");
for (i = 0; i < 256; i++)
{
326,7 → 324,7
OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
}
break;
/*
case RHD_RV505:
case RHD_RV515:
case RHD_RV516:
343,6 → 341,7
OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
}
*/
}
safe_sti(ifl);
};
379,8 → 378,7
dbgprintf("gui_control %x \n", rhd.gui_control);
rhd.surface_cntl = 0;
rhd.dst_pitch_offset = ((screenpitch / 64) << 22) |
((rhd.FbIntAddress + rhd.FbScanoutStart) >> 10);
rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10);
dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
389,7 → 387,7
scr_pixmap.height = rhd.displayHeight;
scr_pixmap.format = PICT_a8r8g8b8;
scr_pixmap.pitch = screenpitch;
scr_pixmap.local = (void*)rhd.FbIntAddress;
scr_pixmap.local = (void*)rhd.fbLocation;
scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
scr_pixmap.mapped = (void*)0;

/programs/system/drivers/ati2d/radeon_chipinfo_gen.h
0,0 → 1,306
/* This file is autogenerated please do not edit */
RADEONCardInfo RADEONCards[] = {
{ 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 },
{ 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
{ 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
{ 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 },
{ 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
{ 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
{ 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 },
{ 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
{ 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 },
{ 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
{ 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
{ 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
{ 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
{ 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
{ 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
{ 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
{ 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
{ 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
{ 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
{ 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
{ 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
{ 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
{ 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
{ 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
{ 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
{ 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
{ 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
{ 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
{ 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
{ 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
{ 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
{ 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
{ 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
{ 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
{ 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
{ 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
{ 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
{ 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
{ 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },
{ 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
{ 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
{ 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
{ 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
{ 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
{ 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
{ 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
{ 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
{ 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
{ 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
{ 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
{ 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
{ 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
{ 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
{ 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 },
{ 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 },
{ 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
{ 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
{ 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 },
{ 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
{ 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
{ 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
{ 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 },
{ 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 },
{ 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
{ 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
{ 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
{ 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 },
{ 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
{ 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
{ 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 },
{ 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
{ 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
{ 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
{ 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 },
{ 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x9590, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9596, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9597, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9598, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
};

/programs/system/drivers/ati2d/radeon_chipset_gen.h
0,0 → 1,307
/* This file is autogenerated please do not edit */
static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
{ PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" },
{ PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
{ PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" },
{ PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
{ PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" },
{ PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" },
{ PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" },
{ PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" },
{ PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" },
{ PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" },
{ PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" },
{ PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" },
{ PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" },
{ PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" },
{ PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" },
{ PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" },
{ PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" },
{ PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" },
{ PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" },
{ PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" },
{ PCI_CHIP_RV350_4155, "ATI Radeon 9650" },
{ PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" },
{ PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" },
{ PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" },
{ PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" },
{ PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" },
{ PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
{ PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" },
{ PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" },
{ PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" },
{ PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" },
{ PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" },
{ PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" },
{ PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" },
{ PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" },
{ PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" },
{ PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" },
{ PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" },
{ PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" },
{ PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" },
{ PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" },
{ PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" },
{ PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
{ PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" },
{ PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" },
{ PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" },
{ PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" },
{ PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
{ PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
{ PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
{ PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" },
{ PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
{ PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" },
{ PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" },
{ PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" },
{ PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" },
{ PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" },
{ PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" },
{ PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" },
{ PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" },
{ PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" },
{ PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" },
{ PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" },
{ PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" },
{ PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" },
{ PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" },
{ PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" },
{ PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" },
{ PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" },
{ PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" },
{ PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" },
{ PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" },
{ PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" },
{ PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" },
{ PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" },
{ PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" },
{ PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" },
{ PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" },
{ PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" },
{ PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" },
{ PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" },
{ PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" },
{ PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" },
{ PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" },
{ PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" },
{ PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" },
{ PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" },
{ PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" },
{ PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" },
{ PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" },
{ PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" },
{ PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
{ PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
{ PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
{ PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" },
{ PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" },
{ PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" },
{ PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" },
{ PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
{ PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" },
{ PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" },
{ PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" },
{ PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" },
{ PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" },
{ PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" },
{ PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" },
{ PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" },
{ PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" },
{ PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" },
{ PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" },
{ PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" },
{ PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" },
{ PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" },
{ PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
{ PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
{ PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
{ PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
{ PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
{ PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
{ PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" },
{ PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" },
{ PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" },
{ PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" },
{ PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" },
{ PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" },
{ PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" },
{ PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" },
{ PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" },
{ PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" },
{ PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" },
{ PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" },
{ PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" },
{ PCI_CHIP_R520_7100, "ATI Radeon X1800" },
{ PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" },
{ PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" },
{ PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" },
{ PCI_CHIP_R520_7104, "ATI FireGL V7200" },
{ PCI_CHIP_R520_7105, "ATI FireGL V5300" },
{ PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" },
{ PCI_CHIP_R520_7108, "ATI Radeon X1800" },
{ PCI_CHIP_R520_7109, "ATI Radeon X1800" },
{ PCI_CHIP_R520_710A, "ATI Radeon X1800" },
{ PCI_CHIP_R520_710B, "ATI Radeon X1800" },
{ PCI_CHIP_R520_710C, "ATI Radeon X1800" },
{ PCI_CHIP_R520_710E, "ATI FireGL V7300" },
{ PCI_CHIP_R520_710F, "ATI FireGL V7350" },
{ PCI_CHIP_RV515_7140, "ATI Radeon X1600" },
{ PCI_CHIP_RV515_7141, "ATI RV505" },
{ PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" },
{ PCI_CHIP_RV515_7143, "ATI Radeon X1550" },
{ PCI_CHIP_RV515_7144, "ATI M54-GL" },
{ PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" },
{ PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" },
{ PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" },
{ PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" },
{ PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" },
{ PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" },
{ PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" },
{ PCI_CHIP_RV515_714D, "ATI Radeon X1300" },
{ PCI_CHIP_RV515_714E, "ATI Radeon X1300" },
{ PCI_CHIP_RV515_714F, "ATI RV505" },
{ PCI_CHIP_RV515_7151, "ATI RV505" },
{ PCI_CHIP_RV515_7152, "ATI FireGL V3300" },
{ PCI_CHIP_RV515_7153, "ATI FireGL V3350" },
{ PCI_CHIP_RV515_715E, "ATI Radeon X1300" },
{ PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" },
{ PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" },
{ PCI_CHIP_RV515_7181, "ATI Radeon X1600" },
{ PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" },
{ PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" },
{ PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" },
{ PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" },
{ PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" },
{ PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" },
{ PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" },
{ PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" },
{ PCI_CHIP_RV515_718F, "ATI Radeon X1300" },
{ PCI_CHIP_RV515_7193, "ATI Radeon X1550" },
{ PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" },
{ PCI_CHIP_RV515_719B, "ATI FireMV 2250" },
{ PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" },
{ PCI_CHIP_RV530_71C0, "ATI Radeon X1600" },
{ PCI_CHIP_RV530_71C1, "ATI Radeon X1650" },
{ PCI_CHIP_RV530_71C2, "ATI Radeon X1600" },
{ PCI_CHIP_RV530_71C3, "ATI Radeon X1600" },
{ PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" },
{ PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" },
{ PCI_CHIP_RV530_71C6, "ATI Radeon X1650" },
{ PCI_CHIP_RV530_71C7, "ATI Radeon X1650" },
{ PCI_CHIP_RV530_71CD, "ATI Radeon X1600" },
{ PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" },
{ PCI_CHIP_RV530_71D2, "ATI FireGL V3400" },
{ PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" },
{ PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" },
{ PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" },
{ PCI_CHIP_RV530_71DA, "ATI FireGL V5200" },
{ PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" },
{ PCI_CHIP_RV515_7200, "ATI Radeon X2300HD" },
{ PCI_CHIP_RV515_7210, "ATI Mobility Radeon HD 2300" },
{ PCI_CHIP_RV515_7211, "ATI Mobility Radeon HD 2300" },
{ PCI_CHIP_R580_7240, "ATI Radeon X1950" },
{ PCI_CHIP_R580_7243, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7244, "ATI Radeon X1950" },
{ PCI_CHIP_R580_7245, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7246, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7247, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7248, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7249, "ATI Radeon X1900" },
{ PCI_CHIP_R580_724A, "ATI Radeon X1900" },
{ PCI_CHIP_R580_724B, "ATI Radeon X1900" },
{ PCI_CHIP_R580_724C, "ATI Radeon X1900" },
{ PCI_CHIP_R580_724D, "ATI Radeon X1900" },
{ PCI_CHIP_R580_724E, "ATI AMD Stream Processor" },
{ PCI_CHIP_R580_724F, "ATI Radeon X1900" },
{ PCI_CHIP_RV570_7280, "ATI Radeon X1950" },
{ PCI_CHIP_RV560_7281, "ATI RV560" },
{ PCI_CHIP_RV560_7283, "ATI RV560" },
{ PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" },
{ PCI_CHIP_RV560_7287, "ATI RV560" },
{ PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" },
{ PCI_CHIP_RV570_7289, "ATI RV570" },
{ PCI_CHIP_RV570_728B, "ATI RV570" },
{ PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" },
{ PCI_CHIP_RV560_7290, "ATI RV560" },
{ PCI_CHIP_RV560_7291, "ATI Radeon X1650" },
{ PCI_CHIP_RV560_7293, "ATI Radeon X1650" },
{ PCI_CHIP_RV560_7297, "ATI RV560" },
{ PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" },
{ PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" },
{ PCI_CHIP_RS690_791E, "ATI Radeon X1200" },
{ PCI_CHIP_RS690_791F, "ATI Radeon X1200" },
{ PCI_CHIP_RS600_793F, "ATI Radeon X1200" },
{ PCI_CHIP_RS600_7941, "ATI Radeon X1200" },
{ PCI_CHIP_RS600_7942, "ATI Radeon X1200" },
{ PCI_CHIP_RS740_796C, "ATI RS740" },
{ PCI_CHIP_RS740_796D, "ATI RS740M" },
{ PCI_CHIP_RS740_796E, "ATI RS740" },
{ PCI_CHIP_RS740_796F, "ATI RS740M" },
{ PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" },
{ PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" },
{ PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" },
{ PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" },
{ PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" },
{ PCI_CHIP_R600_940A, "ATI FireGL V8650" },
{ PCI_CHIP_R600_940B, "ATI FireGL V8600" },
{ PCI_CHIP_R600_940F, "ATI FireGL V7600" },
{ PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" },
{ PCI_CHIP_RV770_9441, "ATI Radeon HD 4870 x2" },
{ PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" },
{ PCI_CHIP_RV610_94C0, "ATI RV610" },
{ PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" },
{ PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" },
{ PCI_CHIP_RV610_94C4, "ATI Radeon HD 2400 PRO AGP" },
{ PCI_CHIP_RV610_94C5, "ATI FireGL V4000" },
{ PCI_CHIP_RV610_94C6, "ATI RV610" },
{ PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" },
{ PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" },
{ PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" },
{ PCI_CHIP_RV610_94CB, "ATI RADEON E2400" },
{ PCI_CHIP_RV610_94CC, "ATI RV610" },
{ PCI_CHIP_RV670_9500, "ATI RV670" },
{ PCI_CHIP_RV670_9501, "ATI Radeon HD3870" },
{ PCI_CHIP_RV670_9505, "ATI Radeon HD3850" },
{ PCI_CHIP_RV670_9507, "ATI RV670" },
{ PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" },
{ PCI_CHIP_RV670_9511, "ATI FireGL V7700" },
{ PCI_CHIP_RV670_9515, "ATI Radeon HD3850" },
{ PCI_CHIP_RV630_9580, "ATI RV630" },
{ PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
{ PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
{ PCI_CHIP_RV630_9586, "ATI Radeon HD 2600 XT AGP" },
{ PCI_CHIP_RV630_9587, "ATI Radeon HD 2600 Pro AGP" },
{ PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" },
{ PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" },
{ PCI_CHIP_RV630_958A, "ATI Gemini RV630" },
{ PCI_CHIP_RV630_958B, "ATI Gemini Mobility Radeon HD 2600 XT" },
{ PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
{ PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
{ PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" },
{ PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" },
{ PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" },
{ PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" },
{ PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" },
{ PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" },
{ PCI_CHIP_RV620_95CD, "ATI FireMV 2450" },
{ PCI_CHIP_RV620_95CE, "ATI FireMV 2260" },
{ PCI_CHIP_RV620_95CF, "ATI FireMV 2260" },
{ PCI_CHIP_RV635_9590, "ATI ATI Radeon HD 3600 Series" },
{ PCI_CHIP_RV635_9596, "ATI ATI Radeon HD 3650 AGP" },
{ PCI_CHIP_RV635_9597, "ATI ATI Radeon HD 3600 PRO" },
{ PCI_CHIP_RV635_9598, "ATI ATI Radeon HD 3600 XT" },
{ PCI_CHIP_RV635_9599, "ATI ATI Radeon HD 3600 PRO" },
{ PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" },
{ PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" },
{ PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" },
{ PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" },
{ PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" },
{ PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" },
{ -1, NULL }
};

/programs/system/drivers/ati2d/radeon_reg.h
1032,6 → 1032,10
#define RADEON_OV0_BASE_ADDR 0x43c
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
1458,6 → 1462,7
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_DSTCACHE_CTLSTAT 0x1714
#define RADEON_RB3D_ZCACHE_MODE 0x3250
#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
3184,6 → 3189,7
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
3417,6 → 3423,7
#define RS690_MC_AGP_LOCATION 0x101
#define RS690_MC_AGP_BASE 0x102
#define RS690_MC_AGP_BASE_2 0x103
#define RS690_MC_INIT_MISC_LAT_TIMER 0x104
#define RS690_MC_STATUS 0x90
#define RS690_MC_STATUS_IDLE (1 << 0)
3435,6 → 3442,7
#define R520_MC_STATUS_IDLE (1<<1)
#define RV515_MC_STATUS 0x08
#define RV515_MC_STATUS_IDLE (1<<4)
#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
#define AVIVO_MC_DATA 0x0074
#define RV515_MC_FB_LOCATION 0x1
3597,8 → 3605,20
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
#define AVIVO_D1MODE_DATA_FORMAT 0x6528
# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
3650,6 → 3670,8
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
3657,6 → 3679,7
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
#define AVIVO_D2SCL_UPDATE 0x6dcc
#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
3917,6 → 3940,8
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define R700_MC_VM_FB_LOCATION 0x2024
#define R600_HDP_NONSURFACE_BASE 0x2c04
#define R600_BUS_CNTL 0x5420
4233,7 → 4258,7
#define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc
#define R300_VAP_OUT_VTX_FMT_0 0x2090
# define R300_VTX_POS_PRESENT (1 << 0)
# define R300_VTX_COLOR_0_PRESENT (1 << 1)
4321,6 → 4346,7
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
#define R300_TX_FILTER0_1 0x4404
# define R300_TX_CLAMP_S(x) (x << 0)
# define R300_TX_CLAMP_T(x) (x << 3)
# define R300_TX_CLAMP_R(x) (x << 6)
4338,7 → 4364,9
# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_0 0x4440
#define R300_TX_FILTER1_1 0x4444
#define R300_TX_FORMAT0_0 0x4480
#define R300_TX_FORMAT0_1 0x4484
# define R300_TXWIDTH_SHIFT 0
# define R300_TXHEIGHT_SHIFT 11
# define R300_NUM_LEVELS_SHIFT 26
4346,6 → 4374,7
# define R300_TXPROJECTED (1 << 30)
# define R300_TXPITCH_EN (1 << 31)
#define R300_TX_FORMAT1_0 0x44c0
#define R300_TX_FORMAT1_1 0x44c4
# define R300_TX_FORMAT_X8 0x0
# define R300_TX_FORMAT_X16 0x1
# define R300_TX_FORMAT_Y4X4 0x2
4419,10 → 4448,12
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
#define R300_TX_FORMAT2_0 0x4500
#define R300_TX_FORMAT2_1 0x4504
# define R500_TXWIDTH_11 (1 << 15)
# define R500_TXHEIGHT_11 (1 << 16)
#define R300_TX_OFFSET_0 0x4540
#define R300_TX_OFFSET_1 0x4544
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
4499,6 → 4530,7
#define R300_US_TEX_INST_0 0x4620
#define R300_US_TEX_INST_1 0x4624
#define R300_US_TEX_INST_2 0x4628
#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
# define R300_TEX_SRC_ADDR(x) (x << 0)
# define R300_TEX_DST_ADDR(x) (x << 6)
# define R300_TEX_ID(x) (x << 11)
4511,11 → 4543,13
#define R300_US_ALU_RGB_ADDR_0 0x46c0
#define R300_US_ALU_RGB_ADDR_1 0x46c4
#define R300_US_ALU_RGB_ADDR_2 0x46c8
#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) (x << 0)
# define R300_ALU_RGB_ADDR1(x) (x << 6)
# define R300_ALU_RGB_ADDR2(x) (x << 12)
# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_RGB_ADDRD(x) (x << 18)
4525,6 → 4559,7
# define R300_ALU_RGB_MASK_R 1
# define R300_ALU_RGB_MASK_G 2
# define R300_ALU_RGB_MASK_B 4
# define R300_ALU_RGB_MASK_RGB 7
# define R300_ALU_RGB_TARGET_A (0 << 29)
# define R300_ALU_RGB_TARGET_B (1 << 29)
# define R300_ALU_RGB_TARGET_C (2 << 29)
4532,6 → 4567,7
#define R300_US_ALU_RGB_INST_0 0x48c0
#define R300_US_ALU_RGB_INST_1 0x48c4
#define R300_US_ALU_RGB_INST_2 0x48c8
#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
# define R300_ALU_RGB_SEL_A(x) (x << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
4603,11 → 4639,13
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
# define R300_ALU_ALPHA_ADDR1(x) (x << 6)
# define R300_ALU_ALPHA_ADDR2(x) (x << 12)
# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_ALPHA_ADDRD(x) (x << 18)
4623,6 → 4661,7
#define R300_US_ALU_ALPHA_INST_0 0x49c0
#define R300_US_ALU_ALPHA_INST_1 0x49c4
#define R300_US_ALU_ALPHA_INST_2 0x49c8
#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
4679,6 → 4718,15
# define R300_ALU_ALPHA_OMOD_DIV_8 6
# define R300_ALU_ALPHA_CLAMP (1 << 30)
#define R300_US_ALU_CONST_R_0 0x4c00
#define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)
#define R300_US_ALU_CONST_G_0 0x4c04
#define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)
#define R300_US_ALU_CONST_B_0 0x4c08
#define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)
#define R300_US_ALU_CONST_A_0 0x4c0c
#define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)
#define R300_FG_DEPTH_SRC 0x4bd8
#define R300_FG_FOG_BLEND 0x4bc0
#define R300_FG_ALPHA_FUNC 0x4bd4
4758,10 → 4806,11
/* R500 US has to be loaded through an index/data pair */
#define R500_GA_US_VECTOR_INDEX 0x4250
# define R500_US_VECTOR_INDEX(x) (x << 0)
# define R500_US_VECTOR_TYPE_INST (0 << 16)
# define R500_US_VECTOR_TYPE_CONST (1 << 16)
# define R500_US_VECTOR_CLAMP (1 << 17)
# define R500_US_VECTOR_INST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_INST)
# define R500_US_VECTOR_CONST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_CONST)
#define R500_GA_US_VECTOR_DATA 0x4254
/*

/programs/system/drivers/ati2d/syscall.h
54,6 → 54,7
///////////////////////////////////////////////////////////////////////////////
static u32_t PciApi(int cmd);
u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8");
60,10 → 61,18
u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16");
u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32");
#define pciReadLong(tag, reg) \
PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg))
u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8");
u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16");
u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32");
#define pciWriteLong(tag, reg, val) \
PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val))
///////////////////////////////////////////////////////////////////////////////
int dbg_open(char *path);

/programs/system/drivers/ati2d/types.h
11,9 → 11,9
typedef unsigned int count_t;
typedef unsigned int eflags_t;
typedef int bool;
typedef unsigned int Bool;
#define TRUE (bool)1
#define FALSE (bool)0
#define TRUE (Bool)1
#define FALSE (Bool)0