/kernel/trunk/const.inc |
---|
1,6 → 1,6 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
;; ;; |
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;; |
;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;; |
;; Distributed under terms of the GNU General Public License ;; |
;; ;; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
98,6 → 98,9 |
MSR_SYSENTER_CS equ 0x174 |
MSR_SYSENTER_ESP equ 0x175 |
MSR_SYSENTER_EIP equ 0x176 |
MSR_CR_PAT equ 0x277 |
MSR_MTRR_DEF_TYPE equ 0x2FF |
MSR_AMD_EFER equ 0xC0000080 ; Extended Feature Enable Register |
MSR_AMD_STAR equ 0xC0000081 ; SYSCALL/SYSRET Target Address Register |
276,7 → 279,9 |
PG_USER equ 0x004 |
PG_PCD equ 0x008 |
PG_PWT equ 0x010 |
PG_ACCESSED equ 0x020 |
PG_DIRTY equ 0x040 |
PG_PAT equ 0x080 |
PG_GLOBAL equ 0x100 |
PG_SHARED equ 0x200 |
287,6 → 292,18 |
PDE_LARGE equ 0x080 |
PAT_WB equ 0x000 |
PAT_WC equ 0x008 |
PAT_UCM equ 0x010 |
PAT_UC equ 0x018 |
PAT_TYPE_UC equ 0 |
PAT_TYPE_WC equ 1 |
PAT_TYPE_WB equ 6 |
PAT_TYPE_UCM equ 7 |
PAT_VALUE equ 0x00070106; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
;;;;;;;;;;;boot time variables |
BOOT_BPP equ 0x9000 ;byte bits per pixel |
/kernel/trunk/core/mtrr.inc |
---|
25,21 → 25,65 |
; Helper procedure for mtrr_reconfigure and set_mtrr, |
; called before changes in MTRRs. |
; 1. disable and flush caches |
; 2. clear PGE bit in cr4 |
; 3. flush TLB |
; 4. disable mtrr |
proc mtrr_begin_change |
mov eax, cr0 |
or eax, 0x60000000 ;disable caching |
mov cr0, eax |
wbinvd ;invalidate cache |
bt [cpu_caps], CAPS_PGE |
jnc .cr3_flush |
mov eax, cr4 |
btr eax, 7 ;clear cr4.PGE |
mov cr4, eax ;flush TLB |
jmp @F ;skip extra serialization |
.cr3_flush: |
mov eax, cr3 |
mov cr3, eax ;flush TLB |
@@: |
mov ecx, MSR_MTRR_DEF_TYPE |
rdmsr |
btr eax, 11 ;clear enable flag |
wrmsr ;disable mtrr |
ret |
endp |
; Helper procedure for mtrr_reconfigure and set_mtrr, |
; called after changes in MTRRs. |
; 1. enable mtrr |
; 2. flush all caches |
; 3. flush TLB |
; 4. restore cr4.PGE flag, if required |
proc mtrr_end_change |
mov ecx, MSR_MTRR_DEF_TYPE |
rdmsr |
or ah, 8 ; enable variable-ranges MTRR |
and al, 0xF0 ; default memtype = UC |
wrmsr |
wbinvd ;again invalidate |
mov eax, cr0 |
and eax, not 0x60000000 |
mov cr0, eax ; enable caching |
mov eax, cr3 |
mov cr3, eax ;flush tlb |
bt [cpu_caps], CAPS_PGE |
jnc @F |
mov eax, cr4 |
bts eax, 7 ;set cr4.PGE flag |
mov cr4, eax |
@@: |
ret |
endp |
695,12 → 739,15 |
jmp @b |
@@: |
; 9i. Configure MTRR_DEF_TYPE. |
mov ecx, 0x2FF |
rdmsr |
or ah, 8 ; enable variable-ranges MTRR |
and al, 0xF0; default memtype = UC |
; 9i. Check PAT support and reprogram PAT_MASR for write combining memory |
bt [cpu_caps], CAPS_PAT |
jnc @F |
mov ecx, MSR_CR_PAT |
mov eax, PAT_VALUE ;UC UCM WC WB |
mov edx, eax |
wrmsr |
@@: |
; 9j. Changes are done. |
call mtrr_end_change |
738,7 → 785,9 |
ret |
.found: |
; found, write values |
push ecx |
call mtrr_begin_change |
pop ecx |
xor edx, edx |
mov eax, [base] |
or eax, [mem_type] |
/kernel/trunk/data32.inc |
---|
219,8 → 219,6 |
align 4 |
pte_valid_mask dd 0xFFFFF000+PG_SHARED+PG_NOCACHE+PG_UWR |
keyboard dd 1 |
syslang dd 1 |
363,6 → 361,7 |
mst MEM_STATE |
pte_valid_mask rd 1 |
page_start rd 1 |
page_end rd 1 |
sys_page_map rd 1 |
/kernel/trunk/kernel.asm |
---|
351,17 → 351,26 |
mov fs, cx |
mov gs, bx |
xor eax, eax |
mov ebx, 0xFFFFF000+PG_SHARED+PG_NOCACHE+PG_UWR |
bt [cpu_caps], CAPS_PAT |
setc al |
shl eax, 7 |
or ebx, eax |
mov eax, PG_GLOBAL |
bt [cpu_caps], CAPS_PGE |
jnc @F |
or [sys_proc+PROC.pdt_0+(OS_BASE shr 20)], eax |
or [pte_valid_mask], eax |
or ebx, eax |
mov ebx, cr4 |
or ebx, CR4_PGE |
mov cr4, ebx |
mov eax, cr4 |
or eax, CR4_PGE |
mov cr4, eax |
@@: |
mov [pte_valid_mask], ebx |
xor eax, eax |
mov dword [sys_proc+PROC.pdt_0], eax |
mov dword [sys_proc+PROC.pdt_0+4], eax |