2384,6 → 2384,9 |
u32 num_heads = 0, lb_size; |
int i; |
|
if (!rdev->mode_info.mode_config_initialized) |
return; |
|
radeon_update_display_priority(rdev); |
|
for (i = 0; i < rdev->num_crtc; i++) { |
3362,6 → 3365,7 |
void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
{ |
struct radeon_ring *ring = &rdev->ring[ib->ring]; |
unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; |
u32 header; |
|
if (ib->is_const_ib) { |
3397,14 → 3401,13 |
#endif |
(ib->gpu_addr & 0xFFFFFFFC)); |
radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); |
radeon_ring_write(ring, ib->length_dw | |
(ib->vm ? (ib->vm->id << 24) : 0)); |
radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); |
|
if (!ib->is_const_ib) { |
/* flush read cache over gart for this vmid */ |
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); |
radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); |
radeon_ring_write(ring, vm_id); |
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | |
PACKET3_TC_ACTION_ENA | |
4684,7 → 4687,7 |
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) |
{ |
int ret = 0; |
u32 idx = 0; |
u32 idx = 0, i; |
struct radeon_cs_packet pkt; |
|
do { |
4695,6 → 4698,12 |
switch (pkt.type) { |
case RADEON_PACKET_TYPE0: |
dev_err(rdev->dev, "Packet0 not allowed!\n"); |
for (i = 0; i < ib->length_dw; i++) { |
if (i == idx) |
printk("\t0x%08x <---\n", ib->ptr[i]); |
else |
printk("\t0x%08x\n", ib->ptr[i]); |
} |
ret = -EINVAL; |
break; |
case RADEON_PACKET_TYPE2: |
5014,27 → 5023,23 |
block, mc_id); |
} |
|
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) |
void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
unsigned vm_id, uint64_t pd_addr) |
{ |
struct radeon_ring *ring = &rdev->ring[ridx]; |
|
if (vm == NULL) |
return; |
|
/* write new base address */ |
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | |
WRITE_DATA_DST_SEL(0))); |
|
if (vm->id < 8) { |
if (vm_id < 8) { |
radeon_ring_write(ring, |
(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); |
(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); |
} else { |
radeon_ring_write(ring, |
(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); |
(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); |
} |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, vm->pd_gpu_addr >> 12); |
radeon_ring_write(ring, pd_addr >> 12); |
|
/* flush hdp cache */ |
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
5050,7 → 5055,7 |
WRITE_DATA_DST_SEL(0))); |
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
radeon_ring_write(ring, 0); |
radeon_ring_write(ring, 1 << vm->id); |
radeon_ring_write(ring, 1 << vm_id); |
|
/* sync PFP to ME, otherwise we might get invalid PFP reads */ |
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |