897,6 → 897,8 |
|
/* update display watermarks based on new power state */ |
radeon_bandwidth_update(rdev); |
/* update displays */ |
radeon_dpm_display_configuration_changed(rdev); |
|
/* wait for the rings to drain */ |
for (i = 0; i < RADEON_NUM_RINGS; i++) { |
913,9 → 915,6 |
|
radeon_dpm_post_set_power_state(rdev); |
|
/* update displays */ |
radeon_dpm_display_configuration_changed(rdev); |
|
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
rdev->pm.dpm.single_display = single_display; |