| 163,7 → 163,7 |
|---|
| |
| /* starting with BTC, there is one state that is used for both |
| * MH and SH. Difference is that we always use the high clock index for |
| * mclk. |
| * mclk and vddci. |
| */ |
| if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && |
| (rdev->family >= CHIP_BARTS) && |
| 228,7 → 228,7 |
|---|
| |
| static void radeon_pm_set_clocks(struct radeon_device *rdev) |
| { |
| int i; |
| int i, r; |
| |
| /* no need to take locks, etc. if nothing's going to change */ |
| if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && |
| 242,9 → 242,18 |
|---|
| /* wait for the rings to drain */ |
| for (i = 0; i < RADEON_NUM_RINGS; i++) { |
| struct radeon_ring *ring = &rdev->ring[i]; |
| if (ring->ready) |
| radeon_fence_wait_empty_locked(rdev, i); |
| if (!ring->ready) { |
| continue; |
| } |
| r = radeon_fence_wait_empty_locked(rdev, i); |
| if (r) { |
| /* needs a GPU reset dont reset here */ |
| mutex_unlock(&rdev->ring_lock); |
| // up_write(&rdev->pm.mclk_lock); |
| mutex_unlock(&rdev->ddev->struct_mutex); |
| return; |
| } |
| } |
| |
| radeon_unmap_vram_bos(rdev); |
| |
| 485,6 → 494,7 |
|---|
| rdev->pm.current_sclk = rdev->pm.default_sclk; |
| rdev->pm.current_mclk = rdev->pm.default_mclk; |
| rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
| rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; |
| if (rdev->pm.pm_method == PM_METHOD_DYNPM |
| && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { |
| rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
| 672,13 → 682,17 |
|---|
| struct radeon_device *rdev = dev->dev_private; |
| |
| seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); |
| /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ |
| if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) |
| seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); |
| else |
| seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
| seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); |
| if (rdev->asic->get_memory_clock) |
| if (rdev->asic->pm.get_memory_clock) |
| seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
| if (rdev->pm.current_vddc) |
| seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); |
| if (rdev->asic->get_pcie_lanes) |
| if (rdev->asic->pm.get_pcie_lanes) |
| seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
| |
| return 0; |