28,7 → 28,7 |
//#include <linux/console.h> |
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#include <drmP.h> |
//#include <drm/drm_crtc_helper.h> |
#include <drm_crtc_helper.h> |
#include "radeon_drm.h" |
#include "radeon_reg.h" |
#include "radeon.h" |
285,7 → 285,6 |
} |
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/* |
* ASIC |
*/ |
474,7 → 473,7 |
struct pci_dev *pdev, |
uint32_t flags) |
{ |
int r, ret = -1; |
int r, ret; |
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dbgprintf("%s\n",__FUNCTION__); |
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495,7 → 494,6 |
// mutex_init(&rdev->cp.mutex); |
// rwlock_init(&rdev->fence_drv.lock); |
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if (radeon_agpmode == -1) { |
rdev->flags &= ~RADEON_IS_AGP; |
if (rdev->family > CHIP_RV515 || |
580,7 → 578,6 |
// radeon_combios_asic_init(rdev->ddev); |
} |
} |
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/* Get vram informations */ |
radeon_vram_info(rdev); |
/* Device is severly broken if aper size > vram size. |
608,9 → 605,7 |
r = radeon_mc_init(rdev); |
if (r) { |
return r; |
}; |
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} |
/* Fence driver */ |
// r = radeon_fence_driver_init(rdev); |
// if (r) { |
628,9 → 623,9 |
/* Initialize GART (initialize after TTM so we can allocate |
* memory through TTM but finalize after TTM) */ |
r = radeon_gart_enable(rdev); |
// if (!r) { |
// r = radeon_gem_init(rdev); |
// } |
if (!r) { |
r = radeon_gem_init(rdev); |
} |
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/* 1M ring buffer */ |
if (!r) { |
672,11 → 667,12 |
if (!ret) { |
DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
} |
// if (radeon_benchmarking) { |
if (radeon_benchmarking) { |
// radeon_benchmark(rdev); |
// } |
} |
return ret; |
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return -1; |
// return -1; |
} |
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static struct pci_device_id pciidlist[] = { |
873,6 → 869,9 |
// driver->name, driver->major, driver->minor, driver->patchlevel, |
// driver->date, pci_name(pdev), dev->primary->index); |
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drm_helper_resume_force_mode(dev); |
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return 0; |
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err_g4: |