60,7 → 60,6 |
* are considered as fatal) |
*/ |
|
#include <ddk.h> |
#include <asm/atomic.h> |
|
#include <linux/list.h> |
83,6 → 82,8 |
|
#include <syscall.h> |
|
extern unsigned long volatile jiffies; |
|
/* |
* Modules parameters. |
*/ |
97,10 → 98,10 |
extern int radeon_testing; |
extern int radeon_connector_table; |
extern int radeon_tv; |
extern int radeon_new_pll; |
extern int radeon_dynpm; |
extern int radeon_audio; |
|
extern int radeon_disp_priority; |
extern int radeon_hw_i2c; |
extern int radeon_pcie_gen2; |
typedef struct pm_message { |
int event; |
} pm_message_t; |
160,11 → 161,29 |
#define writeq __raw_writeq |
|
|
static inline u32 ioread32(const volatile void __iomem *addr) |
{ |
return in32((u32)addr); |
} |
|
static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
{ |
out32((u32)addr, b); |
} |
|
struct __wait_queue_head { |
spinlock_t lock; |
struct list_head task_list; |
}; |
typedef struct __wait_queue_head wait_queue_head_t; |
|
|
/* |
* Copy from radeon_drv.h so we don't have to include both and have conflicting |
* symbol; |
*/ |
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
/* RADEON_IB_POOL_SIZE must be a power of 2 */ |
#define RADEON_IB_POOL_SIZE 16 |
#define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
230,6 → 249,7 |
uint32_t default_sclk; |
uint32_t default_dispclk; |
uint32_t dp_extclk; |
uint32_t max_pixel_clock; |
}; |
|
/* |
236,9 → 256,18 |
* Power management |
*/ |
int radeon_pm_init(struct radeon_device *rdev); |
void radeon_pm_fini(struct radeon_device *rdev); |
void radeon_pm_compute_clocks(struct radeon_device *rdev); |
void radeon_pm_suspend(struct radeon_device *rdev); |
void radeon_pm_resume(struct radeon_device *rdev); |
void radeon_combios_get_power_modes(struct radeon_device *rdev); |
void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
void rs690_pm_info(struct radeon_device *rdev); |
extern int rv6xx_get_temp(struct radeon_device *rdev); |
extern int rv770_get_temp(struct radeon_device *rdev); |
extern int evergreen_get_temp(struct radeon_device *rdev); |
extern int sumo_get_temp(struct radeon_device *rdev); |
|
/* |
* Fences. |
247,8 → 276,9 |
uint32_t scratch_reg; |
atomic_t seq; |
uint32_t last_seq; |
unsigned long count_timeout; |
// wait_queue_head_t queue; |
unsigned long last_jiffies; |
unsigned long last_timeout; |
wait_queue_head_t queue; |
rwlock_t lock; |
struct list_head created; |
struct list_head emited; |
262,7 → 292,6 |
struct list_head list; |
/* protected by radeon_fence.lock */ |
uint32_t seq; |
unsigned long timeout; |
bool emited; |
bool signaled; |
}; |
293,7 → 322,7 |
*/ |
struct radeon_mman { |
struct ttm_bo_global_ref bo_global_ref; |
struct ttm_global_reference mem_global_ref; |
// struct drm_global_reference mem_global_ref; |
struct ttm_bo_device bdev; |
bool mem_global_referenced; |
bool initialized; |
315,12 → 344,12 |
int surface_reg; |
/* Constant after initialization */ |
struct radeon_device *rdev; |
struct drm_gem_object *gobj; |
struct drm_gem_object gem_base; |
u32 domain; |
}; |
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
|
struct radeon_bo_list { |
struct list_head list; |
struct radeon_bo *bo; |
uint64_t gpu_offset; |
unsigned rdomain; |
377,6 → 406,7 |
union radeon_gart_table table; |
struct page **pages; |
dma_addr_t *pages_addr; |
bool *ttm_alloced; |
bool ready; |
}; |
|
413,6 → 443,7 |
int vram_mtrr; |
bool vram_is_ddr; |
bool igp_sideport_enabled; |
u64 gtt_base_align; |
}; |
|
bool radeon_combios_sideport_present(struct radeon_device *rdev); |
423,6 → 454,7 |
*/ |
struct radeon_scratch { |
unsigned num_reg; |
uint32_t reg_base; |
bool free[32]; |
uint32_t reg[32]; |
}; |
434,15 → 466,58 |
/* |
* IRQS. |
*/ |
struct r500_irq_stat_regs { |
u32 disp_int; |
}; |
|
struct r600_irq_stat_regs { |
u32 disp_int; |
u32 disp_int_cont; |
u32 disp_int_cont2; |
u32 d1grph_int; |
u32 d2grph_int; |
}; |
|
struct evergreen_irq_stat_regs { |
u32 disp_int; |
u32 disp_int_cont; |
u32 disp_int_cont2; |
u32 disp_int_cont3; |
u32 disp_int_cont4; |
u32 disp_int_cont5; |
u32 d1grph_int; |
u32 d2grph_int; |
u32 d3grph_int; |
u32 d4grph_int; |
u32 d5grph_int; |
u32 d6grph_int; |
}; |
|
union radeon_irq_stat_regs { |
struct r500_irq_stat_regs r500; |
struct r600_irq_stat_regs r600; |
struct evergreen_irq_stat_regs evergreen; |
}; |
|
struct radeon_irq { |
bool installed; |
bool sw_int; |
/* FIXME: use a define max crtc rather than hardcode it */ |
bool crtc_vblank_int[2]; |
bool crtc_vblank_int[6]; |
bool pflip[6]; |
wait_queue_head_t vblank_queue; |
/* FIXME: use defines for max hpd/dacs */ |
bool hpd[6]; |
bool gui_idle; |
bool gui_idle_acked; |
wait_queue_head_t idle_queue; |
/* FIXME: use defines for max HDMI blocks */ |
bool hdmi[2]; |
spinlock_t sw_lock; |
int sw_refcount; |
union radeon_irq_stat_regs stat_regs; |
spinlock_t pflip_lock[6]; |
int pflip_refcount[6]; |
}; |
|
int radeon_irq_kms_init(struct radeon_device *rdev); |
528,7 → 603,9 |
extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
/* Ring access between begin & end cannot sleep */ |
void radeon_ring_free_size(struct radeon_device *rdev); |
int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
void radeon_ring_commit(struct radeon_device *rdev); |
void radeon_ring_unlock_commit(struct radeon_device *rdev); |
void radeon_ring_unlock_undo(struct radeon_device *rdev); |
int radeon_ring_test(struct radeon_device *rdev); |
632,6 → 709,7 |
*/ |
int radeon_agp_init(struct radeon_device *rdev); |
void radeon_agp_resume(struct radeon_device *rdev); |
void radeon_agp_suspend(struct radeon_device *rdev); |
void radeon_agp_fini(struct radeon_device *rdev); |
|
|
642,8 → 720,17 |
struct radeon_bo *wb_obj; |
volatile uint32_t *wb; |
uint64_t gpu_addr; |
bool enabled; |
bool use_event; |
}; |
|
#define RADEON_WB_SCRATCH_OFFSET 0 |
#define RADEON_WB_CP_RPTR_OFFSET 1024 |
#define RADEON_WB_CP1_RPTR_OFFSET 1280 |
#define RADEON_WB_CP2_RPTR_OFFSET 1536 |
#define R600_WB_IH_WPTR_OFFSET 2048 |
#define R600_WB_EVENT_OFFSET 3072 |
|
/** |
* struct radeon_pm - power management datas |
* @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
655,26 → 742,34 |
* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
* @sclk: GPU clock Mhz (core bandwith depends of this clock) |
* @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
* @needed_bandwidth: current bandwidth needs |
* |
* It keeps track of various data needed to take powermanagement decision. |
* Bandwith need is used to determine minimun clock of the GPU and memory. |
* Bandwidth need is used to determine minimun clock of the GPU and memory. |
* Equation between gpu/memory clock and available bandwidth is hw dependent |
* (type of memory, bus size, efficiency, ...) |
*/ |
enum radeon_pm_state { |
PM_STATE_DISABLED, |
PM_STATE_MINIMUM, |
PM_STATE_PAUSED, |
PM_STATE_ACTIVE |
|
enum radeon_pm_method { |
PM_METHOD_PROFILE, |
PM_METHOD_DYNPM, |
}; |
enum radeon_pm_action { |
PM_ACTION_NONE, |
PM_ACTION_MINIMUM, |
PM_ACTION_DOWNCLOCK, |
PM_ACTION_UPCLOCK |
|
enum radeon_dynpm_state { |
DYNPM_STATE_DISABLED, |
DYNPM_STATE_MINIMUM, |
DYNPM_STATE_PAUSED, |
DYNPM_STATE_ACTIVE, |
DYNPM_STATE_SUSPENDED, |
}; |
enum radeon_dynpm_action { |
DYNPM_ACTION_NONE, |
DYNPM_ACTION_MINIMUM, |
DYNPM_ACTION_DOWNCLOCK, |
DYNPM_ACTION_UPCLOCK, |
DYNPM_ACTION_DEFAULT |
}; |
|
enum radeon_voltage_type { |
VOLTAGE_NONE = 0, |
691,13 → 786,39 |
POWER_STATE_TYPE_PERFORMANCE, |
}; |
|
enum radeon_pm_clock_mode_type { |
POWER_MODE_TYPE_DEFAULT, |
POWER_MODE_TYPE_LOW, |
POWER_MODE_TYPE_MID, |
POWER_MODE_TYPE_HIGH, |
enum radeon_pm_profile_type { |
PM_PROFILE_DEFAULT, |
PM_PROFILE_AUTO, |
PM_PROFILE_LOW, |
PM_PROFILE_MID, |
PM_PROFILE_HIGH, |
}; |
|
#define PM_PROFILE_DEFAULT_IDX 0 |
#define PM_PROFILE_LOW_SH_IDX 1 |
#define PM_PROFILE_MID_SH_IDX 2 |
#define PM_PROFILE_HIGH_SH_IDX 3 |
#define PM_PROFILE_LOW_MH_IDX 4 |
#define PM_PROFILE_MID_MH_IDX 5 |
#define PM_PROFILE_HIGH_MH_IDX 6 |
#define PM_PROFILE_MAX 7 |
|
struct radeon_pm_profile { |
int dpms_off_ps_idx; |
int dpms_on_ps_idx; |
int dpms_off_cm_idx; |
int dpms_on_cm_idx; |
}; |
|
enum radeon_int_thermal_type { |
THERMAL_TYPE_NONE, |
THERMAL_TYPE_RV6XX, |
THERMAL_TYPE_RV770, |
THERMAL_TYPE_EVERGREEN, |
THERMAL_TYPE_SUMO, |
THERMAL_TYPE_NI, |
}; |
|
struct radeon_voltage { |
enum radeon_voltage_type type; |
/* gpio voltage */ |
709,15 → 830,13 |
u8 vddci_id; /* index into vddci voltage table */ |
bool vddci_enabled; |
/* r6xx+ sw */ |
u32 voltage; |
u16 voltage; |
/* evergreen+ vddci */ |
u16 vddci; |
}; |
|
struct radeon_pm_non_clock_info { |
/* pcie lanes */ |
int pcie_lanes; |
/* standardized non-clock flags */ |
u32 flags; |
}; |
/* clock mode flags */ |
#define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
|
struct radeon_pm_clock_info { |
/* memory clock */ |
726,10 → 845,13 |
u32 sclk; |
/* voltage info */ |
struct radeon_voltage voltage; |
/* standardized clock flags - not sure we'll need these */ |
/* standardized clock flags */ |
u32 flags; |
}; |
|
/* state flags */ |
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
|
struct radeon_power_state { |
enum radeon_pm_state_type type; |
/* XXX: use a define for num clock modes */ |
737,9 → 859,11 |
/* number of valid clock modes in this power state */ |
int num_clock_modes; |
struct radeon_pm_clock_info *default_clock_mode; |
/* non clock info about this state */ |
struct radeon_pm_non_clock_info non_clock_info; |
bool voltage_drop_active; |
/* standardized state flags */ |
u32 flags; |
u32 misc; /* vbios specific flags */ |
u32 misc2; /* vbios specific flags */ |
int pcie_lanes; /* pcie lanes */ |
}; |
|
/* |
749,13 → 873,11 |
|
struct radeon_pm { |
struct mutex mutex; |
// struct delayed_work idle_work; |
enum radeon_pm_state state; |
enum radeon_pm_action planned_action; |
unsigned long action_timeout; |
bool downclocked; |
int active_crtcs; |
u32 active_crtcs; |
int active_crtc_count; |
int req_vblank; |
bool vblank_sync; |
bool gui_idle; |
fixed20_12 max_bandwidth; |
fixed20_12 igp_sideport_mclk; |
fixed20_12 igp_system_mclk; |
766,16 → 888,41 |
fixed20_12 ht_bandwidth; |
fixed20_12 core_bandwidth; |
fixed20_12 sclk; |
fixed20_12 mclk; |
fixed20_12 needed_bandwidth; |
/* XXX: use a define for num power modes */ |
struct radeon_power_state power_state[8]; |
struct radeon_power_state *power_state; |
/* number of valid power states */ |
int num_power_states; |
struct radeon_power_state *current_power_state; |
struct radeon_pm_clock_info *current_clock_mode; |
struct radeon_power_state *requested_power_state; |
struct radeon_pm_clock_info *requested_clock_mode; |
struct radeon_power_state *default_power_state; |
int current_power_state_index; |
int current_clock_mode_index; |
int requested_power_state_index; |
int requested_clock_mode_index; |
int default_power_state_index; |
u32 current_sclk; |
u32 current_mclk; |
u16 current_vddc; |
u16 current_vddci; |
u32 default_sclk; |
u32 default_mclk; |
u16 default_vddc; |
u16 default_vddci; |
struct radeon_i2c_chan *i2c_bus; |
/* selected pm method */ |
enum radeon_pm_method pm_method; |
/* dynpm power management */ |
// struct delayed_work dynpm_idle_work; |
enum radeon_dynpm_state dynpm_state; |
enum radeon_dynpm_action dynpm_planned_action; |
unsigned long dynpm_action_timeout; |
bool dynpm_can_upclock; |
bool dynpm_can_downclock; |
/* profile-based power management */ |
enum radeon_pm_profile_type profile; |
int profile_index; |
struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
/* internal thermal controller on rv6xx+ */ |
enum radeon_int_thermal_type int_thermal_type; |
struct device *int_hwmon_dev; |
}; |
|
/* |
787,7 → 934,8 |
int (*resume)(struct radeon_device *rdev); |
int (*suspend)(struct radeon_device *rdev); |
void (*vga_set_state)(struct radeon_device *rdev, bool state); |
int (*gpu_reset)(struct radeon_device *rdev); |
bool (*gpu_is_lockup)(struct radeon_device *rdev); |
int (*asic_reset)(struct radeon_device *rdev); |
void (*gart_tlb_flush)(struct radeon_device *rdev); |
int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
827,7 → 975,7 |
int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
uint32_t tiling_flags, uint32_t pitch, |
uint32_t offset, uint32_t obj_size); |
int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
void (*bandwidth_update)(struct radeon_device *rdev); |
void (*hpd_init)(struct radeon_device *rdev); |
void (*hpd_fini)(struct radeon_device *rdev); |
840,15 → 988,32 |
* through ring. |
*/ |
void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
bool (*gui_idle)(struct radeon_device *rdev); |
/* power management */ |
void (*pm_misc)(struct radeon_device *rdev); |
void (*pm_prepare)(struct radeon_device *rdev); |
void (*pm_finish)(struct radeon_device *rdev); |
void (*pm_init_profile)(struct radeon_device *rdev); |
void (*pm_get_dynpm_state)(struct radeon_device *rdev); |
/* pageflipping */ |
void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
}; |
|
/* |
* Asic structures |
*/ |
struct r100_gpu_lockup { |
unsigned long last_jiffies; |
u32 last_cp_rptr; |
}; |
|
struct r100_asic { |
const unsigned *reg_safe_bm; |
unsigned reg_safe_bm_size; |
u32 hdp_cntl; |
struct r100_gpu_lockup lockup; |
}; |
|
struct r300_asic { |
856,6 → 1021,7 |
unsigned reg_safe_bm_size; |
u32 resync_scratch; |
u32 hdp_cntl; |
struct r100_gpu_lockup lockup; |
}; |
|
struct r600_asic { |
875,6 → 1041,8 |
unsigned tiling_nbanks; |
unsigned tiling_npipes; |
unsigned tiling_group_size; |
unsigned tile_config; |
struct r100_gpu_lockup lockup; |
}; |
|
struct rv770_asic { |
898,20 → 1066,97 |
unsigned tiling_nbanks; |
unsigned tiling_npipes; |
unsigned tiling_group_size; |
unsigned tile_config; |
struct r100_gpu_lockup lockup; |
}; |
|
struct evergreen_asic { |
unsigned num_ses; |
unsigned max_pipes; |
unsigned max_tile_pipes; |
unsigned max_simds; |
unsigned max_backends; |
unsigned max_gprs; |
unsigned max_threads; |
unsigned max_stack_entries; |
unsigned max_hw_contexts; |
unsigned max_gs_threads; |
unsigned sx_max_export_size; |
unsigned sx_max_export_pos_size; |
unsigned sx_max_export_smx_size; |
unsigned sq_num_cf_insts; |
unsigned sx_num_of_sets; |
unsigned sc_prim_fifo_size; |
unsigned sc_hiz_tile_fifo_size; |
unsigned sc_earlyz_tile_fifo_size; |
unsigned tiling_nbanks; |
unsigned tiling_npipes; |
unsigned tiling_group_size; |
unsigned tile_config; |
struct r100_gpu_lockup lockup; |
}; |
|
struct cayman_asic { |
unsigned max_shader_engines; |
unsigned max_pipes_per_simd; |
unsigned max_tile_pipes; |
unsigned max_simds_per_se; |
unsigned max_backends_per_se; |
unsigned max_texture_channel_caches; |
unsigned max_gprs; |
unsigned max_threads; |
unsigned max_gs_threads; |
unsigned max_stack_entries; |
unsigned sx_num_of_sets; |
unsigned sx_max_export_size; |
unsigned sx_max_export_pos_size; |
unsigned sx_max_export_smx_size; |
unsigned max_hw_contexts; |
unsigned sq_num_cf_insts; |
unsigned sc_prim_fifo_size; |
unsigned sc_hiz_tile_fifo_size; |
unsigned sc_earlyz_tile_fifo_size; |
|
unsigned num_shader_engines; |
unsigned num_shader_pipes_per_simd; |
unsigned num_tile_pipes; |
unsigned num_simds_per_se; |
unsigned num_backends_per_se; |
unsigned backend_disable_mask_per_asic; |
unsigned backend_map; |
unsigned num_texture_channel_caches; |
unsigned mem_max_burst_length_bytes; |
unsigned mem_row_size_in_kb; |
unsigned shader_engine_tile_size; |
unsigned num_gpus; |
unsigned multi_gpu_tile_size; |
|
unsigned tile_config; |
struct r100_gpu_lockup lockup; |
}; |
|
union radeon_asic_config { |
struct r300_asic r300; |
struct r100_asic r100; |
struct r600_asic r600; |
struct rv770_asic rv770; |
struct evergreen_asic evergreen; |
struct cayman_asic cayman; |
}; |
|
|
/* |
* asic initizalization from radeon_asic.c |
*/ |
void radeon_agp_disable(struct radeon_device *rdev); |
int radeon_asic_init(struct radeon_device *rdev); |
|
|
|
/* VRAM scratch page for HDP bug */ |
struct r700_vram_scratch { |
struct radeon_bo *robj; |
volatile uint32_t *ptr; |
}; |
|
/* |
* Core structure, functions and helpers. |
937,12 → 1182,9 |
bool is_atom_bios; |
uint16_t bios_header_start; |
struct radeon_bo *stollen_vga_memory; |
struct fb_info *fbdev_info; |
struct radeon_bo *fbdev_rbo; |
struct radeon_framebuffer *fbdev_rfb; |
/* Register mmio */ |
unsigned long rmmio_base; |
unsigned long rmmio_size; |
resource_size_t rmmio_base; |
resource_size_t rmmio_size; |
void *rmmio; |
radeon_rreg_t mc_rreg; |
radeon_wreg_t mc_wreg; |
951,6 → 1193,9 |
uint32_t pcie_reg_mask; |
radeon_rreg_t pciep_rreg; |
radeon_wreg_t pciep_wreg; |
/* io port */ |
void __iomem *rio_mem; |
resource_size_t rio_mem_size; |
struct radeon_clock clock; |
struct radeon_mc mc; |
struct radeon_gart gart; |
959,8 → 1204,11 |
struct radeon_mman mman; |
struct radeon_fence_driver fence_drv; |
struct radeon_cp cp; |
/* cayman compute rings */ |
struct radeon_cp cp1; |
struct radeon_cp cp2; |
struct radeon_ib_pool ib_pool; |
// struct radeon_irq irq; |
struct radeon_irq irq; |
struct radeon_asic *asic; |
struct radeon_gem gem; |
struct radeon_pm pm; |
977,12 → 1225,19 |
const struct firmware *me_fw; /* all family ME firmware */ |
const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
const struct firmware *mc_fw; /* NI MC firmware */ |
struct r600_blit r600_blit; |
struct r700_vram_scratch vram_scratch; |
int msi_enabled; /* msi enabled */ |
// struct r600_ih ih; /* r6/700 interrupt ring */ |
// struct workqueue_struct *wq; |
// struct work_struct hotplug_work; |
int num_crtc; /* number of crtcs */ |
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
struct mutex vram_mutex; |
|
/* audio stuff */ |
bool audio_enabled; |
// struct timer_list audio_timer; |
int audio_channels; |
int audio_rate; |
990,7 → 1245,9 |
uint8_t audio_status_bits; |
uint8_t audio_category_code; |
|
bool powered_down; |
|
/* i2c buses */ |
struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
}; |
|
int radeon_device_init(struct radeon_device *rdev, |
1000,13 → 1257,6 |
void radeon_device_fini(struct radeon_device *rdev); |
int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
|
/* r600 blit */ |
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
void r600_kms_blit_copy(struct radeon_device *rdev, |
u64 src_gpu_addr, u64 dst_gpu_addr, |
int size_bytes); |
|
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
{ |
if (reg < rdev->rmmio_size) |
1027,6 → 1277,26 |
} |
} |
|
static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
{ |
if (reg < rdev->rio_mem_size) |
return ioread32(rdev->rio_mem + reg); |
else { |
iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
} |
} |
|
static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
{ |
if (reg < rdev->rio_mem_size) |
iowrite32(v, rdev->rio_mem + reg); |
else { |
iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
} |
} |
|
/* |
* Cast helper |
*/ |
1037,6 → 1307,8 |
*/ |
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg)) |
#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg)) |
#define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1063,6 → 1335,8 |
tmp_ |= ((val) & ~(mask)); \ |
WREG32_PLL(reg, tmp_); \ |
} while (0) |
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
|
/* |
* Indirect registers accessor |
1106,10 → 1380,25 |
(rdev->family == CHIP_RV410) || \ |
(rdev->family == CHIP_RS400) || \ |
(rdev->family == CHIP_RS480)) |
#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
(rdev->ddev->pdev->device == 0x9443) || \ |
(rdev->ddev->pdev->device == 0x944B) || \ |
(rdev->ddev->pdev->device == 0x9506) || \ |
(rdev->ddev->pdev->device == 0x9509) || \ |
(rdev->ddev->pdev->device == 0x950F) || \ |
(rdev->ddev->pdev->device == 0x689C) || \ |
(rdev->ddev->pdev->device == 0x689D)) |
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
(rdev->family == CHIP_RS690) || \ |
(rdev->family == CHIP_RS740) || \ |
(rdev->family >= CHIP_R600)) |
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
(rdev->flags & RADEON_IS_IGP)) |
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
|
/* |
* BIOS helpers. |
1150,7 → 1439,8 |
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
#define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1178,9 → 1468,19 |
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) |
#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) |
#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) |
|
/* Common functions */ |
/* AGP */ |
extern int radeon_gpu_reset(struct radeon_device *rdev); |
extern void radeon_agp_disable(struct radeon_device *rdev); |
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
extern void radeon_gart_restore(struct radeon_device *rdev); |
1187,10 → 1487,13 |
extern int radeon_modeset_init(struct radeon_device *rdev); |
extern void radeon_modeset_fini(struct radeon_device *rdev); |
extern bool radeon_card_posted(struct radeon_device *rdev); |
extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
extern void radeon_update_display_priority(struct radeon_device *rdev); |
extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
extern int radeon_clocks_init(struct radeon_device *rdev); |
extern void radeon_clocks_fini(struct radeon_device *rdev); |
extern void radeon_scratch_init(struct radeon_device *rdev); |
extern void radeon_wb_fini(struct radeon_device *rdev); |
extern int radeon_wb_init(struct radeon_device *rdev); |
extern void radeon_wb_disable(struct radeon_device *rdev); |
extern void radeon_surface_init(struct radeon_device *rdev); |
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1201,160 → 1504,25 |
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
extern int radeon_resume_kms(struct drm_device *dev); |
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
|
/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
struct r100_mc_save { |
u32 GENMO_WT; |
u32 CRTC_EXT_CNTL; |
u32 CRTC_GEN_CNTL; |
u32 CRTC2_GEN_CNTL; |
u32 CUR_OFFSET; |
u32 CUR2_OFFSET; |
}; |
extern void r100_cp_disable(struct radeon_device *rdev); |
extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
extern void r100_cp_fini(struct radeon_device *rdev); |
extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
extern int r100_pci_gart_init(struct radeon_device *rdev); |
extern void r100_pci_gart_fini(struct radeon_device *rdev); |
extern int r100_pci_gart_enable(struct radeon_device *rdev); |
extern void r100_pci_gart_disable(struct radeon_device *rdev); |
extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
extern void r100_ib_fini(struct radeon_device *rdev); |
extern int r100_ib_init(struct radeon_device *rdev); |
extern void r100_irq_disable(struct radeon_device *rdev); |
extern int r100_irq_set(struct radeon_device *rdev); |
extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
extern void r100_vram_init_sizes(struct radeon_device *rdev); |
extern void r100_wb_disable(struct radeon_device *rdev); |
extern void r100_wb_fini(struct radeon_device *rdev); |
extern int r100_wb_init(struct radeon_device *rdev); |
extern void r100_hdp_reset(struct radeon_device *rdev); |
extern int r100_rb2d_reset(struct radeon_device *rdev); |
extern int r100_cp_reset(struct radeon_device *rdev); |
extern void r100_vga_render_disable(struct radeon_device *rdev); |
extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
struct radeon_bo *robj); |
extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
const unsigned *auth, unsigned n, |
radeon_packet0_check_t check); |
extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
unsigned idx); |
extern void r100_enable_bm(struct radeon_device *rdev); |
extern void r100_set_common_regs(struct radeon_device *rdev); |
/* |
* r600 functions used by radeon_encoder.c |
*/ |
extern void r600_hdmi_enable(struct drm_encoder *encoder); |
extern void r600_hdmi_disable(struct drm_encoder *encoder); |
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
|
/* rv200,rv250,rv280 */ |
extern void r200_set_safe_registers(struct radeon_device *rdev); |
extern int ni_init_microcode(struct radeon_device *rdev); |
extern int ni_mc_load_microcode(struct radeon_device *rdev); |
|
/* r300,r350,rv350,rv370,rv380 */ |
extern void r300_set_reg_safe(struct radeon_device *rdev); |
extern void r300_mc_program(struct radeon_device *rdev); |
extern void r300_mc_init(struct radeon_device *rdev); |
extern void r300_clock_startup(struct radeon_device *rdev); |
extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
/* radeon_acpi.c */ |
#if defined(CONFIG_ACPI) |
extern int radeon_acpi_init(struct radeon_device *rdev); |
#else |
static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
#endif |
|
/* r420,r423,rv410 */ |
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
extern void r420_pipes_init(struct radeon_device *rdev); |
|
/* rv515 */ |
struct rv515_mc_save { |
u32 d1vga_control; |
u32 d2vga_control; |
u32 vga_render_control; |
u32 vga_hdp_control; |
u32 d1crtc_control; |
u32 d2crtc_control; |
}; |
extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
extern void rv515_vga_render_disable(struct radeon_device *rdev); |
extern void rv515_set_safe_registers(struct radeon_device *rdev); |
extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
extern void rv515_clock_startup(struct radeon_device *rdev); |
extern void rv515_debugfs(struct radeon_device *rdev); |
extern int rv515_suspend(struct radeon_device *rdev); |
|
/* rs400 */ |
extern int rs400_gart_init(struct radeon_device *rdev); |
extern int rs400_gart_enable(struct radeon_device *rdev); |
extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
extern void rs400_gart_disable(struct radeon_device *rdev); |
extern void rs400_gart_fini(struct radeon_device *rdev); |
|
/* rs600 */ |
extern void rs600_set_safe_registers(struct radeon_device *rdev); |
extern int rs600_irq_set(struct radeon_device *rdev); |
extern void rs600_irq_disable(struct radeon_device *rdev); |
|
/* rs690, rs740 */ |
extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
struct drm_display_mode *mode1, |
struct drm_display_mode *mode2); |
|
/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
extern bool r600_card_posted(struct radeon_device *rdev); |
extern void r600_cp_stop(struct radeon_device *rdev); |
extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
extern int r600_cp_resume(struct radeon_device *rdev); |
extern void r600_cp_fini(struct radeon_device *rdev); |
extern int r600_count_pipe_bits(uint32_t val); |
extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
extern int r600_pcie_gart_init(struct radeon_device *rdev); |
extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
extern int r600_ib_test(struct radeon_device *rdev); |
extern int r600_ring_test(struct radeon_device *rdev); |
extern void r600_wb_fini(struct radeon_device *rdev); |
extern int r600_wb_enable(struct radeon_device *rdev); |
extern void r600_wb_disable(struct radeon_device *rdev); |
extern void r600_scratch_init(struct radeon_device *rdev); |
extern int r600_blit_init(struct radeon_device *rdev); |
extern void r600_blit_fini(struct radeon_device *rdev); |
extern int r600_init_microcode(struct radeon_device *rdev); |
extern int r600_gpu_reset(struct radeon_device *rdev); |
/* r600 irq */ |
extern int r600_irq_init(struct radeon_device *rdev); |
extern void r600_irq_fini(struct radeon_device *rdev); |
extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
extern int r600_irq_set(struct radeon_device *rdev); |
extern void r600_irq_suspend(struct radeon_device *rdev); |
/* r600 audio */ |
extern int r600_audio_init(struct radeon_device *rdev); |
extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
extern void r600_audio_fini(struct radeon_device *rdev); |
extern void r600_hdmi_init(struct drm_encoder *encoder); |
extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); |
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
int channels, |
int rate, |
int bps, |
uint8_t status_bits, |
uint8_t category_code); |
|
/* evergreen */ |
struct evergreen_mc_save { |
u32 vga_control[6]; |
u32 vga_render_control; |
u32 vga_hdp_control; |
u32 crtc_control[6]; |
}; |
|
#include "radeon_object.h" |
|
#define DRM_UDELAY(d) udelay(d) |
1368,4 → 1536,23 |
videomode_t *mode, bool strict); |
|
|
|
struct work_struct; |
typedef void (*work_func_t)(struct work_struct *work); |
|
/* |
* The first word is the work queue pointer and the flags rolled into |
* one |
*/ |
#define work_data_bits(work) ((unsigned long *)(&(work)->data)) |
|
struct work_struct { |
atomic_long_t data; |
#define WORK_STRUCT_PENDING 0 /* T if work item pending execution */ |
#define WORK_STRUCT_FLAG_MASK (3UL) |
#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK) |
struct list_head entry; |
work_func_t func; |
}; |
|
#endif |