| 1179,6 → 1179,7 |
|---|
| R6XX_MAX_BACKENDS_MASK) >> 16)), |
| (cc_rb_backend_disable >> 16)); |
| rdev->config.r600.tile_config = tiling_config; |
| rdev->config.r600.backend_map = backend_map; |
| tiling_config |= BACKEND_MAP(backend_map); |
| WREG32(GB_TILING_CONFIG, tiling_config); |
| WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
| 1729,9 → 1730,6 |
|---|
| |
| /* set the wb address whether it's enabled or not */ |
| WREG32(CP_RB_RPTR_ADDR, |
| #ifdef __BIG_ENDIAN |
| RB_RPTR_SWAP(2) | |
| #endif |
| ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
| WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
| WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
| 2437,10 → 2435,6 |
|---|
| /* RPTR_REARM only works if msi's are enabled */ |
| if (rdev->msi_enabled) |
| ih_cntl |= RPTR_REARM; |
| |
| #ifdef __BIG_ENDIAN |
| ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); |
| #endif |
| WREG32(IH_CNTL, ih_cntl); |
| |
| /* force the active interrupt state to all disabled */ |
| 2717,6 → 2711,8 |
|---|
| * adjusted or added to on newer asics |
| */ |
| |
| #define DRM_DEBUG(...) |
| |
| int r600_irq_process(struct radeon_device *rdev) |
| { |
| u32 wptr; |
| 2729,9 → 2725,13 |
|---|
| if (!rdev->ih.enabled || rdev->shutdown) |
| return IRQ_NONE; |
| |
| /* No MSIs, need a dummy read to flush PCI DMAs */ |
| if (!rdev->msi_enabled) |
| RREG32(IH_RB_WPTR); |
| |
| wptr = r600_get_ih_wptr(rdev); |
| rptr = rdev->ih.rptr; |
| DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| // DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| |
| spin_lock_irqsave(&rdev->ih.lock, flags); |
| |
| 2741,6 → 2741,9 |
|---|
| } |
| |
| restart_ih: |
| /* Order reading of wptr vs. reading of IH ring data */ |
| rmb(); |
| |
| /* display interrupts */ |
| r600_irq_ack(rdev); |
| |