| 160,18 → 160,25 |
|---|
| |
| u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
| { |
| unsigned long flags; |
| u32 r; |
| |
| spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
| WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
| r = RREG32(R_0001FC_MC_IND_DATA); |
| spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| return r; |
| } |
| |
| void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| { |
| unsigned long flags; |
| |
| spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
| WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
| S_0001F8_MC_IND_WR_EN(1)); |
| WREG32(R_0001FC_MC_IND_DATA, v); |
| spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| } |
| |
| static void r420_debugfs(struct radeon_device *rdev) |
| 212,7 → 219,7 |
|---|
| radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
| radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
| radeon_ring_write(ring, 0xDEADBEEF); |
| radeon_ring_unlock_commit(rdev, ring); |
| radeon_ring_unlock_commit(rdev, ring, false); |
| } |
| |
| static void r420_cp_errata_fini(struct radeon_device *rdev) |
| 225,7 → 232,7 |
|---|
| radeon_ring_lock(rdev, ring, 8); |
| radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| radeon_ring_write(ring, R300_RB3D_DC_FINISH); |
| radeon_ring_unlock_commit(rdev, ring); |
| radeon_ring_unlock_commit(rdev, ring, false); |
| radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
| } |
| |
| 370,6 → 377,9 |
|---|
| } |
| r420_set_reg_safe(rdev); |
| |
| /* Initialize power management */ |
| radeon_pm_init(rdev); |
| |
| rdev->accel_working = true; |
| r = r420_startup(rdev); |
| if (r) { |