34,7 → 34,7 |
#include "radeon.h" |
#include "radeon_asic.h" |
#include <drm/radeon_drm.h> |
|
#include "r100_track.h" |
#include "r300d.h" |
#include "rv350d.h" |
#include "r300_reg_safe.h" |
69,24 → 69,27 |
mb(); |
} |
|
#define R300_PTE_UNSNOOPED (1 << 0) |
#define R300_PTE_WRITEABLE (1 << 2) |
#define R300_PTE_READABLE (1 << 3) |
|
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, |
uint64_t addr, uint32_t flags) |
{ |
void __iomem *ptr = rdev->gart.ptr; |
|
if (i < 0 || i > rdev->gart.num_gpu_pages) { |
return -EINVAL; |
} |
addr = (lower_32_bits(addr) >> 8) | |
((upper_32_bits(addr) & 0xff) << 24) | |
R300_PTE_WRITEABLE | R300_PTE_READABLE; |
((upper_32_bits(addr) & 0xff) << 24); |
if (flags & RADEON_GART_PAGE_READ) |
addr |= R300_PTE_READABLE; |
if (flags & RADEON_GART_PAGE_WRITE) |
addr |= R300_PTE_WRITEABLE; |
if (!(flags & RADEON_GART_PAGE_SNOOP)) |
addr |= R300_PTE_UNSNOOPED; |
/* on x86 we want this to be CPU endian, on powerpc |
* on powerpc without HW swappers, it'll get swapped on way |
* into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
writel(addr, ((void __iomem *)ptr) + (i * 4)); |
return 0; |
} |
|
int rv370_pcie_gart_init(struct radeon_device *rdev) |
123,7 → 126,6 |
r = radeon_gart_table_vram_pin(rdev); |
if (r) |
return r; |
radeon_gart_restore(rdev); |
/* discard memory request outside of configured range */ |
tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); |
293,7 → 295,7 |
radeon_ring_write(ring, |
R300_GEOMETRY_ROUND_NEAREST | |
R300_COLOR_ROUND_NEAREST); |
radeon_ring_unlock_commit(rdev, ring); |
radeon_ring_unlock_commit(rdev, ring, false); |
} |
|
static void r300_errata(struct radeon_device *rdev) |
592,9 → 594,6 |
#endif |
} |
|
|
#if 0 |
|
static int r300_packet0_check(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
unsigned idx, unsigned reg) |
643,7 → 642,7 |
track->cb[i].robj = reloc->robj; |
track->cb[i].offset = idx_value; |
track->cb_dirty = true; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
break; |
case R300_ZB_DEPTHOFFSET: |
r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
656,7 → 655,7 |
track->zb.robj = reloc->robj; |
track->zb.offset = idx_value; |
track->zb_dirty = true; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
break; |
case R300_TX_OFFSET_0: |
case R300_TX_OFFSET_0+4: |
685,16 → 684,16 |
|
if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { |
ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ |
((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); |
((idx_value & ~31) + (u32)reloc->gpu_offset); |
} else { |
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
if (reloc->tiling_flags & RADEON_TILING_MACRO) |
tile_flags |= R300_TXO_MACRO_TILE; |
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
if (reloc->tiling_flags & RADEON_TILING_MICRO) |
tile_flags |= R300_TXO_MICRO_TILE; |
else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
|
tmp = idx_value + ((u32)reloc->lobj.gpu_offset); |
tmp = idx_value + ((u32)reloc->gpu_offset); |
tmp |= tile_flags; |
ib[idx] = tmp; |
} |
756,11 → 755,11 |
return r; |
} |
|
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
if (reloc->tiling_flags & RADEON_TILING_MACRO) |
tile_flags |= R300_COLOR_TILE_ENABLE; |
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
if (reloc->tiling_flags & RADEON_TILING_MICRO) |
tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
|
tmp = idx_value & ~(0x7 << 16); |
841,11 → 840,11 |
return r; |
} |
|
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
if (reloc->tiling_flags & RADEON_TILING_MACRO) |
tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
if (reloc->tiling_flags & RADEON_TILING_MICRO) |
tile_flags |= R300_DEPTHMICROTILE_TILED; |
else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
|
tmp = idx_value & ~(0x7 << 16); |
1055,7 → 1054,7 |
radeon_cs_dump_packet(p, pkt); |
return r; |
} |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
break; |
case 0x4e0c: |
/* RB3D_COLOR_CHANNEL_MASK */ |
1100,7 → 1099,7 |
track->aa.robj = reloc->robj; |
track->aa.offset = idx_value; |
track->aa_dirty = true; |
ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
break; |
case R300_RB3D_AARESOLVE_PITCH: |
track->aa.pitch = idx_value & 0x3FFE; |
1165,7 → 1164,7 |
radeon_cs_dump_packet(p, pkt); |
return r; |
} |
ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
if (r) { |
return r; |
1287,9 → 1286,7 |
} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
return 0; |
} |
#endif |
|
|
void r300_set_reg_safe(struct radeon_device *rdev) |
{ |
rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; |
1484,10 → 1481,13 |
} |
r300_set_reg_safe(rdev); |
|
/* Initialize power management */ |
radeon_pm_init(rdev); |
|
rdev->accel_working = true; |
r = r300_startup(rdev); |
if (r) { |
/* Somethings want wront with the accel init stop accel */ |
/* Something went wrong with the accel init, so stop accel */ |
dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
if (rdev->flags & RADEON_IS_PCIE) |
rv370_pcie_gart_fini(rdev); |