| 69,8 → 69,7 |
|---|
| frame->checksum = 0; |
| frame->ecc = 0; |
| |
| /* Header isn't part of the checksum */ |
| for (i = 5; i < frame->len; i++) |
| for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
| sum += data[i]; |
| |
| frame->checksum = 0x100 - sum; |
| 104,7 → 103,7 |
|---|
| flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; |
| break; |
| case DIP_TYPE_SPD: |
| flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC; |
| flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; |
| break; |
| default: |
| DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 165,9 → 164,9 |
|---|
| |
| flags = intel_infoframe_index(frame); |
| |
| val &= ~VIDEO_DIP_SELECT_MASK; |
| val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
| |
| I915_WRITE(reg, val | flags); |
| I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); |
| |
| for (i = 0; i < len; i += 4) { |
| I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 245,16 → 244,17 |
|---|
| sdvox |= HDMI_MODE_SELECT; |
| |
| if (intel_hdmi->has_audio) { |
| DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
| pipe_name(intel_crtc->pipe)); |
| sdvox |= SDVO_AUDIO_ENABLE; |
| sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
| intel_write_eld(encoder, adjusted_mode); |
| } |
| |
| if (intel_crtc->pipe == 1) { |
| if (HAS_PCH_CPT(dev)) |
| sdvox |= PORT_TRANS_B_SEL_CPT; |
| else |
| sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| else if (intel_crtc->pipe == 1) |
| sdvox |= SDVO_PIPE_B_SELECT; |
| } |
| |
| I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
| POSTING_READ(intel_hdmi->sdvox_reg); |
| 269,7 → 269,11 |
|---|
| struct drm_i915_private *dev_priv = dev->dev_private; |
| struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| u32 temp; |
| u32 enable_bits = SDVO_ENABLE; |
| |
| if (intel_hdmi->has_audio) |
| enable_bits |= SDVO_AUDIO_ENABLE; |
| |
| temp = I915_READ(intel_hdmi->sdvox_reg); |
| |
| /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
| 281,9 → 285,9 |
|---|
| } |
| |
| if (mode != DRM_MODE_DPMS_ON) { |
| temp &= ~SDVO_ENABLE; |
| temp &= ~enable_bits; |
| } else { |
| temp |= SDVO_ENABLE; |
| temp |= enable_bits; |
| } |
| |
| I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 486,6 → 490,7 |
|---|
| struct intel_encoder *intel_encoder; |
| struct intel_connector *intel_connector; |
| struct intel_hdmi *intel_hdmi; |
| int i; |
| |
| intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
| if (!intel_hdmi) |
| 511,7 → 516,7 |
|---|
| connector->polled = DRM_CONNECTOR_POLL_HPD; |
| connector->interlace_allowed = 0; |
| connector->doublescan_allowed = 0; |
| intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| |
| /* Set up the DDC bus. */ |
| if (sdvox_reg == SDVOB) { |
| 538,10 → 543,14 |
|---|
| |
| intel_hdmi->sdvox_reg = sdvox_reg; |
| |
| if (!HAS_PCH_SPLIT(dev)) |
| if (!HAS_PCH_SPLIT(dev)) { |
| intel_hdmi->write_infoframe = i9xx_write_infoframe; |
| else |
| I915_WRITE(VIDEO_DIP_CTL, 0); |
| } else { |
| intel_hdmi->write_infoframe = ironlake_write_infoframe; |
| for_each_pipe(i) |
| I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| } |
| |
| drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
| |