| 206,17 → 206,8 |
|---|
| */ |
| |
| static int |
| intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp) |
| intel_dp_link_required(int pixel_clock, int bpp) |
| { |
| struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| int bpp = 24; |
| |
| if (check_bpp) |
| bpp = check_bpp; |
| else if (intel_crtc) |
| bpp = intel_crtc->bpp; |
| |
| return (pixel_clock * bpp + 9) / 10; |
| } |
| |
| 243,12 → 234,11 |
|---|
| return MODE_PANEL; |
| } |
| |
| mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0); |
| mode_rate = intel_dp_link_required(mode->clock, 24); |
| max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| |
| if (mode_rate > max_rate) { |
| mode_rate = intel_dp_link_required(intel_dp, |
| mode->clock, 18); |
| mode_rate = intel_dp_link_required(mode->clock, 18); |
| if (mode_rate > max_rate) |
| return MODE_CLOCK_HIGH; |
| else |
| 681,7 → 671,7 |
|---|
| int lane_count, clock; |
| int max_lane_count = intel_dp_max_lane_count(intel_dp); |
| int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
| int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0; |
| int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
| static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
| |
| if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
| 699,7 → 689,7 |
|---|
| for (clock = 0; clock <= max_clock; clock++) { |
| int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
| |
| if (intel_dp_link_required(intel_dp, mode->clock, bpp) |
| if (intel_dp_link_required(mode->clock, bpp) |
| <= link_avail) { |
| intel_dp->link_bw = bws[clock]; |
| intel_dp->lane_count = lane_count; |