37,6 → 37,8 |
#include <drm/i915_drm.h> |
#include "i915_drv.h" |
#include "i915_trace.h" |
#include <drm/drm_atomic.h> |
#include <drm/drm_atomic_helper.h> |
#include <drm/drm_dp_helper.h> |
#include <drm/drm_crtc_helper.h> |
#include <drm/drm_plane_helper.h> |
43,29 → 45,37 |
#include <drm/drm_rect.h> |
#include <linux/dma_remapping.h> |
|
/* Primary plane formats supported by all gen */ |
#define COMMON_PRIMARY_FORMATS \ |
DRM_FORMAT_C8, \ |
DRM_FORMAT_RGB565, \ |
DRM_FORMAT_XRGB8888, \ |
DRM_FORMAT_ARGB8888 |
|
/* Primary plane formats for gen <= 3 */ |
static const uint32_t intel_primary_formats_gen2[] = { |
COMMON_PRIMARY_FORMATS, |
static const uint32_t i8xx_primary_formats[] = { |
DRM_FORMAT_C8, |
DRM_FORMAT_RGB565, |
DRM_FORMAT_XRGB1555, |
DRM_FORMAT_ARGB1555, |
DRM_FORMAT_XRGB8888, |
}; |
|
/* Primary plane formats for gen >= 4 */ |
static const uint32_t intel_primary_formats_gen4[] = { |
COMMON_PRIMARY_FORMATS, \ |
static const uint32_t i965_primary_formats[] = { |
DRM_FORMAT_C8, |
DRM_FORMAT_RGB565, |
DRM_FORMAT_XRGB8888, |
DRM_FORMAT_XBGR8888, |
DRM_FORMAT_XRGB2101010, |
DRM_FORMAT_XBGR2101010, |
}; |
|
static const uint32_t skl_primary_formats[] = { |
DRM_FORMAT_C8, |
DRM_FORMAT_RGB565, |
DRM_FORMAT_XRGB8888, |
DRM_FORMAT_XBGR8888, |
DRM_FORMAT_ARGB8888, |
DRM_FORMAT_ABGR8888, |
DRM_FORMAT_XRGB2101010, |
DRM_FORMAT_ARGB2101010, |
DRM_FORMAT_XBGR2101010, |
DRM_FORMAT_ABGR2101010, |
DRM_FORMAT_YUYV, |
DRM_FORMAT_YVYU, |
DRM_FORMAT_UYVY, |
DRM_FORMAT_VYUY, |
}; |
|
/* Cursor formats */ |
76,12 → 86,10 |
void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
|
static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config); |
struct intel_crtc_state *pipe_config); |
static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config); |
struct intel_crtc_state *pipe_config); |
|
static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
int x, int y, struct drm_framebuffer *old_fb); |
static int intel_framebuffer_init(struct drm_device *dev, |
struct intel_framebuffer *ifb, |
struct drm_mode_fb_cmd2 *mode_cmd, |
95,18 → 103,21 |
static void haswell_set_pipeconf(struct drm_crtc *crtc); |
static void intel_set_pipe_csc(struct drm_crtc *crtc); |
static void vlv_prepare_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config); |
const struct intel_crtc_state *pipe_config); |
static void chv_prepare_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config); |
const struct intel_crtc_state *pipe_config); |
static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
struct intel_crtc_state *crtc_state); |
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
int num_connectors); |
static void skylake_pfit_enable(struct intel_crtc *crtc); |
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); |
static void ironlake_pfit_enable(struct intel_crtc *crtc); |
static void intel_modeset_setup_hw_state(struct drm_device *dev); |
static void intel_pre_disable_primary(struct drm_crtc *crtc); |
|
static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
{ |
if (!connector->mst_port) |
return connector->encoder; |
else |
return &connector->mst_port->mst_encoders[pipe]->base; |
} |
|
typedef struct { |
int min, max; |
} intel_range_t; |
122,6 → 133,42 |
intel_p2_t p2; |
}; |
|
/* returns HPLL frequency in kHz */ |
static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
{ |
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
|
/* Obtain SKU information */ |
mutex_lock(&dev_priv->sb_lock); |
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
CCK_FUSE_HPLL_FREQ_MASK; |
mutex_unlock(&dev_priv->sb_lock); |
|
return vco_freq[hpll_freq] * 1000; |
} |
|
static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
const char *name, u32 reg) |
{ |
u32 val; |
int divider; |
|
if (dev_priv->hpll_freq == 0) |
dev_priv->hpll_freq = valleyview_get_vco(dev_priv); |
|
mutex_lock(&dev_priv->sb_lock); |
val = vlv_cck_read(dev_priv, reg); |
mutex_unlock(&dev_priv->sb_lock); |
|
divider = val & CCK_FREQUENCY_VALUES; |
|
WARN((val & CCK_FREQUENCY_STATUS) != |
(divider << CCK_FREQUENCY_STATUS_SHIFT), |
"%s change in progress\n", name); |
|
return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
} |
|
int |
intel_pch_rawclk(struct drm_device *dev) |
{ |
132,6 → 179,50 |
return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
} |
|
/* hrawclock is 1/4 the FSB frequency */ |
int intel_hrawclk(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t clkcfg; |
|
/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
if (IS_VALLEYVIEW(dev)) |
return 200; |
|
clkcfg = I915_READ(CLKCFG); |
switch (clkcfg & CLKCFG_FSB_MASK) { |
case CLKCFG_FSB_400: |
return 100; |
case CLKCFG_FSB_533: |
return 133; |
case CLKCFG_FSB_667: |
return 166; |
case CLKCFG_FSB_800: |
return 200; |
case CLKCFG_FSB_1067: |
return 266; |
case CLKCFG_FSB_1333: |
return 333; |
/* these two are just a guess; one of them might be right */ |
case CLKCFG_FSB_1600: |
case CLKCFG_FSB_1600_ALT: |
return 400; |
default: |
return 133; |
} |
} |
|
static void intel_update_czclk(struct drm_i915_private *dev_priv) |
{ |
if (!IS_VALLEYVIEW(dev_priv)) |
return; |
|
dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", |
CCK_CZ_CLOCK_CONTROL); |
|
DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); |
} |
|
static inline u32 /* units of 100MHz */ |
intel_fdi_link_freq(struct drm_device *dev) |
{ |
387,7 → 478,7 |
* them would make no difference. |
*/ |
.dot = { .min = 25000 * 5, .max = 540000 * 5}, |
.vco = { .min = 4860000, .max = 6700000 }, |
.vco = { .min = 4800000, .max = 6480000 }, |
.n = { .min = 1, .max = 1 }, |
.m1 = { .min = 2, .max = 2 }, |
.m2 = { .min = 24 << 22, .max = 175 << 22 }, |
395,14 → 486,22 |
.p2 = { .p2_slow = 1, .p2_fast = 14 }, |
}; |
|
static void vlv_clock(int refclk, intel_clock_t *clock) |
static const intel_limit_t intel_limits_bxt = { |
/* FIXME: find real dot limits */ |
.dot = { .min = 0, .max = INT_MAX }, |
.vco = { .min = 4800000, .max = 6700000 }, |
.n = { .min = 1, .max = 1 }, |
.m1 = { .min = 2, .max = 2 }, |
/* FIXME: find real m2 limits */ |
.m2 = { .min = 2 << 22, .max = 255 << 22 }, |
.p1 = { .min = 2, .max = 4 }, |
.p2 = { .p2_slow = 1, .p2_fast = 20 }, |
}; |
|
static bool |
needs_modeset(struct drm_crtc_state *state) |
{ |
clock->m = clock->m1 * clock->m2; |
clock->p = clock->p1 * clock->p2; |
if (WARN_ON(clock->n == 0 || clock->p == 0)) |
return; |
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
return drm_atomic_crtc_needs_modeset(state); |
} |
|
/** |
426,25 → 525,38 |
* intel_pipe_has_type() but looking at encoder->new_crtc instead of |
* encoder->crtc. |
*/ |
static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) |
static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
int type) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_atomic_state *state = crtc_state->base.state; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
struct intel_encoder *encoder; |
int i, num_connectors = 0; |
|
for_each_intel_encoder(dev, encoder) |
if (encoder->new_crtc == crtc && encoder->type == type) |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != crtc_state->base.crtc) |
continue; |
|
num_connectors++; |
|
encoder = to_intel_encoder(connector_state->best_encoder); |
if (encoder->type == type) |
return true; |
} |
|
WARN_ON(num_connectors == 0); |
|
return false; |
} |
|
static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
int refclk) |
static const intel_limit_t * |
intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
const intel_limit_t *limit; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
if (intel_is_dual_link_lvds(dev)) { |
if (refclk == 100000) |
limit = &intel_limits_ironlake_dual_lvds_100m; |
462,20 → 574,21 |
return limit; |
} |
|
static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
static const intel_limit_t * |
intel_g4x_limit(struct intel_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
const intel_limit_t *limit; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
if (intel_is_dual_link_lvds(dev)) |
limit = &intel_limits_g4x_dual_channel_lvds; |
else |
limit = &intel_limits_g4x_single_channel_lvds; |
} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { |
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
limit = &intel_limits_g4x_hdmi; |
} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
limit = &intel_limits_g4x_sdvo; |
} else /* The option is for other outputs */ |
limit = &intel_limits_i9xx_sdvo; |
483,17 → 596,20 |
return limit; |
} |
|
static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
static const intel_limit_t * |
intel_limit(struct intel_crtc_state *crtc_state, int refclk) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
const intel_limit_t *limit; |
|
if (HAS_PCH_SPLIT(dev)) |
limit = intel_ironlake_limit(crtc, refclk); |
if (IS_BROXTON(dev)) |
limit = &intel_limits_bxt; |
else if (HAS_PCH_SPLIT(dev)) |
limit = intel_ironlake_limit(crtc_state, refclk); |
else if (IS_G4X(dev)) { |
limit = intel_g4x_limit(crtc); |
limit = intel_g4x_limit(crtc_state); |
} else if (IS_PINEVIEW(dev)) { |
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
limit = &intel_limits_pineview_lvds; |
else |
limit = &intel_limits_pineview_sdvo; |
502,14 → 618,14 |
} else if (IS_VALLEYVIEW(dev)) { |
limit = &intel_limits_vlv; |
} else if (!IS_GEN2(dev)) { |
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
limit = &intel_limits_i9xx_lvds; |
else |
limit = &intel_limits_i9xx_sdvo; |
} else { |
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
limit = &intel_limits_i8xx_lvds; |
else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
limit = &intel_limits_i8xx_dvo; |
else |
limit = &intel_limits_i8xx_dac; |
517,15 → 633,25 |
return limit; |
} |
|
/* |
* Platform specific helpers to calculate the port PLL loopback- (clock.m), |
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
* (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
* The helpers' return value is the rate of the clock that is fed to the |
* display engine's pipe which can be the above fast dot clock rate or a |
* divided-down version of it. |
*/ |
/* m1 is reserved as 0 in Pineview, n is a ring counter */ |
static void pineview_clock(int refclk, intel_clock_t *clock) |
static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
{ |
clock->m = clock->m2 + 2; |
clock->p = clock->p1 * clock->p2; |
if (WARN_ON(clock->n == 0 || clock->p == 0)) |
return; |
return 0; |
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
return clock->dot; |
} |
|
static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
533,25 → 659,41 |
return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
} |
|
static void i9xx_clock(int refclk, intel_clock_t *clock) |
static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
{ |
clock->m = i9xx_dpll_compute_m(clock); |
clock->p = clock->p1 * clock->p2; |
if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
return; |
return 0; |
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
return clock->dot; |
} |
|
static void chv_clock(int refclk, intel_clock_t *clock) |
static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
{ |
clock->m = clock->m1 * clock->m2; |
clock->p = clock->p1 * clock->p2; |
if (WARN_ON(clock->n == 0 || clock->p == 0)) |
return; |
return 0; |
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
return clock->dot / 5; |
} |
|
int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
{ |
clock->m = clock->m1 * clock->m2; |
clock->p = clock->p1 * clock->p2; |
if (WARN_ON(clock->n == 0 || clock->p == 0)) |
return 0; |
clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
clock->n << 22); |
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
|
return clock->dot / 5; |
} |
|
#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
573,11 → 715,11 |
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
INTELPllInvalid("m1 out of range\n"); |
|
if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
if (clock->m1 <= clock->m2) |
INTELPllInvalid("m1 <= m2\n"); |
|
if (!IS_VALLEYVIEW(dev)) { |
if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
if (clock->p < limit->p.min || limit->p.max < clock->p) |
INTELPllInvalid("p out of range\n"); |
if (clock->m < limit->m.min || limit->m.max < clock->m) |
595,16 → 737,14 |
return true; |
} |
|
static bool |
i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
static int |
i9xx_select_p2_div(const intel_limit_t *limit, |
const struct intel_crtc_state *crtc_state, |
int target) |
{ |
struct drm_device *dev = crtc->base.dev; |
intel_clock_t clock; |
int err = target; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
/* |
* For LVDS just rely on its current settings for dual-channel. |
* We haven't figured out how to reliably set up different |
611,18 → 751,31 |
* single/dual channel state, if we even can. |
*/ |
if (intel_is_dual_link_lvds(dev)) |
clock.p2 = limit->p2.p2_fast; |
return limit->p2.p2_fast; |
else |
clock.p2 = limit->p2.p2_slow; |
return limit->p2.p2_slow; |
} else { |
if (target < limit->p2.dot_limit) |
clock.p2 = limit->p2.p2_slow; |
return limit->p2.p2_slow; |
else |
clock.p2 = limit->p2.p2_fast; |
return limit->p2.p2_fast; |
} |
} |
|
static bool |
i9xx_find_best_dpll(const intel_limit_t *limit, |
struct intel_crtc_state *crtc_state, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
{ |
struct drm_device *dev = crtc_state->base.crtc->dev; |
intel_clock_t clock; |
int err = target; |
|
memset(best_clock, 0, sizeof(*best_clock)); |
|
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
|
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
clock.m1++) { |
for (clock.m2 = limit->m2.min; |
635,7 → 788,7 |
clock.p1 <= limit->p1.max; clock.p1++) { |
int this_err; |
|
i9xx_clock(refclk, &clock); |
i9xx_calc_dpll_params(refclk, &clock); |
if (!intel_PLL_is_valid(dev, limit, |
&clock)) |
continue; |
657,33 → 810,19 |
} |
|
static bool |
pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
pnv_find_best_dpll(const intel_limit_t *limit, |
struct intel_crtc_state *crtc_state, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
intel_clock_t clock; |
int err = target; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
/* |
* For LVDS just rely on its current settings for dual-channel. |
* We haven't figured out how to reliably set up different |
* single/dual channel state, if we even can. |
*/ |
if (intel_is_dual_link_lvds(dev)) |
clock.p2 = limit->p2.p2_fast; |
else |
clock.p2 = limit->p2.p2_slow; |
} else { |
if (target < limit->p2.dot_limit) |
clock.p2 = limit->p2.p2_slow; |
else |
clock.p2 = limit->p2.p2_fast; |
} |
|
memset(best_clock, 0, sizeof(*best_clock)); |
|
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
|
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
clock.m1++) { |
for (clock.m2 = limit->m2.min; |
694,7 → 833,7 |
clock.p1 <= limit->p1.max; clock.p1++) { |
int this_err; |
|
pineview_clock(refclk, &clock); |
pnv_calc_dpll_params(refclk, &clock); |
if (!intel_PLL_is_valid(dev, limit, |
&clock)) |
continue; |
716,31 → 855,22 |
} |
|
static bool |
g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
g4x_find_best_dpll(const intel_limit_t *limit, |
struct intel_crtc_state *crtc_state, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
intel_clock_t clock; |
int max_n; |
bool found; |
bool found = false; |
/* approximately equals target * 0.00585 */ |
int err_most = (target >> 8) + (target >> 9); |
found = false; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
if (intel_is_dual_link_lvds(dev)) |
clock.p2 = limit->p2.p2_fast; |
else |
clock.p2 = limit->p2.p2_slow; |
} else { |
if (target < limit->p2.dot_limit) |
clock.p2 = limit->p2.p2_slow; |
else |
clock.p2 = limit->p2.p2_fast; |
} |
memset(best_clock, 0, sizeof(*best_clock)); |
|
memset(best_clock, 0, sizeof(*best_clock)); |
clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
|
max_n = limit->n.max; |
/* based on hardware requirement, prefer smaller n to precision */ |
for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
753,7 → 883,7 |
clock.p1 >= limit->p1.min; clock.p1--) { |
int this_err; |
|
i9xx_clock(refclk, &clock); |
i9xx_calc_dpll_params(refclk, &clock); |
if (!intel_PLL_is_valid(dev, limit, |
&clock)) |
continue; |
772,11 → 902,53 |
return found; |
} |
|
/* |
* Check if the calculated PLL configuration is more optimal compared to the |
* best configuration and error found so far. Return the calculated error. |
*/ |
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
const intel_clock_t *calculated_clock, |
const intel_clock_t *best_clock, |
unsigned int best_error_ppm, |
unsigned int *error_ppm) |
{ |
/* |
* For CHV ignore the error and consider only the P value. |
* Prefer a bigger P value based on HW requirements. |
*/ |
if (IS_CHERRYVIEW(dev)) { |
*error_ppm = 0; |
|
return calculated_clock->p > best_clock->p; |
} |
|
if (WARN_ON_ONCE(!target_freq)) |
return false; |
|
*error_ppm = div_u64(1000000ULL * |
abs(target_freq - calculated_clock->dot), |
target_freq); |
/* |
* Prefer a better P value over a better (smaller) error if the error |
* is small. Ensure this preference for future configurations too by |
* setting the error to 0. |
*/ |
if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
*error_ppm = 0; |
|
return true; |
} |
|
return *error_ppm + 10 < best_error_ppm; |
} |
|
static bool |
vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
vlv_find_best_dpll(const intel_limit_t *limit, |
struct intel_crtc_state *crtc_state, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
{ |
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
struct drm_device *dev = crtc->base.dev; |
intel_clock_t clock; |
unsigned int bestppm = 1000000; |
796,50 → 968,49 |
clock.p = clock.p1 * clock.p2; |
/* based on hardware requirement, prefer bigger m1,m2 values */ |
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
unsigned int ppm, diff; |
unsigned int ppm; |
|
clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
refclk * clock.m1); |
|
vlv_clock(refclk, &clock); |
vlv_calc_dpll_params(refclk, &clock); |
|
if (!intel_PLL_is_valid(dev, limit, |
&clock)) |
continue; |
|
diff = abs(clock.dot - target); |
ppm = div_u64(1000000ULL * diff, target); |
if (!vlv_PLL_is_optimal(dev, target, |
&clock, |
best_clock, |
bestppm, &ppm)) |
continue; |
|
if (ppm < 100 && clock.p > best_clock->p) { |
bestppm = 0; |
*best_clock = clock; |
found = true; |
} |
|
if (bestppm >= 10 && ppm < bestppm - 10) { |
bestppm = ppm; |
*best_clock = clock; |
found = true; |
} |
} |
} |
} |
} |
|
return found; |
} |
|
static bool |
chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
chv_find_best_dpll(const intel_limit_t *limit, |
struct intel_crtc_state *crtc_state, |
int target, int refclk, intel_clock_t *match_clock, |
intel_clock_t *best_clock) |
{ |
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
struct drm_device *dev = crtc->base.dev; |
unsigned int best_error_ppm; |
intel_clock_t clock; |
uint64_t m2; |
int found = false; |
|
memset(best_clock, 0, sizeof(*best_clock)); |
best_error_ppm = 1000000; |
|
/* |
* Based on hardware doc, the n always set to 1, and m1 always |
853,6 → 1024,7 |
for (clock.p2 = limit->p2.p2_fast; |
clock.p2 >= limit->p2.p2_slow; |
clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
unsigned int error_ppm; |
|
clock.p = clock.p1 * clock.p2; |
|
864,23 → 1036,33 |
|
clock.m2 = m2; |
|
chv_clock(refclk, &clock); |
chv_calc_dpll_params(refclk, &clock); |
|
if (!intel_PLL_is_valid(dev, limit, &clock)) |
continue; |
|
/* based on hardware requirement, prefer bigger p |
*/ |
if (clock.p > best_clock->p) { |
if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
best_error_ppm, &error_ppm)) |
continue; |
|
*best_clock = clock; |
best_error_ppm = error_ppm; |
found = true; |
} |
} |
} |
|
return found; |
} |
|
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
intel_clock_t *best_clock) |
{ |
int refclk = i9xx_get_refclk(crtc_state, 0); |
|
return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, |
target_clock, refclk, NULL, best_clock); |
} |
|
bool intel_crtc_active(struct drm_crtc *crtc) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
893,9 → 1075,13 |
* |
* We can ditch the crtc->primary->fb check as soon as we can |
* properly reconstruct framebuffers. |
* |
* FIXME: The intel_crtc->active here should be switched to |
* crtc->state->active once we have proper CRTC states wired up |
* for atomic. |
*/ |
return intel_crtc->active && crtc->primary->fb && |
intel_crtc->config.adjusted_mode.crtc_clock; |
return intel_crtc->active && crtc->primary->state->fb && |
intel_crtc->config->base.adjusted_mode.crtc_clock; |
} |
|
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
904,7 → 1090,7 |
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
return intel_crtc->config.cpu_transcoder; |
return intel_crtc->config->cpu_transcoder; |
} |
|
static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
920,7 → 1106,7 |
line_mask = DSL_LINEMASK_GEN3; |
|
line1 = I915_READ(reg) & line_mask; |
mdelay(5); |
msleep(5); |
line2 = I915_READ(reg) & line_mask; |
|
return line1 == line2; |
946,7 → 1132,7 |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
enum pipe pipe = crtc->pipe; |
|
if (INTEL_INFO(dev)->gen >= 4) { |
963,51 → 1149,6 |
} |
} |
|
/* |
* ibx_digital_port_connected - is the specified port connected? |
* @dev_priv: i915 private structure |
* @port: the port to test |
* |
* Returns true if @port is connected, false otherwise. |
*/ |
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
struct intel_digital_port *port) |
{ |
u32 bit; |
|
if (HAS_PCH_IBX(dev_priv->dev)) { |
switch (port->port) { |
case PORT_B: |
bit = SDE_PORTB_HOTPLUG; |
break; |
case PORT_C: |
bit = SDE_PORTC_HOTPLUG; |
break; |
case PORT_D: |
bit = SDE_PORTD_HOTPLUG; |
break; |
default: |
return true; |
} |
} else { |
switch (port->port) { |
case PORT_B: |
bit = SDE_PORTB_HOTPLUG_CPT; |
break; |
case PORT_C: |
bit = SDE_PORTC_HOTPLUG_CPT; |
break; |
case PORT_D: |
bit = SDE_PORTD_HOTPLUG_CPT; |
break; |
default: |
return true; |
} |
} |
|
return I915_READ(SDEISR) & bit; |
} |
|
static const char *state_string(bool enabled) |
{ |
return enabled ? "on" : "off"; |
1017,14 → 1158,12 |
void assert_pll(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
|
reg = DPLL(pipe); |
val = I915_READ(reg); |
val = I915_READ(DPLL(pipe)); |
cur_state = !!(val & DPLL_VCO_ENABLE); |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"PLL state assertion failure (expected %s, current %s)\n", |
state_string(state), state_string(cur_state)); |
} |
1035,12 → 1174,12 |
u32 val; |
bool cur_state; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
|
cur_state = val & DSI_PLL_VCO_EN; |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"DSI PLL state assertion failure (expected %s, current %s)\n", |
state_string(state), state_string(cur_state)); |
} |
1052,10 → 1191,10 |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
if (crtc->config.shared_dpll < 0) |
if (crtc->config->shared_dpll < 0) |
return NULL; |
|
return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
} |
|
/* For ILK+ */ |
1071,7 → 1210,7 |
return; |
|
cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"%s assertion failure (expected %s, current %s)\n", |
pll->name, state_string(state), state_string(cur_state)); |
} |
1079,8 → 1218,6 |
static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
pipe); |
1087,15 → 1224,13 |
|
if (HAS_DDI(dev_priv->dev)) { |
/* DDI does not have a specific FDI_TX register */ |
reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
val = I915_READ(reg); |
u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
} else { |
reg = FDI_TX_CTL(pipe); |
val = I915_READ(reg); |
u32 val = I915_READ(FDI_TX_CTL(pipe)); |
cur_state = !!(val & FDI_TX_ENABLE); |
} |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"FDI TX state assertion failure (expected %s, current %s)\n", |
state_string(state), state_string(cur_state)); |
} |
1105,14 → 1240,12 |
static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
|
reg = FDI_RX_CTL(pipe); |
val = I915_READ(reg); |
val = I915_READ(FDI_RX_CTL(pipe)); |
cur_state = !!(val & FDI_RX_ENABLE); |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"FDI RX state assertion failure (expected %s, current %s)\n", |
state_string(state), state_string(cur_state)); |
} |
1122,7 → 1255,6 |
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
enum pipe pipe) |
{ |
int reg; |
u32 val; |
|
/* ILK FDI PLL is always enabled */ |
1133,22 → 1265,19 |
if (HAS_DDI(dev_priv->dev)) |
return; |
|
reg = FDI_TX_CTL(pipe); |
val = I915_READ(reg); |
WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
val = I915_READ(FDI_TX_CTL(pipe)); |
I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
} |
|
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
|
reg = FDI_RX_CTL(pipe); |
val = I915_READ(reg); |
val = I915_READ(FDI_RX_CTL(pipe)); |
cur_state = !!(val & FDI_RX_PLL_ENABLE); |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"FDI RX PLL assertion failure (expected %s, current %s)\n", |
state_string(state), state_string(cur_state)); |
} |
1190,7 → 1319,7 |
((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
locked = false; |
|
WARN(panel_pipe == pipe && locked, |
I915_STATE_WARN(panel_pipe == pipe && locked, |
"panel assertion failure, pipe %c regs locked\n", |
pipe_name(pipe)); |
} |
1202,11 → 1331,11 |
bool cur_state; |
|
if (IS_845G(dev) || IS_I865G(dev)) |
cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
else |
cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
|
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"cursor on pipe %c assertion failure (expected %s, current %s)\n", |
pipe_name(pipe), state_string(state), state_string(cur_state)); |
} |
1216,8 → 1345,6 |
void assert_pipe(struct drm_i915_private *dev_priv, |
enum pipe pipe, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
pipe); |
1231,12 → 1358,11 |
POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
cur_state = false; |
} else { |
reg = PIPECONF(cpu_transcoder); |
val = I915_READ(reg); |
u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
cur_state = !!(val & PIPECONF_ENABLE); |
} |
|
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"pipe %c assertion failure (expected %s, current %s)\n", |
pipe_name(pipe), state_string(state), state_string(cur_state)); |
} |
1244,14 → 1370,12 |
static void assert_plane(struct drm_i915_private *dev_priv, |
enum plane plane, bool state) |
{ |
int reg; |
u32 val; |
bool cur_state; |
|
reg = DSPCNTR(plane); |
val = I915_READ(reg); |
val = I915_READ(DSPCNTR(plane)); |
cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
WARN(cur_state != state, |
I915_STATE_WARN(cur_state != state, |
"plane %c assertion failure (expected %s, current %s)\n", |
plane_name(plane), state_string(state), state_string(cur_state)); |
} |
1263,15 → 1387,12 |
enum pipe pipe) |
{ |
struct drm_device *dev = dev_priv->dev; |
int reg, i; |
u32 val; |
int cur_pipe; |
int i; |
|
/* Primary planes are fixed to pipes on gen4+ */ |
if (INTEL_INFO(dev)->gen >= 4) { |
reg = DSPCNTR(pipe); |
val = I915_READ(reg); |
WARN(val & DISPLAY_PLANE_ENABLE, |
u32 val = I915_READ(DSPCNTR(pipe)); |
I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
"plane %c assertion failure, should be disabled but not\n", |
plane_name(pipe)); |
return; |
1279,11 → 1400,10 |
|
/* Need to check both planes against the pipe */ |
for_each_pipe(dev_priv, i) { |
reg = DSPCNTR(i); |
val = I915_READ(reg); |
cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
u32 val = I915_READ(DSPCNTR(i)); |
enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
DISPPLANE_SEL_PIPE_SHIFT; |
WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
"plane %c assertion failure, should be off on pipe %c but is still active\n", |
plane_name(i), pipe_name(pipe)); |
} |
1293,34 → 1413,30 |
enum pipe pipe) |
{ |
struct drm_device *dev = dev_priv->dev; |
int reg, sprite; |
u32 val; |
int sprite; |
|
if (INTEL_INFO(dev)->gen >= 9) { |
for_each_sprite(pipe, sprite) { |
val = I915_READ(PLANE_CTL(pipe, sprite)); |
WARN(val & PLANE_CTL_ENABLE, |
for_each_sprite(dev_priv, pipe, sprite) { |
u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
"plane %d assertion failure, should be off on pipe %c but is still active\n", |
sprite, pipe_name(pipe)); |
} |
} else if (IS_VALLEYVIEW(dev)) { |
for_each_sprite(pipe, sprite) { |
reg = SPCNTR(pipe, sprite); |
val = I915_READ(reg); |
WARN(val & SP_ENABLE, |
for_each_sprite(dev_priv, pipe, sprite) { |
u32 val = I915_READ(SPCNTR(pipe, sprite)); |
I915_STATE_WARN(val & SP_ENABLE, |
"sprite %c assertion failure, should be off on pipe %c but is still active\n", |
sprite_name(pipe, sprite), pipe_name(pipe)); |
} |
} else if (INTEL_INFO(dev)->gen >= 7) { |
reg = SPRCTL(pipe); |
val = I915_READ(reg); |
WARN(val & SPRITE_ENABLE, |
u32 val = I915_READ(SPRCTL(pipe)); |
I915_STATE_WARN(val & SPRITE_ENABLE, |
"sprite %c assertion failure, should be off on pipe %c but is still active\n", |
plane_name(pipe), pipe_name(pipe)); |
} else if (INTEL_INFO(dev)->gen >= 5) { |
reg = DVSCNTR(pipe); |
val = I915_READ(reg); |
WARN(val & DVS_ENABLE, |
u32 val = I915_READ(DVSCNTR(pipe)); |
I915_STATE_WARN(val & DVS_ENABLE, |
"sprite %c assertion failure, should be off on pipe %c but is still active\n", |
plane_name(pipe), pipe_name(pipe)); |
} |
1328,7 → 1444,7 |
|
static void assert_vblank_disabled(struct drm_crtc *crtc) |
{ |
if (WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
drm_crtc_vblank_put(crtc); |
} |
|
1337,25 → 1453,23 |
u32 val; |
bool enabled; |
|
WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
|
val = I915_READ(PCH_DREF_CONTROL); |
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
DREF_SUPERSPREAD_SOURCE_MASK)); |
WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
} |
|
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
enum pipe pipe) |
{ |
int reg; |
u32 val; |
bool enabled; |
|
reg = PCH_TRANSCONF(pipe); |
val = I915_READ(reg); |
val = I915_READ(PCH_TRANSCONF(pipe)); |
enabled = !!(val & TRANS_ENABLE); |
WARN(enabled, |
I915_STATE_WARN(enabled, |
"transcoder assertion failed, should be off on pipe %c but is still active\n", |
pipe_name(pipe)); |
} |
1435,11 → 1549,11 |
enum pipe pipe, int reg, u32 port_sel) |
{ |
u32 val = I915_READ(reg); |
WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
reg, pipe_name(pipe)); |
|
WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
&& (val & DP_PIPEB_SELECT), |
"IBX PCH dp port still using transcoder B\n"); |
} |
1448,11 → 1562,11 |
enum pipe pipe, int reg) |
{ |
u32 val = I915_READ(reg); |
WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
reg, pipe_name(pipe)); |
|
WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
&& (val & SDVO_PIPE_B_SELECT), |
"IBX PCH hdmi port still using transcoder B\n"); |
} |
1460,7 → 1574,6 |
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
enum pipe pipe) |
{ |
int reg; |
u32 val; |
|
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1467,15 → 1580,13 |
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
|
reg = PCH_ADPA; |
val = I915_READ(reg); |
WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
val = I915_READ(PCH_ADPA); |
I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
"PCH VGA enabled on transcoder %c, should be disabled\n", |
pipe_name(pipe)); |
|
reg = PCH_LVDS; |
val = I915_READ(reg); |
WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
val = I915_READ(PCH_LVDS); |
I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
"PCH LVDS enabled on transcoder %c, should be disabled\n", |
pipe_name(pipe)); |
|
1484,28 → 1595,8 |
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
} |
|
static void intel_init_dpio(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (!IS_VALLEYVIEW(dev)) |
return; |
|
/* |
* IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), |
* CHV x1 PHY (DP/HDMI D) |
* IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) |
*/ |
if (IS_CHERRYVIEW(dev)) { |
DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; |
DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; |
} else { |
DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
} |
} |
|
static void vlv_enable_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config) |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
1544,7 → 1635,7 |
} |
|
static void chv_enable_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config) |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
1556,7 → 1647,7 |
|
BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
/* Enable back the 10bit clock to display controller */ |
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
1563,6 → 1654,8 |
tmp |= DPIO_DCLKP_EN; |
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); |
|
mutex_unlock(&dev_priv->sb_lock); |
|
/* |
* Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
*/ |
1578,8 → 1671,6 |
/* not sure when this should be written */ |
I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
POSTING_READ(DPLL_MD(pipe)); |
|
mutex_unlock(&dev_priv->dpio_lock); |
} |
|
static int intel_num_dvo_pipes(struct drm_device *dev) |
1588,7 → 1679,7 |
int count = 0; |
|
for_each_intel_crtc(dev, crtc) |
count += crtc->active && |
count += crtc->base.state->active && |
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
|
return count; |
1599,7 → 1690,7 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int reg = DPLL(crtc->pipe); |
u32 dpll = crtc->config.dpll_hw_state.dpll; |
u32 dpll = crtc->config->dpll_hw_state.dpll; |
|
assert_pipe_disabled(dev_priv, crtc->pipe); |
|
1623,6 → 1714,15 |
I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); |
} |
|
/* |
* Apparently we need to have VGA mode enabled prior to changing |
* the P1/P2 dividers. Otherwise the DPLL will keep using the old |
* dividers, even though the register value does change. |
*/ |
I915_WRITE(reg, 0); |
|
I915_WRITE(reg, dpll); |
|
/* Wait for the clocks to stabilize. */ |
POSTING_READ(reg); |
udelay(150); |
1629,7 → 1729,7 |
|
if (INTEL_INFO(dev)->gen >= 4) { |
I915_WRITE(DPLL_MD(crtc->pipe), |
crtc->config.dpll_hw_state.dpll_md); |
crtc->config->dpll_hw_state.dpll_md); |
} else { |
/* The pixel multiplier can only be updated once the |
* DPLL is enabled and the clocks are stable. |
1669,7 → 1769,7 |
/* Disable DVO 2x clock on both PLLs if necessary */ |
if (IS_I830(dev) && |
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
intel_num_dvo_pipes(dev) == 1) { |
!intel_num_dvo_pipes(dev)) { |
I915_WRITE(DPLL(PIPE_B), |
I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); |
I915_WRITE(DPLL(PIPE_A), |
1684,13 → 1784,13 |
/* Make sure the pipe isn't still relying on us */ |
assert_pipe_disabled(dev_priv, pipe); |
|
I915_WRITE(DPLL(pipe), 0); |
I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
POSTING_READ(DPLL(pipe)); |
} |
|
static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
{ |
u32 val = 0; |
u32 val; |
|
/* Make sure the pipe isn't still relying on us */ |
assert_pipe_disabled(dev_priv, pipe); |
1699,8 → 1799,9 |
* Leave integrated clock source and reference clock enabled for pipe B. |
* The latter is needed for VGA hotplug / manual detection. |
*/ |
val = DPLL_VGA_MODE_DIS; |
if (pipe == PIPE_B) |
val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
I915_WRITE(DPLL(pipe), val); |
POSTING_READ(DPLL(pipe)); |
|
1715,13 → 1816,14 |
assert_pipe_disabled(dev_priv, pipe); |
|
/* Set PLL en = 0 */ |
val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
val = DPLL_SSC_REF_CLK_CHV | |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
if (pipe != PIPE_A) |
val |= DPLL_INTEGRATED_CRI_CLK_VLV; |
I915_WRITE(DPLL(pipe), val); |
POSTING_READ(DPLL(pipe)); |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
/* Disable 10bit clock to display controller */ |
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); |
1728,22 → 1830,12 |
val &= ~DPIO_DCLKP_EN; |
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); |
|
/* disable left/right clock distribution */ |
if (pipe != PIPE_B) { |
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
} else { |
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
mutex_unlock(&dev_priv->dpio_lock); |
} |
|
void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
struct intel_digital_port *dport) |
struct intel_digital_port *dport, |
unsigned int expected_mask) |
{ |
u32 port_mask; |
int dpll_reg; |
1756,6 → 1848,7 |
case PORT_C: |
port_mask = DPLL_PORTC_READY_MASK; |
dpll_reg = DPLL(0); |
expected_mask <<= 4; |
break; |
case PORT_D: |
port_mask = DPLL_PORTD_READY_MASK; |
1765,9 → 1858,9 |
BUG(); |
} |
|
if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
port_name(dport->port), I915_READ(dpll_reg)); |
if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); |
} |
|
static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1834,13 → 1927,15 |
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
|
/* PCH only available on ILK+ */ |
BUG_ON(INTEL_INFO(dev)->gen < 5); |
if (WARN_ON(pll == NULL)) |
if (INTEL_INFO(dev)->gen < 5) |
return; |
|
if (WARN_ON(pll->config.crtc_mask == 0)) |
if (pll == NULL) |
return; |
|
if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
return; |
|
DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
pll->name, pll->active, pll->on, |
crtc->base.base.id); |
1896,10 → 1991,14 |
|
if (HAS_PCH_IBX(dev_priv->dev)) { |
/* |
* make the BPC in transcoder be consistent with |
* that in pipeconf reg. |
* Make the BPC in transcoder be consistent with |
* that in pipeconf reg. For HDMI we must use 8bpc |
* here for both 8bpc and 12bpc. |
*/ |
val &= ~PIPECONF_BPC_MASK; |
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
val |= PIPECONF_8BPC; |
else |
val |= pipeconf_val & PIPECONF_BPC_MASK; |
} |
|
1931,9 → 2030,9 |
assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
|
/* Workaround: set timing override bit. */ |
val = I915_READ(_TRANSA_CHICKEN2); |
val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
I915_WRITE(_TRANSA_CHICKEN2, val); |
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
|
val = TRANS_ENABLE; |
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
1991,9 → 2090,9 |
DRM_ERROR("Failed to disable PCH transcoder\n"); |
|
/* Workaround: clear timing override bit. */ |
val = I915_READ(_TRANSA_CHICKEN2); |
val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
I915_WRITE(_TRANSA_CHICKEN2, val); |
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
} |
|
/** |
2014,6 → 2113,8 |
int reg; |
u32 val; |
|
DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
|
assert_planes_disabled(dev_priv, pipe); |
assert_cursor_disabled(dev_priv, pipe); |
assert_sprites_disabled(dev_priv, pipe); |
2028,13 → 2129,13 |
* a plane. On ILK+ the pipe PLLs are integrated, so we don't |
* need the check. |
*/ |
if (!HAS_PCH_SPLIT(dev_priv->dev)) |
if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
assert_dsi_pll_enabled(dev_priv); |
else |
assert_pll_enabled(dev_priv, pipe); |
else { |
if (crtc->config.has_pch_encoder) { |
if (crtc->config->has_pch_encoder) { |
/* if driving the PCH, we need FDI enabled */ |
assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
assert_fdi_tx_pll_enabled(dev_priv, |
2068,11 → 2169,13 |
static void intel_disable_pipe(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
enum pipe pipe = crtc->pipe; |
int reg; |
u32 val; |
|
DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
|
/* |
* Make sure planes won't keep trying to pump pixels to us, |
* or we might hang the display. |
2090,7 → 2193,7 |
* Double wide has implications for planes |
* so best keep it disabled when not needed. |
*/ |
if (crtc->config.double_wide) |
if (crtc->config->double_wide) |
val &= ~PIPECONF_DOUBLE_WIDE; |
|
/* Don't disable pipe or pipe PLLs if needed */ |
2103,121 → 2206,148 |
intel_wait_for_pipe_off(crtc); |
} |
|
/* |
* Plane regs are double buffered, going from enabled->disabled needs a |
* trigger in order to latch. The display address reg provides this. |
*/ |
void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
enum plane plane) |
static bool need_vtd_wa(struct drm_device *dev) |
{ |
struct drm_device *dev = dev_priv->dev; |
u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
|
I915_WRITE(reg, I915_READ(reg)); |
POSTING_READ(reg); |
#ifdef CONFIG_INTEL_IOMMU |
if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
return true; |
#endif |
return false; |
} |
|
/** |
* intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
* @plane: plane to be enabled |
* @crtc: crtc for the plane |
* |
* Enable @plane on @crtc, making sure that the pipe is running first. |
*/ |
static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
struct drm_crtc *crtc) |
unsigned int |
intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
uint64_t fb_format_modifier, unsigned int plane) |
{ |
struct drm_device *dev = plane->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
unsigned int tile_height; |
uint32_t pixel_bytes; |
|
/* If the pipe isn't enabled, we can't pump pixels and may hang */ |
assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
switch (fb_format_modifier) { |
case DRM_FORMAT_MOD_NONE: |
tile_height = 1; |
break; |
case I915_FORMAT_MOD_X_TILED: |
tile_height = IS_GEN2(dev) ? 16 : 8; |
break; |
case I915_FORMAT_MOD_Y_TILED: |
tile_height = 32; |
break; |
case I915_FORMAT_MOD_Yf_TILED: |
pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
switch (pixel_bytes) { |
default: |
case 1: |
tile_height = 64; |
break; |
case 2: |
case 4: |
tile_height = 32; |
break; |
case 8: |
tile_height = 16; |
break; |
case 16: |
WARN_ONCE(1, |
"128-bit pixels are not supported for display!"); |
tile_height = 16; |
break; |
} |
break; |
default: |
MISSING_CASE(fb_format_modifier); |
tile_height = 1; |
break; |
} |
|
if (intel_crtc->primary_enabled) |
return; |
return tile_height; |
} |
|
intel_crtc->primary_enabled = true; |
|
dev_priv->display.update_primary_plane(crtc, plane->fb, |
crtc->x, crtc->y); |
|
/* |
* BDW signals flip done immediately if the plane |
* is disabled, even if the plane enable is already |
* armed to occur at the next vblank :( |
*/ |
if (IS_BROADWELL(dev)) |
intel_wait_for_vblank(dev, intel_crtc->pipe); |
unsigned int |
intel_fb_align_height(struct drm_device *dev, unsigned int height, |
uint32_t pixel_format, uint64_t fb_format_modifier) |
{ |
return ALIGN(height, intel_tile_height(dev, pixel_format, |
fb_format_modifier, 0)); |
} |
|
/** |
* intel_disable_primary_hw_plane - disable the primary hardware plane |
* @plane: plane to be disabled |
* @crtc: crtc for the plane |
* |
* Disable @plane on @crtc, making sure that the pipe is running first. |
*/ |
static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
struct drm_crtc *crtc) |
static int |
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
const struct drm_plane_state *plane_state) |
{ |
struct drm_device *dev = plane->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_rotation_info *info = &view->rotation_info; |
unsigned int tile_height, tile_pitch; |
|
assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
*view = i915_ggtt_view_normal; |
|
if (!intel_crtc->primary_enabled) |
return; |
if (!plane_state) |
return 0; |
|
intel_crtc->primary_enabled = false; |
if (!intel_rotation_90_or_270(plane_state->rotation)) |
return 0; |
|
dev_priv->display.update_primary_plane(crtc, plane->fb, |
crtc->x, crtc->y); |
*view = i915_ggtt_view_rotated; |
|
info->height = fb->height; |
info->pixel_format = fb->pixel_format; |
info->pitch = fb->pitches[0]; |
info->uv_offset = fb->offsets[1]; |
info->fb_modifier = fb->modifier[0]; |
|
tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fb->modifier[0], 0); |
tile_pitch = PAGE_SIZE / tile_height; |
info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
info->size = info->width_pages * info->height_pages * PAGE_SIZE; |
|
if (info->pixel_format == DRM_FORMAT_NV12) { |
tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fb->modifier[0], 1); |
tile_pitch = PAGE_SIZE / tile_height; |
info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
tile_height); |
info->size_uv = info->width_pages_uv * info->height_pages_uv * |
PAGE_SIZE; |
} |
|
static bool need_vtd_wa(struct drm_device *dev) |
{ |
#ifdef CONFIG_INTEL_IOMMU |
if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
return true; |
#endif |
return false; |
return 0; |
} |
|
static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
{ |
int tile_height; |
|
tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
return ALIGN(height, tile_height); |
if (INTEL_INFO(dev_priv)->gen >= 9) |
return 256 * 1024; |
else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
IS_VALLEYVIEW(dev_priv)) |
return 128 * 1024; |
else if (INTEL_INFO(dev_priv)->gen >= 4) |
return 4 * 1024; |
else |
return 0; |
} |
|
int |
intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
struct drm_framebuffer *fb, |
struct intel_engine_cs *pipelined) |
const struct drm_plane_state *plane_state, |
struct intel_engine_cs *pipelined, |
struct drm_i915_gem_request **pipelined_request) |
{ |
struct drm_device *dev = fb->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct i915_ggtt_view view; |
u32 alignment; |
int ret; |
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
switch (obj->tiling_mode) { |
case I915_TILING_NONE: |
if (INTEL_INFO(dev)->gen >= 9) |
alignment = 256 * 1024; |
else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
alignment = 128 * 1024; |
else if (INTEL_INFO(dev)->gen >= 4) |
alignment = 4 * 1024; |
else |
alignment = 64 * 1024; |
switch (fb->modifier[0]) { |
case DRM_FORMAT_MOD_NONE: |
alignment = intel_linear_alignment(dev_priv); |
break; |
case I915_TILING_X: |
case I915_FORMAT_MOD_X_TILED: |
if (INTEL_INFO(dev)->gen >= 9) |
alignment = 256 * 1024; |
else { |
2225,13 → 2355,22 |
alignment = 0; |
} |
break; |
case I915_TILING_Y: |
WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
case I915_FORMAT_MOD_Y_TILED: |
case I915_FORMAT_MOD_Yf_TILED: |
if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, |
"Y tiling bo slipped through, driver bug!\n")) |
return -EINVAL; |
alignment = 1 * 1024 * 1024; |
break; |
default: |
BUG(); |
MISSING_CASE(fb->modifier[0]); |
return -EINVAL; |
} |
|
ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
if (ret) |
return ret; |
|
/* Note that the w/a also requires 64 PTE of padding following the |
* bo. We currently fill all unused PTE with the shadow page and so |
* we should always have valid PTE following the scanout preventing |
2250,7 → 2389,8 |
intel_runtime_pm_get(dev_priv); |
|
dev_priv->mm.interruptible = false; |
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
pipelined_request, &view); |
if (ret) |
goto err_interruptible; |
|
2259,11 → 2399,24 |
* framebuffer compression. For simplicity, we always install |
* a fence as the cost is not that onerous. |
*/ |
if (view.type == I915_GGTT_VIEW_NORMAL) { |
ret = i915_gem_object_get_fence(obj); |
if (ret) |
if (ret == -EDEADLK) { |
/* |
* -EDEADLK means there are no free fences |
* no pending flips. |
* |
* This is propagated to atomic, but it uses |
* -EDEADLK to force a locking recovery, so |
* change the returned error to -EBUSY. |
*/ |
ret = -EBUSY; |
goto err_unpin; |
} else if (ret) |
goto err_unpin; |
|
i915_gem_object_pin_fence(obj); |
} |
|
dev_priv->mm.interruptible = true; |
intel_runtime_pm_put(dev_priv); |
2270,7 → 2423,7 |
return 0; |
|
err_unpin: |
i915_gem_object_unpin_from_display_plane(obj); |
i915_gem_object_unpin_from_display_plane(obj, &view); |
err_interruptible: |
dev_priv->mm.interruptible = true; |
intel_runtime_pm_put(dev_priv); |
2277,17 → 2430,28 |
return ret; |
} |
|
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
const struct drm_plane_state *plane_state) |
{ |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct i915_ggtt_view view; |
int ret; |
|
WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
|
ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
WARN_ONCE(ret, "Couldn't get view from plane state!"); |
|
if (view.type == I915_GGTT_VIEW_NORMAL) |
i915_gem_object_unpin_fence(obj); |
// i915_gem_object_unpin_from_display_plane(obj); |
|
i915_gem_object_unpin_from_display_plane(obj, &view); |
} |
|
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
* is assumed to be a power-of-two. */ |
unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
int *x, int *y, |
unsigned int tiling_mode, |
unsigned int cpp, |
unsigned int pitch) |
2303,16 → 2467,17 |
|
return tile_rows * pitch * 8 + tiles * 4096; |
} else { |
unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
unsigned int offset; |
|
offset = *y * pitch + *x * cpp; |
*y = 0; |
*x = (offset & 4095) / cpp; |
return offset & -4096; |
*y = (offset & alignment) / pitch; |
*x = ((offset & alignment) - *y * pitch) / cpp; |
return offset & ~alignment; |
} |
} |
|
int intel_format_to_fourcc(int format) |
static int i9xx_format_to_fourcc(int format) |
{ |
switch (format) { |
case DISPPLANE_8BPP: |
2333,47 → 2498,83 |
} |
} |
|
static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
struct intel_plane_config *plane_config) |
static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
{ |
switch (format) { |
case PLANE_CTL_FORMAT_RGB_565: |
return DRM_FORMAT_RGB565; |
default: |
case PLANE_CTL_FORMAT_XRGB_8888: |
if (rgb_order) { |
if (alpha) |
return DRM_FORMAT_ABGR8888; |
else |
return DRM_FORMAT_XBGR8888; |
} else { |
if (alpha) |
return DRM_FORMAT_ARGB8888; |
else |
return DRM_FORMAT_XRGB8888; |
} |
case PLANE_CTL_FORMAT_XRGB_2101010: |
if (rgb_order) |
return DRM_FORMAT_XBGR2101010; |
else |
return DRM_FORMAT_XRGB2101010; |
} |
} |
|
static bool |
intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
struct intel_initial_plane_config *plane_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = to_i915(dev); |
struct drm_i915_gem_object *obj = NULL; |
struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
u32 base = plane_config->base; |
struct drm_framebuffer *fb = &plane_config->fb->base; |
u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
u32 size_aligned = round_up(plane_config->base + plane_config->size, |
PAGE_SIZE); |
|
size_aligned -= base_aligned; |
|
if (plane_config->size == 0) |
return false; |
|
obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
plane_config->size); |
/* If the FB is too big, just don't use it since fbdev is not very |
* important and we should probably use that space with FBC or other |
* features. */ |
if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) |
return false; |
|
obj = i915_gem_object_create_stolen_for_preallocated(dev, |
base_aligned, |
base_aligned, |
size_aligned); |
if (!obj) |
return false; |
|
obj->map_and_fenceable=true; |
main_fb_obj = obj; |
obj->tiling_mode = plane_config->tiling; |
if (obj->tiling_mode == I915_TILING_X) |
obj->stride = fb->pitches[0]; |
|
if (plane_config->tiled) { |
obj->tiling_mode = I915_TILING_X; |
obj->stride = crtc->base.primary->fb->pitches[0]; |
} |
mode_cmd.pixel_format = fb->pixel_format; |
mode_cmd.width = fb->width; |
mode_cmd.height = fb->height; |
mode_cmd.pitches[0] = fb->pitches[0]; |
mode_cmd.modifier[0] = fb->modifier[0]; |
mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
|
mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
mode_cmd.width = crtc->base.primary->fb->width; |
mode_cmd.height = crtc->base.primary->fb->height; |
mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; |
|
mutex_lock(&dev->struct_mutex); |
|
if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
&mode_cmd, obj)) { |
DRM_DEBUG_KMS("intel fb init failed\n"); |
goto out_unref_obj; |
} |
|
obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
mutex_unlock(&dev->struct_mutex); |
|
DRM_DEBUG_KMS("plane fb obj %p\n", obj); |
DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
return true; |
|
out_unref_obj: |
2382,23 → 2583,44 |
return false; |
} |
|
static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
struct intel_plane_config *plane_config) |
/* Update plane->state->fb to match plane->fb after driver-internal updates */ |
static void |
update_state_fb(struct drm_plane *plane) |
{ |
if (plane->fb == plane->state->fb) |
return; |
|
if (plane->state->fb) |
drm_framebuffer_unreference(plane->state->fb); |
plane->state->fb = plane->fb; |
if (plane->state->fb) |
drm_framebuffer_reference(plane->state->fb); |
} |
|
static void |
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
struct intel_initial_plane_config *plane_config) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *c; |
struct intel_crtc *i; |
struct drm_i915_gem_object *obj; |
struct drm_plane *primary = intel_crtc->base.primary; |
struct drm_plane_state *plane_state = primary->state; |
struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
struct intel_plane *intel_plane = to_intel_plane(primary); |
struct drm_framebuffer *fb; |
|
if (!intel_crtc->base.primary->fb) |
if (!plane_config->fb) |
return; |
|
if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
return; |
if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
fb = &plane_config->fb->base; |
goto valid_fb; |
} |
|
kfree(intel_crtc->base.primary->fb); |
intel_crtc->base.primary->fb = NULL; |
kfree(plane_config->fb); |
|
/* |
* Failed to alloc the obj, check to see if we should share |
2413,21 → 2635,52 |
if (!i->active) |
continue; |
|
obj = intel_fb_obj(c->primary->fb); |
if (obj == NULL) |
fb = c->primary->fb; |
if (!fb) |
continue; |
|
obj = intel_fb_obj(fb); |
if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
drm_framebuffer_reference(fb); |
goto valid_fb; |
} |
} |
|
/* |
* We've failed to reconstruct the BIOS FB. Current display state |
* indicates that the primary plane is visible, but has a NULL FB, |
* which will lead to problems later if we don't fix it up. The |
* simplest solution is to just disable the primary plane now and |
* pretend the BIOS never had it enabled. |
*/ |
to_intel_plane_state(plane_state)->visible = false; |
crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
intel_pre_disable_primary(&intel_crtc->base); |
intel_plane->disable_plane(primary, &intel_crtc->base); |
|
return; |
|
valid_fb: |
plane_state->src_x = 0; |
plane_state->src_y = 0; |
plane_state->src_w = fb->width << 16; |
plane_state->src_h = fb->height << 16; |
|
plane_state->crtc_x = 0; |
plane_state->crtc_y = 0; |
plane_state->crtc_w = fb->width; |
plane_state->crtc_h = fb->height; |
|
obj = intel_fb_obj(fb); |
if (obj->tiling_mode != I915_TILING_NONE) |
dev_priv->preserve_bios_swizzle = true; |
|
drm_framebuffer_reference(c->primary->fb); |
intel_crtc->base.primary->fb = c->primary->fb; |
obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
break; |
drm_framebuffer_reference(fb); |
primary->fb = primary->state->fb = fb; |
primary->crtc = primary->state->crtc = &intel_crtc->base; |
intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
} |
} |
} |
|
static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
2436,6 → 2689,8 |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_plane *primary = crtc->primary; |
bool visible = to_intel_plane_state(primary->state)->visible; |
struct drm_i915_gem_object *obj; |
int plane = intel_crtc->plane; |
unsigned long linear_offset; |
2443,7 → 2698,7 |
u32 reg = DSPCNTR(plane); |
int pixel_size; |
|
if (!intel_crtc->primary_enabled) { |
if (!visible || !fb) { |
I915_WRITE(reg, 0); |
if (INTEL_INFO(dev)->gen >= 4) |
I915_WRITE(DSPSURF(plane), 0); |
2471,13 → 2726,13 |
* which should always be the user's requested size. |
*/ |
I915_WRITE(DSPSIZE(plane), |
((intel_crtc->config.pipe_src_h - 1) << 16) | |
(intel_crtc->config.pipe_src_w - 1)); |
((intel_crtc->config->pipe_src_h - 1) << 16) | |
(intel_crtc->config->pipe_src_w - 1)); |
I915_WRITE(DSPPOS(plane), 0); |
} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
I915_WRITE(PRIMSIZE(plane), |
((intel_crtc->config.pipe_src_h - 1) << 16) | |
(intel_crtc->config.pipe_src_w - 1)); |
((intel_crtc->config->pipe_src_h - 1) << 16) | |
(intel_crtc->config->pipe_src_w - 1)); |
I915_WRITE(PRIMPOS(plane), 0); |
I915_WRITE(PRIMCNSTALPHA(plane), 0); |
} |
2487,7 → 2742,6 |
dspcntr |= DISPPLANE_8BPP; |
break; |
case DRM_FORMAT_XRGB1555: |
case DRM_FORMAT_ARGB1555: |
dspcntr |= DISPPLANE_BGRX555; |
break; |
case DRM_FORMAT_RGB565: |
2494,19 → 2748,15 |
dspcntr |= DISPPLANE_BGRX565; |
break; |
case DRM_FORMAT_XRGB8888: |
case DRM_FORMAT_ARGB8888: |
dspcntr |= DISPPLANE_BGRX888; |
break; |
case DRM_FORMAT_XBGR8888: |
case DRM_FORMAT_ABGR8888: |
dspcntr |= DISPPLANE_RGBX888; |
break; |
case DRM_FORMAT_XRGB2101010: |
case DRM_FORMAT_ARGB2101010: |
dspcntr |= DISPPLANE_BGRX101010; |
break; |
case DRM_FORMAT_XBGR2101010: |
case DRM_FORMAT_ABGR2101010: |
dspcntr |= DISPPLANE_RGBX101010; |
break; |
default: |
2524,7 → 2774,8 |
|
if (INTEL_INFO(dev)->gen >= 4) { |
intel_crtc->dspaddr_offset = |
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
intel_gen4_compute_page_offset(dev_priv, |
&x, &y, obj->tiling_mode, |
pixel_size, |
fb->pitches[0]); |
linear_offset -= intel_crtc->dspaddr_offset; |
2532,24 → 2783,24 |
intel_crtc->dspaddr_offset = linear_offset; |
} |
|
if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
dspcntr |= DISPPLANE_ROTATE_180; |
|
x += (intel_crtc->config.pipe_src_w - 1); |
y += (intel_crtc->config.pipe_src_h - 1); |
x += (intel_crtc->config->pipe_src_w - 1); |
y += (intel_crtc->config->pipe_src_h - 1); |
|
/* Finding the last pixel of the last line of the display |
data and adding to linear_offset*/ |
linear_offset += |
(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + |
(intel_crtc->config.pipe_src_w - 1) * pixel_size; |
(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
(intel_crtc->config->pipe_src_w - 1) * pixel_size; |
} |
|
intel_crtc->adjusted_x = x; |
intel_crtc->adjusted_y = y; |
|
I915_WRITE(reg, dspcntr); |
|
DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
fb->pitches[0]); |
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
if (INTEL_INFO(dev)->gen >= 4) { |
I915_WRITE(DSPSURF(plane), |
2568,6 → 2819,8 |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_plane *primary = crtc->primary; |
bool visible = to_intel_plane_state(primary->state)->visible; |
struct drm_i915_gem_object *obj; |
int plane = intel_crtc->plane; |
unsigned long linear_offset; |
2575,7 → 2828,7 |
u32 reg = DSPCNTR(plane); |
int pixel_size; |
|
if (!intel_crtc->primary_enabled) { |
if (!visible || !fb) { |
I915_WRITE(reg, 0); |
I915_WRITE(DSPSURF(plane), 0); |
POSTING_READ(reg); |
2603,19 → 2856,15 |
dspcntr |= DISPPLANE_BGRX565; |
break; |
case DRM_FORMAT_XRGB8888: |
case DRM_FORMAT_ARGB8888: |
dspcntr |= DISPPLANE_BGRX888; |
break; |
case DRM_FORMAT_XBGR8888: |
case DRM_FORMAT_ABGR8888: |
dspcntr |= DISPPLANE_RGBX888; |
break; |
case DRM_FORMAT_XRGB2101010: |
case DRM_FORMAT_ARGB2101010: |
dspcntr |= DISPPLANE_BGRX101010; |
break; |
case DRM_FORMAT_XBGR2101010: |
case DRM_FORMAT_ABGR2101010: |
dspcntr |= DISPPLANE_RGBX101010; |
break; |
default: |
2630,30 → 2879,31 |
|
linear_offset = y * fb->pitches[0] + x * pixel_size; |
intel_crtc->dspaddr_offset = |
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
intel_gen4_compute_page_offset(dev_priv, |
&x, &y, obj->tiling_mode, |
pixel_size, |
fb->pitches[0]); |
linear_offset -= intel_crtc->dspaddr_offset; |
if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
dspcntr |= DISPPLANE_ROTATE_180; |
|
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
x += (intel_crtc->config.pipe_src_w - 1); |
y += (intel_crtc->config.pipe_src_h - 1); |
x += (intel_crtc->config->pipe_src_w - 1); |
y += (intel_crtc->config->pipe_src_h - 1); |
|
/* Finding the last pixel of the last line of the display |
data and adding to linear_offset*/ |
linear_offset += |
(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + |
(intel_crtc->config.pipe_src_w - 1) * pixel_size; |
(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
(intel_crtc->config->pipe_src_w - 1) * pixel_size; |
} |
} |
|
intel_crtc->adjusted_x = x; |
intel_crtc->adjusted_y = y; |
|
I915_WRITE(reg, dspcntr); |
|
DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
fb->pitches[0]); |
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
I915_WRITE(DSPSURF(plane), |
i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
2666,6 → 2916,174 |
POSTING_READ(reg); |
} |
|
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
uint32_t pixel_format) |
{ |
u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; |
|
/* |
* The stride is either expressed as a multiple of 64 bytes |
* chunks for linear buffers or in number of tiles for tiled |
* buffers. |
*/ |
switch (fb_modifier) { |
case DRM_FORMAT_MOD_NONE: |
return 64; |
case I915_FORMAT_MOD_X_TILED: |
if (INTEL_INFO(dev)->gen == 2) |
return 128; |
return 512; |
case I915_FORMAT_MOD_Y_TILED: |
/* No need to check for old gens and Y tiling since this is |
* about the display engine and those will be blocked before |
* we get here. |
*/ |
return 128; |
case I915_FORMAT_MOD_Yf_TILED: |
if (bits_per_pixel == 8) |
return 64; |
else |
return 128; |
default: |
MISSING_CASE(fb_modifier); |
return 64; |
} |
} |
|
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
struct drm_i915_gem_object *obj, |
unsigned int plane) |
{ |
const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
struct i915_vma *vma; |
unsigned char *offset; |
|
if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) |
view = &i915_ggtt_view_rotated; |
|
vma = i915_gem_obj_to_ggtt_view(obj, view); |
if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
view->type)) |
return -1; |
|
offset = (unsigned char *)vma->node.start; |
|
if (plane == 1) { |
offset += vma->ggtt_view.rotation_info.uv_start_page * |
PAGE_SIZE; |
} |
|
return (unsigned long)offset; |
} |
|
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); |
I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); |
I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); |
} |
|
/* |
* This function detaches (aka. unbinds) unused scalers in hardware |
*/ |
static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
{ |
struct intel_crtc_scaler_state *scaler_state; |
int i; |
|
scaler_state = &intel_crtc->config->scaler_state; |
|
/* loop through and disable scalers that aren't in use */ |
for (i = 0; i < intel_crtc->num_scalers; i++) { |
if (!scaler_state->scalers[i].in_use) |
skl_detach_scaler(intel_crtc, i); |
} |
} |
|
u32 skl_plane_ctl_format(uint32_t pixel_format) |
{ |
switch (pixel_format) { |
case DRM_FORMAT_C8: |
return PLANE_CTL_FORMAT_INDEXED; |
case DRM_FORMAT_RGB565: |
return PLANE_CTL_FORMAT_RGB_565; |
case DRM_FORMAT_XBGR8888: |
return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
case DRM_FORMAT_XRGB8888: |
return PLANE_CTL_FORMAT_XRGB_8888; |
/* |
* XXX: For ARBG/ABGR formats we default to expecting scanout buffers |
* to be already pre-multiplied. We need to add a knob (or a different |
* DRM_FORMAT) for user-space to configure that. |
*/ |
case DRM_FORMAT_ABGR8888: |
return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
case DRM_FORMAT_ARGB8888: |
return PLANE_CTL_FORMAT_XRGB_8888 | |
PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
case DRM_FORMAT_XRGB2101010: |
return PLANE_CTL_FORMAT_XRGB_2101010; |
case DRM_FORMAT_XBGR2101010: |
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
case DRM_FORMAT_YUYV: |
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
case DRM_FORMAT_YVYU: |
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
case DRM_FORMAT_UYVY: |
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
case DRM_FORMAT_VYUY: |
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
default: |
MISSING_CASE(pixel_format); |
} |
|
return 0; |
} |
|
u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
{ |
switch (fb_modifier) { |
case DRM_FORMAT_MOD_NONE: |
break; |
case I915_FORMAT_MOD_X_TILED: |
return PLANE_CTL_TILED_X; |
case I915_FORMAT_MOD_Y_TILED: |
return PLANE_CTL_TILED_Y; |
case I915_FORMAT_MOD_Yf_TILED: |
return PLANE_CTL_TILED_YF; |
default: |
MISSING_CASE(fb_modifier); |
} |
|
return 0; |
} |
|
u32 skl_plane_ctl_rotation(unsigned int rotation) |
{ |
switch (rotation) { |
case BIT(DRM_ROTATE_0): |
break; |
/* |
* DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr |
* while i915 HW rotation is clockwise, thats why this swapping. |
*/ |
case BIT(DRM_ROTATE_90): |
return PLANE_CTL_ROTATE_270; |
case BIT(DRM_ROTATE_180): |
return PLANE_CTL_ROTATE_180; |
case BIT(DRM_ROTATE_270): |
return PLANE_CTL_ROTATE_90; |
default: |
MISSING_CASE(rotation); |
} |
|
return 0; |
} |
|
static void skylake_update_primary_plane(struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
int x, int y) |
2673,12 → 3091,24 |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_framebuffer *intel_fb; |
struct drm_plane *plane = crtc->primary; |
bool visible = to_intel_plane_state(plane->state)->visible; |
struct drm_i915_gem_object *obj; |
int pipe = intel_crtc->pipe; |
u32 plane_ctl, stride; |
u32 plane_ctl, stride_div, stride; |
u32 tile_height, plane_offset, plane_size; |
unsigned int rotation; |
int x_offset, y_offset; |
unsigned long surf_addr; |
struct intel_crtc_state *crtc_state = intel_crtc->config; |
struct intel_plane_state *plane_state; |
int src_x = 0, src_y = 0, src_w = 0, src_h = 0; |
int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; |
int scaler_id = -1; |
|
if (!intel_crtc->primary_enabled) { |
plane_state = to_intel_plane_state(plane->state); |
|
if (!visible || !fb) { |
I915_WRITE(PLANE_CTL(pipe, 0), 0); |
I915_WRITE(PLANE_SURF(pipe, 0), 0); |
POSTING_READ(PLANE_CTL(pipe, 0)); |
2689,66 → 3119,73 |
PLANE_CTL_PIPE_GAMMA_ENABLE | |
PLANE_CTL_PIPE_CSC_ENABLE; |
|
switch (fb->pixel_format) { |
case DRM_FORMAT_RGB565: |
plane_ctl |= PLANE_CTL_FORMAT_RGB_565; |
break; |
case DRM_FORMAT_XRGB8888: |
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; |
break; |
case DRM_FORMAT_XBGR8888: |
plane_ctl |= PLANE_CTL_ORDER_RGBX; |
plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; |
break; |
case DRM_FORMAT_XRGB2101010: |
plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; |
break; |
case DRM_FORMAT_XBGR2101010: |
plane_ctl |= PLANE_CTL_ORDER_RGBX; |
plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; |
break; |
default: |
BUG(); |
} |
plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
|
intel_fb = to_intel_framebuffer(fb); |
obj = intel_fb->obj; |
rotation = plane->state->rotation; |
plane_ctl |= skl_plane_ctl_rotation(rotation); |
|
/* |
* The stride is either expressed as a multiple of 64 bytes chunks for |
* linear buffers or in number of tiles for tiled buffers. |
*/ |
switch (obj->tiling_mode) { |
case I915_TILING_NONE: |
stride = fb->pitches[0] >> 6; |
break; |
case I915_TILING_X: |
plane_ctl |= PLANE_CTL_TILED_X; |
stride = fb->pitches[0] >> 9; |
break; |
default: |
BUG(); |
obj = intel_fb_obj(fb); |
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
fb->pixel_format); |
surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
|
WARN_ON(drm_rect_width(&plane_state->src) == 0); |
|
scaler_id = plane_state->scaler_id; |
src_x = plane_state->src.x1 >> 16; |
src_y = plane_state->src.y1 >> 16; |
src_w = drm_rect_width(&plane_state->src) >> 16; |
src_h = drm_rect_height(&plane_state->src) >> 16; |
dst_x = plane_state->dst.x1; |
dst_y = plane_state->dst.y1; |
dst_w = drm_rect_width(&plane_state->dst); |
dst_h = drm_rect_height(&plane_state->dst); |
|
WARN_ON(x != src_x || y != src_y); |
|
if (intel_rotation_90_or_270(rotation)) { |
/* stride = Surface height in tiles */ |
tile_height = intel_tile_height(dev, fb->pixel_format, |
fb->modifier[0], 0); |
stride = DIV_ROUND_UP(fb->height, tile_height); |
x_offset = stride * tile_height - y - src_h; |
y_offset = x; |
plane_size = (src_w - 1) << 16 | (src_h - 1); |
} else { |
stride = fb->pitches[0] / stride_div; |
x_offset = x; |
y_offset = y; |
plane_size = (src_h - 1) << 16 | (src_w - 1); |
} |
plane_offset = y_offset << 16 | x_offset; |
|
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) |
plane_ctl |= PLANE_CTL_ROTATE_180; |
intel_crtc->adjusted_x = x_offset; |
intel_crtc->adjusted_y = y_offset; |
|
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); |
I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
|
DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n", |
i915_gem_obj_ggtt_offset(obj), |
x, y, fb->width, fb->height, |
fb->pitches[0]); |
if (scaler_id >= 0) { |
uint32_t ps_ctrl = 0; |
|
WARN_ON(!dst_w || !dst_h); |
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | |
crtc_state->scaler_state.scalers[scaler_id].mode; |
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); |
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); |
I915_WRITE(PLANE_POS(pipe, 0), 0); |
I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); |
I915_WRITE(PLANE_SIZE(pipe, 0), |
(intel_crtc->config.pipe_src_h - 1) << 16 | |
(intel_crtc->config.pipe_src_w - 1)); |
I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); |
} else { |
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); |
} |
|
I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
|
POSTING_READ(PLANE_SURF(pipe, 0)); |
} |
|
2760,8 → 3197,8 |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (dev_priv->display.disable_fbc) |
dev_priv->display.disable_fbc(dev); |
if (dev_priv->fbc.disable_fbc) |
dev_priv->fbc.disable_fbc(dev_priv); |
|
dev_priv->display.update_primary_plane(crtc, fb, x, y); |
|
2784,32 → 3221,25 |
|
static void intel_update_primary_planes(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *crtc; |
|
for_each_crtc(dev, crtc) { |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_plane *plane = to_intel_plane(crtc->primary); |
struct intel_plane_state *plane_state; |
|
drm_modeset_lock(&crtc->mutex, NULL); |
/* |
* FIXME: Once we have proper support for primary planes (and |
* disabling them without disabling the entire crtc) allow again |
* a NULL crtc->primary->fb. |
*/ |
if (intel_crtc->active && crtc->primary->fb) |
dev_priv->display.update_primary_plane(crtc, |
crtc->primary->fb, |
crtc->x, |
crtc->y); |
drm_modeset_unlock(&crtc->mutex); |
drm_modeset_lock_crtc(crtc, &plane->base); |
|
plane_state = to_intel_plane_state(plane->base.state); |
|
if (plane_state->base.fb) |
plane->commit_plane(&plane->base, plane_state); |
|
drm_modeset_unlock_crtc(crtc); |
} |
} |
|
void intel_prepare_reset(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = to_i915(dev); |
struct intel_crtc *crtc; |
|
/* no reset support for gen2 */ |
if (IS_GEN2(dev)) |
return; |
2819,16 → 3249,12 |
return; |
|
drm_modeset_lock_all(dev); |
|
/* |
* Disabling the crtcs gracefully seems nicer. Also the |
* g33 docs say we should at least disable all the planes. |
*/ |
for_each_intel_crtc(dev, crtc) { |
if (crtc->active) |
dev_priv->display.crtc_disable(&crtc->base); |
intel_display_suspend(dev); |
} |
} |
|
void intel_finish_reset(struct drm_device *dev) |
{ |
2852,6 → 3278,9 |
* so update the base address of all primary |
* planes to the the last fb to make sure we're |
* showing the correct fb after a reset. |
* |
* FIXME: Atomic will make this obsolete since we won't schedule |
* CS-based flips (which might get lost in gpu resets) any more. |
*/ |
intel_update_primary_planes(dev); |
return; |
2871,7 → 3300,7 |
dev_priv->display.hpd_irq_setup(dev); |
spin_unlock_irq(&dev_priv->irq_lock); |
|
intel_modeset_setup_hw_state(dev, true); |
intel_display_resume(dev); |
|
intel_hpd_init(dev_priv); |
|
2878,11 → 3307,11 |
drm_modeset_unlock_all(dev); |
} |
|
static int |
static void |
intel_finish_fb(struct drm_framebuffer *old_fb) |
{ |
struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
bool was_interruptible = dev_priv->mm.interruptible; |
int ret; |
|
2889,16 → 3318,19 |
/* Big Hammer, we also need to ensure that any pending |
* MI_WAIT_FOR_EVENT inside a user batch buffer on the |
* current scanout is retired before unpinning the old |
* framebuffer. |
* framebuffer. Note that we rely on userspace rendering |
* into the buffer attached to the pipe they are waiting |
* on. If not, userspace generates a GPU hang with IPEHR |
* point to the MI_WAIT_FOR_EVENT. |
* |
* This should only fail upon a hung GPU, in which case we |
* can safely continue. |
*/ |
dev_priv->mm.interruptible = false; |
ret = i915_gem_object_finish_gpu(obj); |
ret = i915_gem_object_wait_rendering(obj, true); |
dev_priv->mm.interruptible = was_interruptible; |
|
return ret; |
WARN_ON(ret); |
} |
|
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2920,15 → 3352,24 |
} |
#endif |
|
static void intel_update_pipe_size(struct intel_crtc *crtc) |
static void intel_update_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_state *old_crtc_state) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
const struct drm_display_mode *adjusted_mode; |
struct intel_crtc_state *pipe_config = |
to_intel_crtc_state(crtc->base.state); |
|
if (!i915.fastboot) |
return; |
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
crtc->base.mode = crtc->base.state->mode; |
|
DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", |
old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, |
pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
|
if (HAS_DDI(dev)) |
intel_set_pipe_csc(&crtc->base); |
|
/* |
* Update pipe size and adjust fitter if needed: the reason for this is |
* that in compute_mode_changes we check the native mode (not the pfit |
2936,90 → 3377,26 |
* fastboot case, we'll flip, but if we don't update the pipesrc and |
* pfit state, we'll end up with a big fb scanned out into the wrong |
* sized surface. |
* |
* To fix this properly, we need to hoist the checks up into |
* compute_mode_changes (or above), check the actual pfit state and |
* whether the platform allows pfit disable with pipe active, and only |
* then update the pipesrc and pfit state, even on the flip path. |
*/ |
|
adjusted_mode = &crtc->config.adjusted_mode; |
|
I915_WRITE(PIPESRC(crtc->pipe), |
((adjusted_mode->crtc_hdisplay - 1) << 16) | |
(adjusted_mode->crtc_vdisplay - 1)); |
if (!crtc->config.pch_pfit.enabled && |
(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
I915_WRITE(PF_CTL(crtc->pipe), 0); |
I915_WRITE(PF_WIN_POS(crtc->pipe), 0); |
I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); |
} |
crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
} |
((pipe_config->pipe_src_w - 1) << 16) | |
(pipe_config->pipe_src_h - 1)); |
|
static int |
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
struct drm_framebuffer *fb) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
struct drm_framebuffer *old_fb = crtc->primary->fb; |
struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
int ret; |
/* on skylake this is done by detaching scalers */ |
if (INTEL_INFO(dev)->gen >= 9) { |
skl_detach_scalers(crtc); |
|
|
/* no fb bound */ |
if (!fb) { |
DRM_ERROR("No FB bound\n"); |
return 0; |
if (pipe_config->pch_pfit.enabled) |
skylake_pfit_enable(crtc); |
} else if (HAS_PCH_SPLIT(dev)) { |
if (pipe_config->pch_pfit.enabled) |
ironlake_pfit_enable(crtc); |
else if (old_crtc_state->pch_pfit.enabled) |
ironlake_pfit_disable(crtc, true); |
} |
|
if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
plane_name(intel_crtc->plane), |
INTEL_INFO(dev)->num_pipes); |
return -EINVAL; |
} |
|
mutex_lock(&dev->struct_mutex); |
ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL); |
if (ret == 0) |
i915_gem_track_fb(old_obj, intel_fb_obj(fb), |
INTEL_FRONTBUFFER_PRIMARY(pipe)); |
mutex_unlock(&dev->struct_mutex); |
if (ret != 0) { |
DRM_ERROR("pin & fence failed\n"); |
return ret; |
} |
|
dev_priv->display.update_primary_plane(crtc, fb, x, y); |
|
if (intel_crtc->active) |
intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
crtc->primary->fb = fb; |
crtc->x = x; |
crtc->y = y; |
|
if (old_fb) { |
if (intel_crtc->active && old_fb != fb) |
intel_wait_for_vblank(dev, intel_crtc->pipe); |
mutex_lock(&dev->struct_mutex); |
intel_unpin_fb_obj(old_obj); |
mutex_unlock(&dev->struct_mutex); |
} |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
|
return 0; |
} |
|
static void intel_fdi_normal_train(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
3061,38 → 3438,6 |
FDI_FE_ERRC_ENABLE); |
} |
|
static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
{ |
return crtc->base.enabled && crtc->active && |
crtc->config.has_pch_encoder; |
} |
|
static void ivb_modeset_global_resources(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *pipe_B_crtc = |
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
struct intel_crtc *pipe_C_crtc = |
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
uint32_t temp; |
|
/* |
* When everything is off disable fdi C so that we could enable fdi B |
* with all lanes. Note that we don't care about enabled pipes without |
* an enabled pch encoder. |
*/ |
if (!pipe_has_enabled_pch(pipe_B_crtc) && |
!pipe_has_enabled_pch(pipe_C_crtc)) { |
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
|
temp = I915_READ(SOUTH_CHICKEN1); |
temp &= ~FDI_BC_BIFURCATION_SELECT; |
DRM_DEBUG_KMS("disabling fdi C rx\n"); |
I915_WRITE(SOUTH_CHICKEN1, temp); |
} |
} |
|
/* The FDI link training functions for ILK/Ibexpeak. */ |
static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
{ |
3119,7 → 3464,7 |
reg = FDI_TX_CTL(pipe); |
temp = I915_READ(reg); |
temp &= ~FDI_DP_PORT_WIDTH_MASK; |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
temp &= ~FDI_LINK_TRAIN_NONE; |
temp |= FDI_LINK_TRAIN_PATTERN_1; |
I915_WRITE(reg, temp | FDI_TX_ENABLE); |
3217,7 → 3562,7 |
reg = FDI_TX_CTL(pipe); |
temp = I915_READ(reg); |
temp &= ~FDI_DP_PORT_WIDTH_MASK; |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
temp &= ~FDI_LINK_TRAIN_NONE; |
temp |= FDI_LINK_TRAIN_PATTERN_1; |
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3368,7 → 3713,7 |
reg = FDI_TX_CTL(pipe); |
temp = I915_READ(reg); |
temp &= ~FDI_DP_PORT_WIDTH_MASK; |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
temp |= snb_b_fdi_train_param[j/2]; |
3456,7 → 3801,7 |
reg = FDI_RX_CTL(pipe); |
temp = I915_READ(reg); |
temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
|
3619,11 → 3964,11 |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
u32 divsel, phaseinc, auxdiv, phasedir = 0; |
u32 temp; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
/* It is necessary to ungate the pixclk gate prior to programming |
* the divisors, and gate it back when it is done. |
3700,7 → 4045,7 |
|
I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
|
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3708,7 → 4053,7 |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
|
I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
I915_READ(HTOTAL(cpu_transcoder))); |
3727,20 → 4072,23 |
I915_READ(VSYNCSHIFT(cpu_transcoder))); |
} |
|
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t temp; |
|
temp = I915_READ(SOUTH_CHICKEN1); |
if (temp & FDI_BC_BIFURCATION_SELECT) |
if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
return; |
|
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
|
temp &= ~FDI_BC_BIFURCATION_SELECT; |
if (enable) |
temp |= FDI_BC_BIFURCATION_SELECT; |
DRM_DEBUG_KMS("enabling fdi C rx\n"); |
|
DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); |
I915_WRITE(SOUTH_CHICKEN1, temp); |
POSTING_READ(SOUTH_CHICKEN1); |
} |
3748,20 → 4096,19 |
static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
switch (intel_crtc->pipe) { |
case PIPE_A: |
break; |
case PIPE_B: |
if (intel_crtc->config.fdi_lanes > 2) |
WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
if (intel_crtc->config->fdi_lanes > 2) |
cpt_set_fdi_bc_bifurcation(dev, false); |
else |
cpt_enable_fdi_bc_bifurcation(dev); |
cpt_set_fdi_bc_bifurcation(dev, true); |
|
break; |
case PIPE_C: |
cpt_enable_fdi_bc_bifurcation(dev); |
cpt_set_fdi_bc_bifurcation(dev, true); |
|
break; |
default: |
3806,7 → 4153,7 |
temp = I915_READ(PCH_DPLL_SEL); |
temp |= TRANS_DPLL_ENABLE(pipe); |
sel = TRANS_DPLLB_SEL(pipe); |
if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
temp |= sel; |
else |
temp &= ~sel; |
3829,7 → 4176,7 |
intel_fdi_normal_train(crtc); |
|
/* For PCH DP, enable TRANS_DP_CTL */ |
if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { |
if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
reg = TRANS_DP_CTL(pipe); |
temp = I915_READ(reg); |
3836,8 → 4183,7 |
temp &= ~(TRANS_DP_PORT_SEL_MASK | |
TRANS_DP_SYNC_MASK | |
TRANS_DP_BPC_MASK); |
temp |= (TRANS_DP_OUTPUT_ENABLE | |
TRANS_DP_ENH_FRAMING); |
temp |= TRANS_DP_OUTPUT_ENABLE; |
temp |= bpc << 9; /* same format but at 11:9 */ |
|
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
3870,7 → 4216,7 |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
|
assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
|
3882,33 → 4228,17 |
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
} |
|
void intel_put_shared_dpll(struct intel_crtc *crtc) |
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state) |
{ |
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
|
if (pll == NULL) |
return; |
|
if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
WARN(1, "bad %s crtc mask\n", pll->name); |
return; |
} |
|
pll->config.crtc_mask &= ~(1 << crtc->pipe); |
if (pll->config.crtc_mask == 0) { |
WARN_ON(pll->on); |
WARN_ON(pll->active); |
} |
|
crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
} |
|
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct intel_shared_dpll *pll; |
struct intel_shared_dpll_config *shared_dpll; |
enum intel_dpll_id i; |
int max = dev_priv->num_shared_dpll; |
|
shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
|
if (HAS_PCH_IBX(dev_priv->dev)) { |
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
i = (enum intel_dpll_id) crtc->pipe; |
3917,24 → 4247,46 |
DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
crtc->base.base.id, pll->name); |
|
WARN_ON(pll->new_config->crtc_mask); |
WARN_ON(shared_dpll[i].crtc_mask); |
|
goto found; |
} |
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
if (IS_BROXTON(dev_priv->dev)) { |
/* PLL is attached to port in bxt */ |
struct intel_encoder *encoder; |
struct intel_digital_port *intel_dig_port; |
|
encoder = intel_ddi_get_crtc_new_encoder(crtc_state); |
if (WARN_ON(!encoder)) |
return NULL; |
|
intel_dig_port = enc_to_dig_port(&encoder->base); |
/* 1:1 mapping between ports and PLLs */ |
i = (enum intel_dpll_id)intel_dig_port->port; |
pll = &dev_priv->shared_dplls[i]; |
DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
crtc->base.base.id, pll->name); |
WARN_ON(shared_dpll[i].crtc_mask); |
|
goto found; |
} else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
/* Do not consider SPLL */ |
max = 2; |
|
for (i = 0; i < max; i++) { |
pll = &dev_priv->shared_dplls[i]; |
|
/* Only want to check enabled timings first */ |
if (pll->new_config->crtc_mask == 0) |
if (shared_dpll[i].crtc_mask == 0) |
continue; |
|
if (memcmp(&crtc->new_config->dpll_hw_state, |
&pll->new_config->hw_state, |
sizeof(pll->new_config->hw_state)) == 0) { |
if (memcmp(&crtc_state->dpll_hw_state, |
&shared_dpll[i].hw_state, |
sizeof(crtc_state->dpll_hw_state)) == 0) { |
DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
crtc->base.base.id, pll->name, |
pll->new_config->crtc_mask, |
shared_dpll[i].crtc_mask, |
pll->active); |
goto found; |
} |
3943,7 → 4295,7 |
/* Ok no matching timings, maybe there's a free one? */ |
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
pll = &dev_priv->shared_dplls[i]; |
if (pll->new_config->crtc_mask == 0) { |
if (shared_dpll[i].crtc_mask == 0) { |
DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
crtc->base.base.id, pll->name); |
goto found; |
3953,99 → 4305,209 |
return NULL; |
|
found: |
if (pll->new_config->crtc_mask == 0) |
pll->new_config->hw_state = crtc->new_config->dpll_hw_state; |
if (shared_dpll[i].crtc_mask == 0) |
shared_dpll[i].hw_state = |
crtc_state->dpll_hw_state; |
|
crtc->new_config->shared_dpll = i; |
crtc_state->shared_dpll = i; |
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
pipe_name(crtc->pipe)); |
|
pll->new_config->crtc_mask |= 1 << crtc->pipe; |
shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
|
return pll; |
} |
|
/** |
* intel_shared_dpll_start_config - start a new PLL staged config |
* @dev_priv: DRM device |
* @clear_pipes: mask of pipes that will have their PLLs freed |
* |
* Starts a new PLL staged config, copying the current config but |
* releasing the references of pipes specified in clear_pipes. |
*/ |
static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, |
unsigned clear_pipes) |
static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
{ |
struct drm_i915_private *dev_priv = to_i915(state->dev); |
struct intel_shared_dpll_config *shared_dpll; |
struct intel_shared_dpll *pll; |
enum intel_dpll_id i; |
|
if (!to_intel_atomic_state(state)->dpll_set) |
return; |
|
shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
pll = &dev_priv->shared_dplls[i]; |
pll->config = shared_dpll[i]; |
} |
} |
|
pll->new_config = kmemdup(&pll->config, sizeof pll->config, |
GFP_KERNEL); |
if (!pll->new_config) |
goto cleanup; |
static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
int dslreg = PIPEDSL(pipe); |
u32 temp; |
|
pll->new_config->crtc_mask &= ~clear_pipes; |
temp = I915_READ(dslreg); |
udelay(500); |
if (wait_for(I915_READ(dslreg) != temp, 5)) { |
if (wait_for(I915_READ(dslreg) != temp, 5)) |
DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
} |
} |
|
static int |
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, |
unsigned scaler_user, int *scaler_id, unsigned int rotation, |
int src_w, int src_h, int dst_w, int dst_h) |
{ |
struct intel_crtc_scaler_state *scaler_state = |
&crtc_state->scaler_state; |
struct intel_crtc *intel_crtc = |
to_intel_crtc(crtc_state->base.crtc); |
int need_scaling; |
|
need_scaling = intel_rotation_90_or_270(rotation) ? |
(src_h != dst_w || src_w != dst_h): |
(src_w != dst_w || src_h != dst_h); |
|
/* |
* if plane is being disabled or scaler is no more required or force detach |
* - free scaler binded to this plane/crtc |
* - in order to do this, update crtc->scaler_usage |
* |
* Here scaler state in crtc_state is set free so that |
* scaler can be assigned to other user. Actual register |
* update to free the scaler is done in plane/panel-fit programming. |
* For this purpose crtc/plane_state->scaler_id isn't reset here. |
*/ |
if (force_detach || !need_scaling) { |
if (*scaler_id >= 0) { |
scaler_state->scaler_users &= ~(1 << scaler_user); |
scaler_state->scalers[*scaler_id].in_use = 0; |
|
DRM_DEBUG_KMS("scaler_user index %u.%u: " |
"Staged freeing scaler id %d scaler_users = 0x%x\n", |
intel_crtc->pipe, scaler_user, *scaler_id, |
scaler_state->scaler_users); |
*scaler_id = -1; |
} |
return 0; |
} |
|
cleanup: |
while (--i >= 0) { |
pll = &dev_priv->shared_dplls[i]; |
kfree(pll->new_config); |
pll->new_config = NULL; |
/* range checks */ |
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || |
dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || |
|
src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || |
dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { |
DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
"size is out of scaler range\n", |
intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
return -EINVAL; |
} |
|
return -ENOMEM; |
/* mark this plane as a scaler user in crtc_state */ |
scaler_state->scaler_users |= (1 << scaler_user); |
DRM_DEBUG_KMS("scaler_user index %u.%u: " |
"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", |
intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, |
scaler_state->scaler_users); |
|
return 0; |
} |
|
static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) |
/** |
* skl_update_scaler_crtc - Stages update to scaler state for a given crtc. |
* |
* @state: crtc's scaler state |
* |
* Return |
* 0 - scaler_usage updated successfully |
* error - requested scaling cannot be supported or other error condition |
*/ |
int skl_update_scaler_crtc(struct intel_crtc_state *state) |
{ |
struct intel_shared_dpll *pll; |
enum intel_dpll_id i; |
struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
pll = &dev_priv->shared_dplls[i]; |
DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", |
intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); |
|
WARN_ON(pll->new_config == &pll->config); |
|
pll->config = *pll->new_config; |
kfree(pll->new_config); |
pll->new_config = NULL; |
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
&state->scaler_state.scaler_id, DRM_ROTATE_0, |
state->pipe_src_w, state->pipe_src_h, |
adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
} |
} |
|
static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) |
/** |
* skl_update_scaler_plane - Stages update to scaler state for a given plane. |
* |
* @state: crtc's scaler state |
* @plane_state: atomic plane state to update |
* |
* Return |
* 0 - scaler_usage updated successfully |
* error - requested scaling cannot be supported or other error condition |
*/ |
static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
struct intel_plane_state *plane_state) |
{ |
struct intel_shared_dpll *pll; |
enum intel_dpll_id i; |
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
pll = &dev_priv->shared_dplls[i]; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
struct intel_plane *intel_plane = |
to_intel_plane(plane_state->base.plane); |
struct drm_framebuffer *fb = plane_state->base.fb; |
int ret; |
|
WARN_ON(pll->new_config == &pll->config); |
bool force_detach = !fb || !plane_state->visible; |
|
kfree(pll->new_config); |
pll->new_config = NULL; |
DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", |
intel_plane->base.base.id, intel_crtc->pipe, |
drm_plane_index(&intel_plane->base)); |
|
ret = skl_update_scaler(crtc_state, force_detach, |
drm_plane_index(&intel_plane->base), |
&plane_state->scaler_id, |
plane_state->base.rotation, |
drm_rect_width(&plane_state->src) >> 16, |
drm_rect_height(&plane_state->src) >> 16, |
drm_rect_width(&plane_state->dst), |
drm_rect_height(&plane_state->dst)); |
|
if (ret || plane_state->scaler_id < 0) |
return ret; |
|
/* check colorkey */ |
if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
intel_plane->base.base.id); |
return -EINVAL; |
} |
|
/* Check src format */ |
switch (fb->pixel_format) { |
case DRM_FORMAT_RGB565: |
case DRM_FORMAT_XBGR8888: |
case DRM_FORMAT_XRGB8888: |
case DRM_FORMAT_ABGR8888: |
case DRM_FORMAT_ARGB8888: |
case DRM_FORMAT_XRGB2101010: |
case DRM_FORMAT_XBGR2101010: |
case DRM_FORMAT_YUYV: |
case DRM_FORMAT_YVYU: |
case DRM_FORMAT_UYVY: |
case DRM_FORMAT_VYUY: |
break; |
default: |
DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", |
intel_plane->base.base.id, fb->base.id, fb->pixel_format); |
return -EINVAL; |
} |
|
static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
return 0; |
} |
|
static void skylake_scaler_disable(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
int dslreg = PIPEDSL(pipe); |
u32 temp; |
int i; |
|
temp = I915_READ(dslreg); |
udelay(500); |
if (wait_for(I915_READ(dslreg) != temp, 5)) { |
if (wait_for(I915_READ(dslreg) != temp, 5)) |
DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
for (i = 0; i < crtc->num_scalers; i++) |
skl_detach_scaler(crtc, i); |
} |
} |
|
static void skylake_pfit_enable(struct intel_crtc *crtc) |
{ |
4052,13 → 4514,28 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = crtc->pipe; |
struct intel_crtc_scaler_state *scaler_state = |
&crtc->config->scaler_state; |
|
if (crtc->config.pch_pfit.enabled) { |
I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); |
|
if (crtc->config->pch_pfit.enabled) { |
int id; |
|
if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { |
DRM_ERROR("Requesting pfit without getting a scaler first\n"); |
return; |
} |
|
id = scaler_state->scaler_id; |
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | |
PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); |
I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); |
I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); |
|
DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); |
} |
} |
|
static void ironlake_pfit_enable(struct intel_crtc *crtc) |
{ |
4066,7 → 4543,7 |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = crtc->pipe; |
|
if (crtc->config.pch_pfit.enabled) { |
if (crtc->config->pch_pfit.enabled) { |
/* Force use of hard-coded filter coefficients |
* as some pre-programmed values are broken, |
* e.g. x201. |
4076,45 → 4553,17 |
PF_PIPE_SEL_IVB(pipe)); |
else |
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); |
} |
} |
|
static void intel_enable_planes(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
enum pipe pipe = to_intel_crtc(crtc)->pipe; |
struct drm_plane *plane; |
struct intel_plane *intel_plane; |
|
drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
intel_plane = to_intel_plane(plane); |
if (intel_plane->pipe == pipe) |
intel_plane_restore(&intel_plane->base); |
} |
} |
|
static void intel_disable_planes(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
enum pipe pipe = to_intel_crtc(crtc)->pipe; |
struct drm_plane *plane; |
struct intel_plane *intel_plane; |
|
drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
intel_plane = to_intel_plane(plane); |
if (intel_plane->pipe == pipe) |
intel_plane_disable(&intel_plane->base); |
} |
} |
|
void hsw_enable_ips(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (!crtc->config.ips_enabled) |
if (!crtc->config->ips_enabled) |
return; |
|
/* We can only enable IPS after we enable a plane and wait for a vblank */ |
4147,7 → 4596,7 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (!crtc->config.ips_enabled) |
if (!crtc->config->ips_enabled) |
return; |
|
assert_plane_enabled(dev_priv, crtc->plane); |
4174,15 → 4623,14 |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
int palreg = PALETTE(pipe); |
int i; |
bool reenable_ips = false; |
|
/* The clocks have to be on to load the palette. */ |
if (!crtc->enabled || !intel_crtc->active) |
if (!crtc->state->active) |
return; |
|
if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
assert_dsi_pll_enabled(dev_priv); |
else |
4189,14 → 4637,10 |
assert_pll_enabled(dev_priv, pipe); |
} |
|
/* use legacy palette for Ironlake */ |
if (!HAS_GMCH_DISPLAY(dev)) |
palreg = LGC_PALETTE(pipe); |
|
/* Workaround : Do not read or write the pipe palette/gamma data while |
* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
*/ |
if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
GAMMA_MODE_MODE_SPLIT)) { |
hsw_disable_ips(intel_crtc); |
4204,7 → 4648,14 |
} |
|
for (i = 0; i < 256; i++) { |
I915_WRITE(palreg + 4 * i, |
u32 palreg; |
|
if (HAS_GMCH_DISPLAY(dev)) |
palreg = PALETTE(pipe, i); |
else |
palreg = LGC_PALETTE(pipe, i); |
|
I915_WRITE(palreg, |
(intel_crtc->lut_r[i] << 16) | |
(intel_crtc->lut_g[i] << 8) | |
intel_crtc->lut_b[i]); |
4214,9 → 4665,9 |
hsw_enable_ips(intel_crtc); |
} |
|
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
{ |
if (!enable && intel_crtc->overlay) { |
if (intel_crtc->overlay) { |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
4232,50 → 4683,181 |
*/ |
} |
|
static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
/** |
* intel_post_enable_primary - Perform operations after enabling primary plane |
* @crtc: the CRTC whose primary plane was just enabled |
* |
* Performs potentially sleeping operations that must be done after the primary |
* plane is enabled, such as updating FBC and IPS. Note that this may be |
* called due to an explicit primary plane update, or due to an implicit |
* re-enable that is caused when a sprite plane is updated to no longer |
* completely hide the primary plane. |
*/ |
static void |
intel_post_enable_primary(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int pipe = intel_crtc->pipe; |
|
intel_enable_primary_hw_plane(crtc->primary, crtc); |
intel_enable_planes(crtc); |
intel_crtc_update_cursor(crtc, true); |
intel_crtc_dpms_overlay(intel_crtc, true); |
/* |
* BDW signals flip done immediately if the plane |
* is disabled, even if the plane enable is already |
* armed to occur at the next vblank :( |
*/ |
if (IS_BROADWELL(dev)) |
intel_wait_for_vblank(dev, pipe); |
|
/* |
* FIXME IPS should be fine as long as one plane is |
* enabled, but in practice it seems to have problems |
* when going from primary only to sprite only and vice |
* versa. |
*/ |
hsw_enable_ips(intel_crtc); |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
|
/* |
* FIXME: Once we grow proper nuclear flip support out of this we need |
* to compute the mask of flip planes precisely. For the time being |
* consider this a flip from a NULL plane. |
* Gen2 reports pipe underruns whenever all planes are disabled. |
* So don't enable underrun reporting before at least some planes |
* are enabled. |
* FIXME: Need to fix the logic to work when we turn off all planes |
* but leave the pipe running. |
*/ |
intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
if (IS_GEN2(dev)) |
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
|
/* Underruns don't raise interrupts, so check manually. */ |
if (HAS_GMCH_DISPLAY(dev)) |
i9xx_check_fifo_underruns(dev_priv); |
} |
|
static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
/** |
* intel_pre_disable_primary - Perform operations before disabling primary plane |
* @crtc: the CRTC whose primary plane is to be disabled |
* |
* Performs potentially sleeping operations that must be done before the |
* primary plane is disabled, such as updating FBC and IPS. Note that this may |
* be called due to an explicit primary plane update, or due to an implicit |
* disable that is caused when a sprite plane completely hides the primary |
* plane. |
*/ |
static void |
intel_pre_disable_primary(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int pipe = intel_crtc->pipe; |
int plane = intel_crtc->plane; |
|
/* |
* Gen2 reports pipe underruns whenever all planes are disabled. |
* So diasble underrun reporting before all the planes get disabled. |
* FIXME: Need to fix the logic to work when we turn off all planes |
* but leave the pipe running. |
*/ |
if (IS_GEN2(dev)) |
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
if (dev_priv->fbc.plane == plane) |
intel_disable_fbc(dev); |
/* |
* Vblank time updates from the shadow to live plane control register |
* are blocked if the memory self-refresh mode is active at that |
* moment. So to make sure the plane gets truly disabled, disable |
* first the self-refresh mode. The self-refresh enable bit in turn |
* will be checked/applied by the HW only at the next frame start |
* event which is after the vblank start event, so we need to have a |
* wait-for-vblank between disabling the plane and the pipe. |
*/ |
if (HAS_GMCH_DISPLAY(dev)) { |
intel_set_memory_cxsr(dev_priv, false); |
dev_priv->wm.vlv.cxsr = false; |
intel_wait_for_vblank(dev, pipe); |
} |
|
/* |
* FIXME IPS should be fine as long as one plane is |
* enabled, but in practice it seems to have problems |
* when going from primary only to sprite only and vice |
* versa. |
*/ |
hsw_disable_ips(intel_crtc); |
} |
|
intel_crtc_dpms_overlay(intel_crtc, false); |
intel_crtc_update_cursor(crtc, false); |
intel_disable_planes(crtc); |
intel_disable_primary_hw_plane(crtc->primary, crtc); |
static void intel_post_plane_update(struct intel_crtc *crtc) |
{ |
struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_plane *plane; |
|
if (atomic->wait_vblank) |
intel_wait_for_vblank(dev, crtc->pipe); |
|
intel_frontbuffer_flip(dev, atomic->fb_bits); |
|
if (atomic->disable_cxsr) |
crtc->wm.cxsr_allowed = true; |
|
if (crtc->atomic.update_wm_post) |
intel_update_watermarks(&crtc->base); |
|
if (atomic->update_fbc) |
intel_fbc_update(dev_priv); |
|
if (atomic->post_enable_primary) |
intel_post_enable_primary(&crtc->base); |
|
drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) |
intel_update_sprite_watermarks(plane, &crtc->base, |
0, 0, 0, false, false); |
|
memset(atomic, 0, sizeof(*atomic)); |
} |
|
static void intel_pre_plane_update(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
struct drm_plane *p; |
|
/* Track fb's for any planes being disabled */ |
drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
struct intel_plane *plane = to_intel_plane(p); |
|
mutex_lock(&dev->struct_mutex); |
i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
plane->frontbuffer_bit); |
mutex_unlock(&dev->struct_mutex); |
} |
|
if (atomic->disable_fbc) |
intel_fbc_disable_crtc(crtc); |
|
if (crtc->atomic.disable_ips) |
hsw_disable_ips(crtc); |
|
if (atomic->pre_disable_primary) |
intel_pre_disable_primary(&crtc->base); |
|
if (atomic->disable_cxsr) { |
crtc->wm.cxsr_allowed = false; |
intel_set_memory_cxsr(dev_priv, false); |
} |
} |
|
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
{ |
struct drm_device *dev = crtc->dev; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_plane *p; |
int pipe = intel_crtc->pipe; |
|
intel_crtc_dpms_overlay_disable(intel_crtc); |
|
drm_for_each_plane_mask(p, dev, plane_mask) |
to_intel_plane(p)->disable_plane(p, crtc); |
|
/* |
* FIXME: Once we grow proper nuclear flip support out of this we need |
* to compute the mask of flip planes precisely. For the time being |
4292,22 → 4874,20 |
struct intel_encoder *encoder; |
int pipe = intel_crtc->pipe; |
|
WARN_ON(!crtc->enabled); |
|
if (intel_crtc->active) |
if (WARN_ON(intel_crtc->active)) |
return; |
|
if (intel_crtc->config.has_pch_encoder) |
if (intel_crtc->config->has_pch_encoder) |
intel_prepare_shared_dpll(intel_crtc); |
|
if (intel_crtc->config.has_dp_encoder) |
intel_dp_set_m_n(intel_crtc); |
if (intel_crtc->config->has_dp_encoder) |
intel_dp_set_m_n(intel_crtc, M1_N1); |
|
intel_set_pipe_timings(intel_crtc); |
|
if (intel_crtc->config.has_pch_encoder) { |
if (intel_crtc->config->has_pch_encoder) { |
intel_cpu_transcoder_set_m_n(intel_crtc, |
&intel_crtc->config.fdi_m_n, NULL); |
&intel_crtc->config->fdi_m_n, NULL); |
} |
|
ironlake_set_pipeconf(crtc); |
4321,7 → 4901,7 |
if (encoder->pre_enable) |
encoder->pre_enable(encoder); |
|
if (intel_crtc->config.has_pch_encoder) { |
if (intel_crtc->config->has_pch_encoder) { |
/* Note: FDI PLL enabling _must_ be done before we enable the |
* cpu pipes, hence this is separate from all the other fdi/pch |
* enabling. */ |
4342,19 → 4922,17 |
intel_update_watermarks(crtc); |
intel_enable_pipe(intel_crtc); |
|
if (intel_crtc->config.has_pch_encoder) |
if (intel_crtc->config->has_pch_encoder) |
ironlake_pch_enable(crtc); |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->enable(encoder); |
|
if (HAS_PCH_CPT(dev)) |
cpt_verify_modeset(dev, intel_crtc->pipe); |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
intel_crtc_enable_planes(crtc); |
} |
|
/* IPS only exists on ULT machines and is tied to pipe A. */ |
4363,35 → 4941,6 |
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
} |
|
/* |
* This implements the workaround described in the "notes" section of the mode |
* set sequence documentation. When going from no pipes or single pipe to |
* multiple pipes, and planes are enabled after the pipe, we need to wait at |
* least 2 vblanks on the first pipe before enabling planes on the second pipe. |
*/ |
static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
|
/* We want to get the other_active_crtc only if there's only 1 other |
* active crtc. */ |
for_each_intel_crtc(dev, crtc_it) { |
if (!crtc_it->active || crtc_it == crtc) |
continue; |
|
if (other_active_crtc) |
return; |
|
other_active_crtc = crtc_it; |
} |
if (!other_active_crtc) |
return; |
|
intel_wait_for_vblank(dev, other_active_crtc->pipe); |
intel_wait_for_vblank(dev, other_active_crtc->pipe); |
} |
|
static void haswell_crtc_enable(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
4398,29 → 4947,30 |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_encoder *encoder; |
int pipe = intel_crtc->pipe; |
int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
struct intel_crtc_state *pipe_config = |
to_intel_crtc_state(crtc->state); |
bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
|
WARN_ON(!crtc->enabled); |
|
if (intel_crtc->active) |
if (WARN_ON(intel_crtc->active)) |
return; |
|
if (intel_crtc_to_shared_dpll(intel_crtc)) |
intel_enable_shared_dpll(intel_crtc); |
|
if (intel_crtc->config.has_dp_encoder) |
intel_dp_set_m_n(intel_crtc); |
if (intel_crtc->config->has_dp_encoder) |
intel_dp_set_m_n(intel_crtc, M1_N1); |
|
intel_set_pipe_timings(intel_crtc); |
|
if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { |
I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), |
intel_crtc->config.pixel_multiplier - 1); |
if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), |
intel_crtc->config->pixel_multiplier - 1); |
} |
|
if (intel_crtc->config.has_pch_encoder) { |
if (intel_crtc->config->has_pch_encoder) { |
intel_cpu_transcoder_set_m_n(intel_crtc, |
&intel_crtc->config.fdi_m_n, NULL); |
&intel_crtc->config->fdi_m_n, NULL); |
} |
|
haswell_set_pipeconf(crtc); |
4430,19 → 4980,23 |
intel_crtc->active = true; |
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
for_each_encoder_on_crtc(dev, crtc, encoder) |
for_each_encoder_on_crtc(dev, crtc, encoder) { |
if (encoder->pre_pll_enable) |
encoder->pre_pll_enable(encoder); |
if (encoder->pre_enable) |
encoder->pre_enable(encoder); |
} |
|
if (intel_crtc->config.has_pch_encoder) { |
if (intel_crtc->config->has_pch_encoder) { |
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
true); |
dev_priv->display.fdi_link_train(crtc); |
} |
|
if (!is_dsi) |
intel_ddi_enable_pipe_clock(intel_crtc); |
|
if (IS_SKYLAKE(dev)) |
if (INTEL_INFO(dev)->gen >= 9) |
skylake_pfit_enable(intel_crtc); |
else |
ironlake_pfit_enable(intel_crtc); |
4454,47 → 5008,36 |
intel_crtc_load_lut(crtc); |
|
intel_ddi_set_pipe_settings(crtc); |
if (!is_dsi) |
intel_ddi_enable_transcoder_func(crtc); |
|
intel_update_watermarks(crtc); |
intel_enable_pipe(intel_crtc); |
|
if (intel_crtc->config.has_pch_encoder) |
if (intel_crtc->config->has_pch_encoder) |
lpt_pch_enable(crtc); |
|
if (intel_crtc->config.dp_encoder_is_mst) |
if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) |
intel_ddi_set_vc_payload_alloc(crtc, true); |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) { |
encoder->enable(encoder); |
intel_opregion_notify_encoder(encoder, true); |
} |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
/* If we change the relative order between pipe/planes enabling, we need |
* to change the workaround. */ |
haswell_mode_set_planes_workaround(intel_crtc); |
intel_crtc_enable_planes(crtc); |
hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
intel_wait_for_vblank(dev, hsw_workaround_pipe); |
intel_wait_for_vblank(dev, hsw_workaround_pipe); |
} |
|
static void skylake_pfit_disable(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = crtc->pipe; |
|
/* To avoid upsetting the power well on haswell only disable the pfit if |
* it's in use. The hw state code will make sure we get this right. */ |
if (crtc->config.pch_pfit.enabled) { |
I915_WRITE(PS_CTL(pipe), 0); |
I915_WRITE(PS_WIN_POS(pipe), 0); |
I915_WRITE(PS_WIN_SZ(pipe), 0); |
} |
} |
|
static void ironlake_pfit_disable(struct intel_crtc *crtc) |
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
4502,7 → 5045,7 |
|
/* To avoid upsetting the power well on haswell only disable the pfit if |
* it's in use. The hw state code will make sure we get this right. */ |
if (crtc->config.pch_pfit.enabled) { |
if (force || crtc->config->pch_pfit.enabled) { |
I915_WRITE(PF_CTL(pipe), 0); |
I915_WRITE(PF_WIN_POS(pipe), 0); |
I915_WRITE(PF_WIN_SZ(pipe), 0); |
4518,31 → 5061,27 |
int pipe = intel_crtc->pipe; |
u32 reg, temp; |
|
if (!intel_crtc->active) |
return; |
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->disable(encoder); |
|
intel_crtc_disable_planes(crtc); |
|
drm_crtc_vblank_off(crtc); |
assert_vblank_disabled(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->disable(encoder); |
|
if (intel_crtc->config.has_pch_encoder) |
if (intel_crtc->config->has_pch_encoder) |
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
|
intel_disable_pipe(intel_crtc); |
|
ironlake_pfit_disable(intel_crtc); |
ironlake_pfit_disable(intel_crtc, false); |
|
if (intel_crtc->config->has_pch_encoder) |
ironlake_fdi_disable(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
if (encoder->post_disable) |
encoder->post_disable(encoder); |
|
if (intel_crtc->config.has_pch_encoder) { |
ironlake_fdi_disable(crtc); |
|
if (intel_crtc->config->has_pch_encoder) { |
ironlake_disable_pch_transcoder(dev_priv, pipe); |
|
if (HAS_PCH_CPT(dev)) { |
4560,18 → 5099,8 |
I915_WRITE(PCH_DPLL_SEL, temp); |
} |
|
/* disable PCH DPLL */ |
intel_disable_shared_dpll(intel_crtc); |
|
ironlake_fdi_pll_disable(intel_crtc); |
} |
|
intel_crtc->active = false; |
intel_update_watermarks(crtc); |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
} |
|
static void haswell_crtc_disable(struct drm_crtc *crtc) |
4580,39 → 5109,37 |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_encoder *encoder; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
|
if (!intel_crtc->active) |
return; |
|
intel_crtc_disable_planes(crtc); |
|
drm_crtc_vblank_off(crtc); |
assert_vblank_disabled(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) { |
intel_opregion_notify_encoder(encoder, false); |
encoder->disable(encoder); |
} |
|
if (intel_crtc->config.has_pch_encoder) |
drm_crtc_vblank_off(crtc); |
assert_vblank_disabled(crtc); |
|
if (intel_crtc->config->has_pch_encoder) |
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
false); |
intel_disable_pipe(intel_crtc); |
|
if (intel_crtc->config.dp_encoder_is_mst) |
if (intel_crtc->config->dp_encoder_is_mst) |
intel_ddi_set_vc_payload_alloc(crtc, false); |
|
if (!is_dsi) |
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
|
if (IS_SKYLAKE(dev)) |
skylake_pfit_disable(intel_crtc); |
if (INTEL_INFO(dev)->gen >= 9) |
skylake_scaler_disable(intel_crtc); |
else |
ironlake_pfit_disable(intel_crtc); |
ironlake_pfit_disable(intel_crtc, false); |
|
if (!is_dsi) |
intel_ddi_disable_pipe_clock(intel_crtc); |
|
if (intel_crtc->config.has_pch_encoder) { |
if (intel_crtc->config->has_pch_encoder) { |
lpt_disable_pch_transcoder(dev_priv); |
intel_ddi_fdi_disable(crtc); |
} |
4620,32 → 5147,15 |
for_each_encoder_on_crtc(dev, crtc, encoder) |
if (encoder->post_disable) |
encoder->post_disable(encoder); |
|
intel_crtc->active = false; |
intel_update_watermarks(crtc); |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
|
if (intel_crtc_to_shared_dpll(intel_crtc)) |
intel_disable_shared_dpll(intel_crtc); |
} |
|
static void ironlake_crtc_off(struct drm_crtc *crtc) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
intel_put_shared_dpll(intel_crtc); |
} |
|
|
static void i9xx_pfit_enable(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc_config *pipe_config = &crtc->config; |
struct intel_crtc_state *pipe_config = crtc->config; |
|
if (!crtc->config.gmch_pfit.control) |
if (!pipe_config->gmch_pfit.control) |
return; |
|
/* |
4674,12 → 5184,34 |
return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
case PORT_D: |
return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
case PORT_E: |
return POWER_DOMAIN_PORT_DDI_E_2_LANES; |
default: |
WARN_ON_ONCE(1); |
MISSING_CASE(port); |
return POWER_DOMAIN_PORT_OTHER; |
} |
} |
|
static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
{ |
switch (port) { |
case PORT_A: |
return POWER_DOMAIN_AUX_A; |
case PORT_B: |
return POWER_DOMAIN_AUX_B; |
case PORT_C: |
return POWER_DOMAIN_AUX_C; |
case PORT_D: |
return POWER_DOMAIN_AUX_D; |
case PORT_E: |
/* FIXME: Check VBT for actual wiring of PORT E */ |
return POWER_DOMAIN_AUX_D; |
default: |
MISSING_CASE(port); |
return POWER_DOMAIN_AUX_A; |
} |
} |
|
#define for_each_power_domain(domain, mask) \ |
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
if ((1 << (domain)) & (mask)) |
4711,6 → 5243,36 |
} |
} |
|
enum intel_display_power_domain |
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) |
{ |
struct drm_device *dev = intel_encoder->base.dev; |
struct intel_digital_port *intel_dig_port; |
|
switch (intel_encoder->type) { |
case INTEL_OUTPUT_UNKNOWN: |
case INTEL_OUTPUT_HDMI: |
/* |
* Only DDI platforms should ever use these output types. |
* We can get here after the HDMI detect code has already set |
* the type of the shared encoder. Since we can't be sure |
* what's the status of the given connectors, play safe and |
* run the DP detection too. |
*/ |
WARN_ON_ONCE(!HAS_DDI(dev)); |
case INTEL_OUTPUT_DISPLAYPORT: |
case INTEL_OUTPUT_EDP: |
intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
return port_to_aux_power_domain(intel_dig_port->port); |
case INTEL_OUTPUT_DP_MST: |
intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; |
return port_to_aux_power_domain(intel_dig_port->port); |
default: |
MISSING_CASE(intel_encoder->type); |
return POWER_DOMAIN_AUX_A; |
} |
} |
|
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
4720,12 → 5282,15 |
unsigned long mask; |
enum transcoder transcoder; |
|
if (!crtc->state->active) |
return 0; |
|
transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
|
mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
if (intel_crtc->config.pch_pfit.enabled || |
intel_crtc->config.pch_pfit.force_thru) |
if (intel_crtc->config->pch_pfit.enabled || |
intel_crtc->config->pch_pfit.force_thru) |
mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4734,64 → 5299,131 |
return mask; |
} |
|
static void modeset_update_crtc_power_domains(struct drm_device *dev) |
static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
struct intel_crtc *crtc; |
|
/* |
* First get all needed power domains, then put all unneeded, to avoid |
* any unnecessary toggling of the power wells. |
*/ |
for_each_intel_crtc(dev, crtc) { |
struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum intel_display_power_domain domain; |
unsigned long domains, new_domains, old_domains; |
|
if (!crtc->base.enabled) |
continue; |
old_domains = intel_crtc->enabled_power_domains; |
intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); |
|
pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
domains = new_domains & ~old_domains; |
|
for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
for_each_power_domain(domain, domains) |
intel_display_power_get(dev_priv, domain); |
|
return old_domains & ~new_domains; |
} |
|
if (dev_priv->display.modeset_global_resources) |
dev_priv->display.modeset_global_resources(dev); |
|
for_each_intel_crtc(dev, crtc) { |
static void modeset_put_power_domains(struct drm_i915_private *dev_priv, |
unsigned long domains) |
{ |
enum intel_display_power_domain domain; |
|
for_each_power_domain(domain, crtc->enabled_power_domains) |
for_each_power_domain(domain, domains) |
intel_display_power_put(dev_priv, domain); |
} |
|
crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
{ |
struct drm_device *dev = state->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned long put_domains[I915_MAX_PIPES] = {}; |
struct drm_crtc_state *crtc_state; |
struct drm_crtc *crtc; |
int i; |
|
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
if (needs_modeset(crtc->state)) |
put_domains[to_intel_crtc(crtc)->pipe] = |
modeset_get_crtc_power_domains(crtc); |
} |
|
intel_display_set_init_power(dev_priv, false); |
if (dev_priv->display.modeset_commit_cdclk) { |
unsigned int cdclk = to_intel_atomic_state(state)->cdclk; |
|
if (cdclk != dev_priv->cdclk_freq && |
!WARN_ON(!state->allow_modeset)) |
dev_priv->display.modeset_commit_cdclk(state); |
} |
|
/* returns HPLL frequency in kHz */ |
static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
for (i = 0; i < I915_MAX_PIPES; i++) |
if (put_domains[i]) |
modeset_put_power_domains(dev_priv, put_domains[i]); |
} |
|
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
{ |
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
int max_cdclk_freq = dev_priv->max_cdclk_freq; |
|
/* Obtain SKU information */ |
mutex_lock(&dev_priv->dpio_lock); |
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
CCK_FUSE_HPLL_FREQ_MASK; |
mutex_unlock(&dev_priv->dpio_lock); |
if (INTEL_INFO(dev_priv)->gen >= 9 || |
IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
return max_cdclk_freq; |
else if (IS_CHERRYVIEW(dev_priv)) |
return max_cdclk_freq*95/100; |
else if (INTEL_INFO(dev_priv)->gen < 4) |
return 2*max_cdclk_freq*90/100; |
else |
return max_cdclk_freq*90/100; |
} |
|
return vco_freq[hpll_freq] * 1000; |
static void intel_update_max_cdclk(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (IS_SKYLAKE(dev)) { |
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
|
if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
dev_priv->max_cdclk_freq = 675000; |
else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
dev_priv->max_cdclk_freq = 540000; |
else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
dev_priv->max_cdclk_freq = 450000; |
else |
dev_priv->max_cdclk_freq = 337500; |
} else if (IS_BROADWELL(dev)) { |
/* |
* FIXME with extra cooling we can allow |
* 540 MHz for ULX and 675 Mhz for ULT. |
* How can we know if extra cooling is |
* available? PCI ID, VTB, something else? |
*/ |
if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
dev_priv->max_cdclk_freq = 450000; |
else if (IS_BDW_ULX(dev)) |
dev_priv->max_cdclk_freq = 450000; |
else if (IS_BDW_ULT(dev)) |
dev_priv->max_cdclk_freq = 540000; |
else |
dev_priv->max_cdclk_freq = 675000; |
} else if (IS_CHERRYVIEW(dev)) { |
dev_priv->max_cdclk_freq = 320000; |
} else if (IS_VALLEYVIEW(dev)) { |
dev_priv->max_cdclk_freq = 400000; |
} else { |
/* otherwise assume cdclk is fixed */ |
dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; |
} |
|
static void vlv_update_cdclk(struct drm_device *dev) |
dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
|
DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
dev_priv->max_cdclk_freq); |
|
DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", |
dev_priv->max_dotclk_freq); |
} |
|
static void intel_update_cdclk(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
dev_priv->vlv_cdclk_freq); |
dev_priv->cdclk_freq); |
|
/* |
* Program the gmbus_freq based on the cdclk frequency. |
4798,9 → 5430,412 |
* BSpec erroneously claims we should aim for 4MHz, but |
* in fact 1MHz is the correct frequency. |
*/ |
I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
if (IS_VALLEYVIEW(dev)) { |
/* |
* Program the gmbus_freq based on the cdclk frequency. |
* BSpec erroneously claims we should aim for 4MHz, but |
* in fact 1MHz is the correct frequency. |
*/ |
I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
} |
|
if (dev_priv->max_cdclk_freq == 0) |
intel_update_max_cdclk(dev); |
} |
|
static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t divider; |
uint32_t ratio; |
uint32_t current_freq; |
int ret; |
|
/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ |
switch (frequency) { |
case 144000: |
divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
ratio = BXT_DE_PLL_RATIO(60); |
break; |
case 288000: |
divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
ratio = BXT_DE_PLL_RATIO(60); |
break; |
case 384000: |
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
ratio = BXT_DE_PLL_RATIO(60); |
break; |
case 576000: |
divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
ratio = BXT_DE_PLL_RATIO(60); |
break; |
case 624000: |
divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
ratio = BXT_DE_PLL_RATIO(65); |
break; |
case 19200: |
/* |
* Bypass frequency with DE PLL disabled. Init ratio, divider |
* to suppress GCC warning. |
*/ |
ratio = 0; |
divider = 0; |
break; |
default: |
DRM_ERROR("unsupported CDCLK freq %d", frequency); |
|
return; |
} |
|
mutex_lock(&dev_priv->rps.hw_lock); |
/* Inform power controller of upcoming frequency change */ |
ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
0x80000000); |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
if (ret) { |
DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", |
ret, frequency); |
return; |
} |
|
current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; |
/* convert from .1 fixpoint MHz with -1MHz offset to kHz */ |
current_freq = current_freq * 500 + 1000; |
|
/* |
* DE PLL has to be disabled when |
* - setting to 19.2MHz (bypass, PLL isn't used) |
* - before setting to 624MHz (PLL needs toggling) |
* - before setting to any frequency from 624MHz (PLL needs toggling) |
*/ |
if (frequency == 19200 || frequency == 624000 || |
current_freq == 624000) { |
I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); |
/* Timeout 200us */ |
if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), |
1)) |
DRM_ERROR("timout waiting for DE PLL unlock\n"); |
} |
|
if (frequency != 19200) { |
uint32_t val; |
|
val = I915_READ(BXT_DE_PLL_CTL); |
val &= ~BXT_DE_PLL_RATIO_MASK; |
val |= ratio; |
I915_WRITE(BXT_DE_PLL_CTL, val); |
|
I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); |
/* Timeout 200us */ |
if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) |
DRM_ERROR("timeout waiting for DE PLL lock\n"); |
|
val = I915_READ(CDCLK_CTL); |
val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; |
val |= divider; |
/* |
* Disable SSA Precharge when CD clock frequency < 500 MHz, |
* enable otherwise. |
*/ |
val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
if (frequency >= 500000) |
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
|
val &= ~CDCLK_FREQ_DECIMAL_MASK; |
/* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
val |= (frequency - 1000) / 500; |
I915_WRITE(CDCLK_CTL, val); |
} |
|
mutex_lock(&dev_priv->rps.hw_lock); |
ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
DIV_ROUND_UP(frequency, 25000)); |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
if (ret) { |
DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", |
ret, frequency); |
return; |
} |
|
intel_update_cdclk(dev); |
} |
|
void broxton_init_cdclk(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t val; |
|
/* |
* NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT |
* or else the reset will hang because there is no PCH to respond. |
* Move the handshake programming to initialization sequence. |
* Previously was left up to BIOS. |
*/ |
val = I915_READ(HSW_NDE_RSTWRN_OPT); |
val &= ~RESET_PCH_HANDSHAKE_ENABLE; |
I915_WRITE(HSW_NDE_RSTWRN_OPT, val); |
|
/* Enable PG1 for cdclk */ |
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
|
/* check if cd clock is enabled */ |
if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { |
DRM_DEBUG_KMS("Display already initialized\n"); |
return; |
} |
|
/* |
* FIXME: |
* - The initial CDCLK needs to be read from VBT. |
* Need to make this change after VBT has changes for BXT. |
* - check if setting the max (or any) cdclk freq is really necessary |
* here, it belongs to modeset time |
*/ |
broxton_set_cdclk(dev, 624000); |
|
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
POSTING_READ(DBUF_CTL); |
|
udelay(10); |
|
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
DRM_ERROR("DBuf power enable timeout!\n"); |
} |
|
void broxton_uninit_cdclk(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
POSTING_READ(DBUF_CTL); |
|
udelay(10); |
|
if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
DRM_ERROR("DBuf power disable timeout!\n"); |
|
/* Set minimum (bypass) frequency, in effect turning off the DE PLL */ |
broxton_set_cdclk(dev, 19200); |
|
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
} |
|
static const struct skl_cdclk_entry { |
unsigned int freq; |
unsigned int vco; |
} skl_cdclk_frequencies[] = { |
{ .freq = 308570, .vco = 8640 }, |
{ .freq = 337500, .vco = 8100 }, |
{ .freq = 432000, .vco = 8640 }, |
{ .freq = 450000, .vco = 8100 }, |
{ .freq = 540000, .vco = 8100 }, |
{ .freq = 617140, .vco = 8640 }, |
{ .freq = 675000, .vco = 8100 }, |
}; |
|
static unsigned int skl_cdclk_decimal(unsigned int freq) |
{ |
return (freq - 1000) / 500; |
} |
|
static unsigned int skl_cdclk_get_vco(unsigned int freq) |
{ |
unsigned int i; |
|
for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { |
const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; |
|
if (e->freq == freq) |
return e->vco; |
} |
|
return 8100; |
} |
|
static void |
skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) |
{ |
unsigned int min_freq; |
u32 val; |
|
/* select the minimum CDCLK before enabling DPLL 0 */ |
val = I915_READ(CDCLK_CTL); |
val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; |
val |= CDCLK_FREQ_337_308; |
|
if (required_vco == 8640) |
min_freq = 308570; |
else |
min_freq = 337500; |
|
val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); |
|
I915_WRITE(CDCLK_CTL, val); |
POSTING_READ(CDCLK_CTL); |
|
/* |
* We always enable DPLL0 with the lowest link rate possible, but still |
* taking into account the VCO required to operate the eDP panel at the |
* desired frequency. The usual DP link rates operate with a VCO of |
* 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. |
* The modeset code is responsible for the selection of the exact link |
* rate later on, with the constraint of choosing a frequency that |
* works with required_vco. |
*/ |
val = I915_READ(DPLL_CTRL1); |
|
val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | |
DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); |
val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
if (required_vco == 8640) |
val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
SKL_DPLL0); |
else |
val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
SKL_DPLL0); |
|
I915_WRITE(DPLL_CTRL1, val); |
POSTING_READ(DPLL_CTRL1); |
|
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); |
|
if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) |
DRM_ERROR("DPLL0 not locked\n"); |
} |
|
static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
{ |
int ret; |
u32 val; |
|
/* inform PCU we want to change CDCLK */ |
val = SKL_CDCLK_PREPARE_FOR_CHANGE; |
mutex_lock(&dev_priv->rps.hw_lock); |
ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); |
} |
|
static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) |
{ |
unsigned int i; |
|
for (i = 0; i < 15; i++) { |
if (skl_cdclk_pcu_ready(dev_priv)) |
return true; |
udelay(10); |
} |
|
return false; |
} |
|
static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) |
{ |
struct drm_device *dev = dev_priv->dev; |
u32 freq_select, pcu_ack; |
|
DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); |
|
if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { |
DRM_ERROR("failed to inform PCU about cdclk change\n"); |
return; |
} |
|
/* set CDCLK_CTL */ |
switch(freq) { |
case 450000: |
case 432000: |
freq_select = CDCLK_FREQ_450_432; |
pcu_ack = 1; |
break; |
case 540000: |
freq_select = CDCLK_FREQ_540; |
pcu_ack = 2; |
break; |
case 308570: |
case 337500: |
default: |
freq_select = CDCLK_FREQ_337_308; |
pcu_ack = 0; |
break; |
case 617140: |
case 675000: |
freq_select = CDCLK_FREQ_675_617; |
pcu_ack = 3; |
break; |
} |
|
I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); |
POSTING_READ(CDCLK_CTL); |
|
/* inform PCU of the change */ |
mutex_lock(&dev_priv->rps.hw_lock); |
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
intel_update_cdclk(dev); |
} |
|
void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
{ |
/* disable DBUF power */ |
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
POSTING_READ(DBUF_CTL); |
|
udelay(10); |
|
if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) |
DRM_ERROR("DBuf power disable timeout\n"); |
|
/* |
* DMC assumes ownership of LCPLL and will get confused if we touch it. |
*/ |
if (dev_priv->csr.dmc_payload) { |
/* disable DPLL0 */ |
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & |
~LCPLL_PLL_ENABLE); |
if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) |
DRM_ERROR("Couldn't disable DPLL0\n"); |
} |
|
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
} |
|
void skl_init_cdclk(struct drm_i915_private *dev_priv) |
{ |
u32 val; |
unsigned int required_vco; |
|
/* enable PCH reset handshake */ |
val = I915_READ(HSW_NDE_RSTWRN_OPT); |
I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); |
|
/* enable PG1 and Misc I/O */ |
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
|
/* DPLL0 not enabled (happens on early BIOS versions) */ |
if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { |
/* enable DPLL0 */ |
required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); |
skl_dpll0_enable(dev_priv, required_vco); |
} |
|
/* set CDCLK to the frequency the BIOS chose */ |
skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); |
|
/* enable DBUF power */ |
I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); |
POSTING_READ(DBUF_CTL); |
|
udelay(10); |
|
if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) |
DRM_ERROR("DBuf power enable timeout\n"); |
} |
|
/* Adjust CDclk dividers to allow high res or save power if possible */ |
static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
{ |
4807,7 → 5842,8 |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 val, cmd; |
|
WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
!= dev_priv->cdclk_freq); |
|
if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
cmd = 2; |
4828,26 → 5864,25 |
} |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
mutex_lock(&dev_priv->sb_lock); |
|
if (cdclk == 400000) { |
u32 divider; |
|
divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
|
mutex_lock(&dev_priv->dpio_lock); |
/* adjust cdclk divider */ |
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
val &= ~DISPLAY_FREQUENCY_VALUES; |
val &= ~CCK_FREQUENCY_VALUES; |
val |= divider; |
vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
|
if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & |
DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
50)) |
DRM_ERROR("timed out waiting for CDclk change\n"); |
mutex_unlock(&dev_priv->dpio_lock); |
} |
|
mutex_lock(&dev_priv->dpio_lock); |
/* adjust self-refresh exit latency value */ |
val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
val &= ~0x7f; |
4861,9 → 5896,10 |
else |
val |= 3000 / 250; /* 3.0 usec */ |
vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
mutex_unlock(&dev_priv->dpio_lock); |
|
vlv_update_cdclk(dev); |
mutex_unlock(&dev_priv->sb_lock); |
|
intel_update_cdclk(dev); |
} |
|
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4871,27 → 5907,27 |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 val, cmd; |
|
WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
!= dev_priv->cdclk_freq); |
|
switch (cdclk) { |
case 400000: |
cmd = 3; |
break; |
case 333333: |
case 320000: |
cmd = 2; |
break; |
case 266667: |
cmd = 1; |
break; |
case 200000: |
cmd = 0; |
break; |
default: |
WARN_ON(1); |
MISSING_CASE(cdclk); |
return; |
} |
|
/* |
* Specs are full of misinformation, but testing on actual |
* hardware has shown that we just need to write the desired |
* CCK divider into the Punit register. |
*/ |
cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
|
mutex_lock(&dev_priv->rps.hw_lock); |
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
val &= ~DSPFREQGUAR_MASK_CHV; |
4904,7 → 5940,7 |
} |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
vlv_update_cdclk(dev); |
intel_update_cdclk(dev); |
} |
|
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4911,27 → 5947,25 |
int max_pixclk) |
{ |
int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
|
/* FIXME: Punit isn't quite ready yet */ |
if (IS_CHERRYVIEW(dev_priv->dev)) |
return 400000; |
|
/* |
* Really only a few cases to deal with, as only 4 CDclks are supported: |
* 200MHz |
* 267MHz |
* 320/333MHz (depends on HPLL freq) |
* 400MHz |
* So we check to see whether we're above 90% of the lower bin and |
* adjust if needed. |
* 400MHz (VLV only) |
* So we check to see whether we're above 90% (VLV) or 95% (CHV) |
* of the lower bin and adjust if needed. |
* |
* We seem to get an unstable or solid color picture at 200MHz. |
* Not sure what's wrong. For now use 200MHz only when all pipes |
* are off. |
*/ |
if (max_pixclk > freq_320*9/10) |
if (!IS_CHERRYVIEW(dev_priv) && |
max_pixclk > freq_320*limit/100) |
return 400000; |
else if (max_pixclk > 266667*9/10) |
else if (max_pixclk > 266667*limit/100) |
return freq_320; |
else if (max_pixclk > 0) |
return 266667; |
4939,47 → 5973,123 |
return 200000; |
} |
|
/* compute the max pixel clock for new configuration */ |
static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
int max_pixclk) |
{ |
struct drm_device *dev = dev_priv->dev; |
/* |
* FIXME: |
* - remove the guardband, it's not needed on BXT |
* - set 19.2MHz bypass frequency if there are no active pipes |
*/ |
if (max_pixclk > 576000*9/10) |
return 624000; |
else if (max_pixclk > 384000*9/10) |
return 576000; |
else if (max_pixclk > 288000*9/10) |
return 384000; |
else if (max_pixclk > 144000*9/10) |
return 288000; |
else |
return 144000; |
} |
|
/* Compute the max pixel clock for new configuration. Uses atomic state if |
* that's non-NULL, look at current state otherwise. */ |
static int intel_mode_max_pixclk(struct drm_device *dev, |
struct drm_atomic_state *state) |
{ |
struct intel_crtc *intel_crtc; |
struct intel_crtc_state *crtc_state; |
int max_pixclk = 0; |
|
for_each_intel_crtc(dev, intel_crtc) { |
if (intel_crtc->new_enabled) |
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
if (IS_ERR(crtc_state)) |
return PTR_ERR(crtc_state); |
|
if (!crtc_state->base.enable) |
continue; |
|
max_pixclk = max(max_pixclk, |
intel_crtc->new_config->adjusted_mode.crtc_clock); |
crtc_state->base.adjusted_mode.crtc_clock); |
} |
|
return max_pixclk; |
} |
|
static void valleyview_modeset_global_pipes(struct drm_device *dev, |
unsigned *prepare_pipes) |
static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
{ |
struct drm_device *dev = state->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc; |
int max_pixclk = intel_mode_max_pixclk(dev_priv); |
int max_pixclk = intel_mode_max_pixclk(dev, state); |
|
if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
dev_priv->vlv_cdclk_freq) |
return; |
if (max_pixclk < 0) |
return max_pixclk; |
|
/* disable/enable all currently active pipes while we change cdclk */ |
for_each_intel_crtc(dev, intel_crtc) |
if (intel_crtc->base.enabled) |
*prepare_pipes |= (1 << intel_crtc->pipe); |
to_intel_atomic_state(state)->cdclk = |
valleyview_calc_cdclk(dev_priv, max_pixclk); |
|
return 0; |
} |
|
static void valleyview_modeset_global_resources(struct drm_device *dev) |
static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
{ |
struct drm_device *dev = state->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int max_pixclk = intel_mode_max_pixclk(dev_priv); |
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
int max_pixclk = intel_mode_max_pixclk(dev, state); |
|
if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
if (max_pixclk < 0) |
return max_pixclk; |
|
to_intel_atomic_state(state)->cdclk = |
broxton_calc_cdclk(dev_priv, max_pixclk); |
|
return 0; |
} |
|
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
{ |
unsigned int credits, default_credits; |
|
if (IS_CHERRYVIEW(dev_priv)) |
default_credits = PFI_CREDIT(12); |
else |
default_credits = PFI_CREDIT(8); |
|
if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
/* CHV suggested value is 31 or 63 */ |
if (IS_CHERRYVIEW(dev_priv)) |
credits = PFI_CREDIT_63; |
else |
credits = PFI_CREDIT(15); |
} else { |
credits = default_credits; |
} |
|
/* |
* WA - write default credits before re-programming |
* FIXME: should we also set the resend bit here? |
*/ |
I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
default_credits); |
|
I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | |
credits | PFI_CREDIT_RESEND); |
|
/* |
* FIXME is this guaranteed to clear |
* immediately or should we poll for it? |
*/ |
WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); |
} |
|
static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
{ |
struct drm_device *dev = old_state->dev; |
unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
/* |
* FIXME: We can end up here with all power domains off, yet |
* with a CDCLK frequency other than the minimum. To account |
* for this take the PIPE-A power domain, which covers the HW |
4995,9 → 6105,10 |
else |
valleyview_set_cdclk(dev, req_cdclk); |
|
vlv_program_pfi_credits(dev_priv); |
|
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
} |
} |
|
static void valleyview_crtc_enable(struct drm_crtc *crtc) |
{ |
5008,23 → 6119,14 |
int pipe = intel_crtc->pipe; |
bool is_dsi; |
|
WARN_ON(!crtc->enabled); |
|
if (intel_crtc->active) |
if (WARN_ON(intel_crtc->active)) |
return; |
|
is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
|
if (!is_dsi) { |
if (IS_CHERRYVIEW(dev)) |
chv_prepare_pll(intel_crtc, &intel_crtc->config); |
else |
vlv_prepare_pll(intel_crtc, &intel_crtc->config); |
} |
if (intel_crtc->config->has_dp_encoder) |
intel_dp_set_m_n(intel_crtc, M1_N1); |
|
if (intel_crtc->config.has_dp_encoder) |
intel_dp_set_m_n(intel_crtc); |
|
intel_set_pipe_timings(intel_crtc); |
|
if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5045,11 → 6147,14 |
encoder->pre_pll_enable(encoder); |
|
if (!is_dsi) { |
if (IS_CHERRYVIEW(dev)) |
chv_enable_pll(intel_crtc, &intel_crtc->config); |
else |
vlv_enable_pll(intel_crtc, &intel_crtc->config); |
if (IS_CHERRYVIEW(dev)) { |
chv_prepare_pll(intel_crtc, intel_crtc->config); |
chv_enable_pll(intel_crtc, intel_crtc->config); |
} else { |
vlv_prepare_pll(intel_crtc, intel_crtc->config); |
vlv_enable_pll(intel_crtc, intel_crtc->config); |
} |
} |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
if (encoder->pre_enable) |
5059,19 → 6164,13 |
|
intel_crtc_load_lut(crtc); |
|
intel_update_watermarks(crtc); |
intel_enable_pipe(intel_crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->enable(encoder); |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
intel_crtc_enable_planes(crtc); |
|
/* Underruns don't raise interrupts, so check manually. */ |
i9xx_check_fifo_underruns(dev_priv); |
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->enable(encoder); |
} |
|
static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5079,8 → 6178,8 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); |
I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); |
I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); |
} |
|
static void i9xx_crtc_enable(struct drm_crtc *crtc) |
5091,15 → 6190,13 |
struct intel_encoder *encoder; |
int pipe = intel_crtc->pipe; |
|
WARN_ON(!crtc->enabled); |
|
if (intel_crtc->active) |
if (WARN_ON(intel_crtc->active)) |
return; |
|
i9xx_set_pll_dividers(intel_crtc); |
|
if (intel_crtc->config.has_dp_encoder) |
intel_dp_set_m_n(intel_crtc); |
if (intel_crtc->config->has_dp_encoder) |
intel_dp_set_m_n(intel_crtc, M1_N1); |
|
intel_set_pipe_timings(intel_crtc); |
|
5123,26 → 6220,11 |
intel_update_watermarks(crtc); |
intel_enable_pipe(intel_crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->enable(encoder); |
|
assert_vblank_disabled(crtc); |
drm_crtc_vblank_on(crtc); |
|
intel_crtc_enable_planes(crtc); |
|
/* |
* Gen2 reports pipe underruns whenever all planes are disabled. |
* So don't enable underrun reporting before at least some planes |
* are enabled. |
* FIXME: Need to fix the logic to work when we turn off all planes |
* but leave the pipe running. |
*/ |
if (IS_GEN2(dev)) |
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
|
/* Underruns don't raise interrupts, so check manually. */ |
i9xx_check_fifo_underruns(dev_priv); |
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->enable(encoder); |
} |
|
static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5150,7 → 6232,7 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
if (!crtc->config.gmch_pfit.control) |
if (!crtc->config->gmch_pfit.control) |
return; |
|
assert_pipe_disabled(dev_priv, crtc->pipe); |
5168,31 → 6250,7 |
struct intel_encoder *encoder; |
int pipe = intel_crtc->pipe; |
|
if (!intel_crtc->active) |
return; |
|
/* |
* Gen2 reports pipe underruns whenever all planes are disabled. |
* So diasble underrun reporting before all the planes get disabled. |
* FIXME: Need to fix the logic to work when we turn off all planes |
* but leave the pipe running. |
*/ |
if (IS_GEN2(dev)) |
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
/* |
* Vblank time updates from the shadow to live plane control register |
* are blocked if the memory self-refresh mode is active at that |
* moment. So to make sure the plane gets truly disabled, disable |
* first the self-refresh mode. The self-refresh enable bit in turn |
* will be checked/applied by the HW only at the next frame start |
* event which is after the vblank start event, so we need to have a |
* wait-for-vblank between disabling the plane and the pipe. |
*/ |
intel_set_memory_cxsr(dev_priv, false); |
intel_crtc_disable_planes(crtc); |
|
/* |
* On gen2 planes are double buffered but the pipe isn't, so we must |
* wait for planes to fully turn off before disabling the pipe. |
* We also need to wait on all gmch platforms because of the |
5200,12 → 6258,12 |
*/ |
intel_wait_for_vblank(dev, pipe); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->disable(encoder); |
|
drm_crtc_vblank_off(crtc); |
assert_vblank_disabled(crtc); |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
encoder->disable(encoder); |
|
intel_disable_pipe(intel_crtc); |
|
i9xx_pfit_disable(intel_crtc); |
5223,42 → 6281,35 |
i9xx_disable_pll(intel_crtc); |
} |
|
for_each_encoder_on_crtc(dev, crtc, encoder) |
if (encoder->post_pll_disable) |
encoder->post_pll_disable(encoder); |
|
if (!IS_GEN2(dev)) |
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
|
intel_crtc->active = false; |
intel_update_watermarks(crtc); |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
} |
|
static void i9xx_crtc_off(struct drm_crtc *crtc) |
static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
{ |
} |
|
/* Master function to enable/disable CRTC and corresponding power wells */ |
void intel_crtc_control(struct drm_crtc *crtc, bool enable) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
enum intel_display_power_domain domain; |
unsigned long domains; |
|
if (enable) { |
if (!intel_crtc->active) { |
domains = get_crtc_power_domains(crtc); |
for_each_power_domain(domain, domains) |
intel_display_power_get(dev_priv, domain); |
intel_crtc->enabled_power_domains = domains; |
if (!intel_crtc->active) |
return; |
|
dev_priv->display.crtc_enable(crtc); |
if (to_intel_plane_state(crtc->primary->state)->visible) { |
intel_pre_disable_primary(crtc); |
|
intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
to_intel_plane_state(crtc->primary->state)->visible = false; |
} |
} else { |
if (intel_crtc->active) { |
|
dev_priv->display.crtc_disable(crtc); |
intel_crtc->active = false; |
intel_update_watermarks(crtc); |
intel_disable_shared_dpll(intel_crtc); |
|
domains = intel_crtc->enabled_power_domains; |
for_each_power_domain(domain, domains) |
5265,60 → 6316,65 |
intel_display_power_put(dev_priv, domain); |
intel_crtc->enabled_power_domains = 0; |
} |
} |
} |
|
/** |
* Sets the power management mode of the pipe and plane. |
/* |
* turn all crtc's off, but do not adjust state |
* This has to be paired with a call to intel_modeset_setup_hw_state. |
*/ |
void intel_crtc_update_dpms(struct drm_crtc *crtc) |
int intel_display_suspend(struct drm_device *dev) |
{ |
struct drm_device *dev = crtc->dev; |
struct intel_encoder *intel_encoder; |
bool enable = false; |
struct drm_mode_config *config = &dev->mode_config; |
struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; |
struct drm_atomic_state *state; |
struct drm_crtc *crtc; |
unsigned crtc_mask = 0; |
int ret = 0; |
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
enable |= intel_encoder->connectors_active; |
if (WARN_ON(!ctx)) |
return 0; |
|
intel_crtc_control(crtc, enable); |
} |
lockdep_assert_held(&ctx->ww_ctx); |
state = drm_atomic_state_alloc(dev); |
if (WARN_ON(!state)) |
return -ENOMEM; |
|
static void intel_crtc_disable(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_connector *connector; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
enum pipe pipe = to_intel_crtc(crtc)->pipe; |
state->acquire_ctx = ctx; |
state->allow_modeset = true; |
|
/* crtc should still be enabled when we disable it. */ |
WARN_ON(!crtc->enabled); |
for_each_crtc(dev, crtc) { |
struct drm_crtc_state *crtc_state = |
drm_atomic_get_crtc_state(state, crtc); |
|
dev_priv->display.crtc_disable(crtc); |
dev_priv->display.off(crtc); |
ret = PTR_ERR_OR_ZERO(crtc_state); |
if (ret) |
goto free; |
|
if (crtc->primary->fb) { |
mutex_lock(&dev->struct_mutex); |
intel_unpin_fb_obj(old_obj); |
i915_gem_track_fb(old_obj, NULL, |
INTEL_FRONTBUFFER_PRIMARY(pipe)); |
mutex_unlock(&dev->struct_mutex); |
crtc->primary->fb = NULL; |
if (!crtc_state->active) |
continue; |
|
crtc_state->active = false; |
crtc_mask |= 1 << drm_crtc_index(crtc); |
} |
|
/* Update computed state. */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
if (!connector->encoder || !connector->encoder->crtc) |
continue; |
if (crtc_mask) { |
ret = drm_atomic_commit(state); |
|
if (connector->encoder->crtc != crtc) |
continue; |
if (!ret) { |
for_each_crtc(dev, crtc) |
if (crtc_mask & (1 << drm_crtc_index(crtc))) |
crtc->state->active = true; |
|
connector->dpms = DRM_MODE_DPMS_OFF; |
to_intel_encoder(connector->encoder)->connectors_active = false; |
return ret; |
} |
} |
|
free: |
if (ret) |
DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
drm_atomic_state_free(state); |
return ret; |
} |
|
void intel_encoder_destroy(struct drm_encoder *encoder) |
{ |
struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
5327,84 → 6383,73 |
kfree(intel_encoder); |
} |
|
/* Simple dpms helper for encoders with just one connector, no cloning and only |
* one kind of off state. It clamps all !ON modes to fully OFF and changes the |
* state of the entire output pipe. */ |
static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
{ |
if (mode == DRM_MODE_DPMS_ON) { |
encoder->connectors_active = true; |
|
intel_crtc_update_dpms(encoder->base.crtc); |
} else { |
encoder->connectors_active = false; |
|
intel_crtc_update_dpms(encoder->base.crtc); |
} |
} |
|
/* Cross check the actual hw state with our own modeset state tracking (and it's |
* internal consistency). */ |
static void intel_connector_check_state(struct intel_connector *connector) |
{ |
if (connector->get_hw_state(connector)) { |
struct intel_encoder *encoder = connector->encoder; |
struct drm_crtc *crtc; |
bool encoder_enabled; |
enum pipe pipe; |
struct drm_crtc *crtc = connector->base.state->crtc; |
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
connector->base.base.id, |
connector->base.name); |
|
/* there is no real hw state for MST connectors */ |
if (connector->mst_port) |
if (connector->get_hw_state(connector)) { |
struct intel_encoder *encoder = connector->encoder; |
struct drm_connector_state *conn_state = connector->base.state; |
|
I915_STATE_WARN(!crtc, |
"connector enabled without attached crtc\n"); |
|
if (!crtc) |
return; |
|
WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
"wrong connector dpms state\n"); |
WARN(connector->base.encoder != &encoder->base, |
"active connector not linked to encoder\n"); |
I915_STATE_WARN(!crtc->state->active, |
"connector is active, but attached crtc isn't\n"); |
|
if (encoder) { |
WARN(!encoder->connectors_active, |
"encoder->connectors_active not set\n"); |
|
encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
WARN(!encoder_enabled, "encoder not enabled\n"); |
if (WARN_ON(!encoder->base.crtc)) |
if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
return; |
|
crtc = encoder->base.crtc; |
I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
"atomic encoder doesn't match attached encoder\n"); |
|
WARN(!crtc->enabled, "crtc not enabled\n"); |
WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
WARN(pipe != to_intel_crtc(crtc)->pipe, |
"encoder active on the wrong pipe\n"); |
I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
"attached encoder crtc differs from connector crtc\n"); |
} else { |
I915_STATE_WARN(crtc && crtc->state->active, |
"attached crtc is active, but connector isn't\n"); |
I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
"best encoder set without crtc!\n"); |
} |
} |
} |
|
/* Even simpler default implementation, if there's really no special case to |
* consider. */ |
void intel_connector_dpms(struct drm_connector *connector, int mode) |
int intel_connector_init(struct intel_connector *connector) |
{ |
/* All the simple cases only support two dpms states. */ |
if (mode != DRM_MODE_DPMS_ON) |
mode = DRM_MODE_DPMS_OFF; |
struct drm_connector_state *connector_state; |
|
if (mode == connector->dpms) |
return; |
connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); |
if (!connector_state) |
return -ENOMEM; |
|
connector->dpms = mode; |
connector->base.state = connector_state; |
return 0; |
} |
|
/* Only need to change hw state when actually enabled */ |
if (connector->encoder) |
intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
struct intel_connector *intel_connector_alloc(void) |
{ |
struct intel_connector *connector; |
|
intel_modeset_check_state(connector->dev); |
connector = kzalloc(sizeof *connector, GFP_KERNEL); |
if (!connector) |
return NULL; |
|
if (intel_connector_init(connector) < 0) { |
kfree(connector); |
return NULL; |
} |
|
return connector; |
} |
|
/* Simple connector->get_hw_state implementation for encoders that support only |
* one connector and no cloning and hence the encoder state determines the state |
* of the connector. */ |
5416,19 → 6461,27 |
return encoder->get_hw_state(encoder, &pipe); |
} |
|
static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
struct intel_crtc_config *pipe_config) |
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *pipe_B_crtc = |
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
return crtc_state->fdi_lanes; |
|
return 0; |
} |
|
static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_atomic_state *state = pipe_config->base.state; |
struct intel_crtc *other_crtc; |
struct intel_crtc_state *other_crtc_state; |
|
DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
pipe_name(pipe), pipe_config->fdi_lanes); |
if (pipe_config->fdi_lanes > 4) { |
DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
pipe_name(pipe), pipe_config->fdi_lanes); |
return false; |
return -EINVAL; |
} |
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
5435,40 → 6488,53 |
if (pipe_config->fdi_lanes > 2) { |
DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
pipe_config->fdi_lanes); |
return false; |
return -EINVAL; |
} else { |
return true; |
return 0; |
} |
} |
|
if (INTEL_INFO(dev)->num_pipes == 2) |
return true; |
return 0; |
|
/* Ivybridge 3 pipe is really complicated */ |
switch (pipe) { |
case PIPE_A: |
return true; |
return 0; |
case PIPE_B: |
if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
pipe_config->fdi_lanes > 2) { |
if (pipe_config->fdi_lanes <= 2) |
return 0; |
|
other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); |
other_crtc_state = |
intel_atomic_get_crtc_state(state, other_crtc); |
if (IS_ERR(other_crtc_state)) |
return PTR_ERR(other_crtc_state); |
|
if (pipe_required_fdi_lanes(other_crtc_state) > 0) { |
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
pipe_name(pipe), pipe_config->fdi_lanes); |
return false; |
return -EINVAL; |
} |
return true; |
return 0; |
case PIPE_C: |
if (!pipe_has_enabled_pch(pipe_B_crtc) || |
pipe_B_crtc->config.fdi_lanes <= 2) { |
if (pipe_config->fdi_lanes > 2) { |
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", |
pipe_name(pipe), pipe_config->fdi_lanes); |
return false; |
return -EINVAL; |
} |
} else { |
|
other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); |
other_crtc_state = |
intel_atomic_get_crtc_state(state, other_crtc); |
if (IS_ERR(other_crtc_state)) |
return PTR_ERR(other_crtc_state); |
|
if (pipe_required_fdi_lanes(other_crtc_state) > 2) { |
DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
return false; |
return -EINVAL; |
} |
return true; |
return 0; |
default: |
BUG(); |
} |
5476,12 → 6542,12 |
|
#define RETRY 1 |
static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
int lane, link_bw, fdi_dotclock; |
bool setup_ok, needs_recompute = false; |
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
int lane, link_bw, fdi_dotclock, ret; |
bool needs_recompute = false; |
|
retry: |
/* FDI is a binary signal running at ~2.7GHz, encoding |
5503,9 → 6569,9 |
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
link_bw, &pipe_config->fdi_m_n); |
|
setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
intel_crtc->pipe, pipe_config); |
if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
pipe_config->pipe_bpp -= 2*3; |
DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
pipe_config->pipe_bpp); |
5518,28 → 6584,51 |
if (needs_recompute) |
return RETRY; |
|
return setup_ok ? 0 : -EINVAL; |
return ret; |
} |
|
static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
struct intel_crtc_state *pipe_config) |
{ |
if (pipe_config->pipe_bpp > 24) |
return false; |
|
/* HSW can handle pixel rate up to cdclk? */ |
if (IS_HASWELL(dev_priv->dev)) |
return true; |
|
/* |
* We compare against max which means we must take |
* the increased cdclk requirement into account when |
* calculating the new cdclk. |
* |
* Should measure whether using a lower cdclk w/o IPS |
*/ |
return ilk_pipe_pixel_rate(pipe_config) <= |
dev_priv->max_cdclk_freq * 95 / 100; |
} |
|
static void hsw_compute_ips_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
pipe_config->ips_enabled = i915.enable_ips && |
hsw_crtc_supports_ips(crtc) && |
pipe_config->pipe_bpp <= 24; |
pipe_config_supports_ips(dev_priv, pipe_config); |
} |
|
static int intel_crtc_compute_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
|
/* FIXME should check pixel clock limits on all platforms */ |
if (INTEL_INFO(dev)->gen < 4) { |
int clock_limit = |
dev_priv->display.get_display_clock_speed(dev); |
int clock_limit = dev_priv->max_cdclk_freq; |
|
/* |
* Enable pixel doubling when the dot clock |
5564,7 → 6653,7 |
* - LVDS dual channel mode |
* - Double wide pipe |
*/ |
if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
pipe_config->pipe_src_w &= ~1; |
|
5572,17 → 6661,9 |
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
*/ |
if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
return -EINVAL; |
|
if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
} else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
/* only a 8bpc pipe, with 6bpc dither through the panel fitter |
* for lvds. */ |
pipe_config->pipe_bpp = 8*3; |
} |
|
if (HAS_IPS(dev)) |
hsw_compute_ips_config(crtc, pipe_config); |
|
5592,32 → 6673,130 |
return 0; |
} |
|
static int valleyview_get_display_clock_speed(struct drm_device *dev) |
static int skylake_get_display_clock_speed(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 val; |
int divider; |
struct drm_i915_private *dev_priv = to_i915(dev); |
uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
uint32_t cdctl = I915_READ(CDCLK_CTL); |
uint32_t linkrate; |
|
/* FIXME: Punit isn't quite ready yet */ |
if (IS_CHERRYVIEW(dev)) |
return 400000; |
if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
return 24000; /* 24MHz is the cd freq with NSSC ref */ |
|
if (dev_priv->hpll_freq == 0) |
dev_priv->hpll_freq = valleyview_get_vco(dev_priv); |
if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) |
return 540000; |
|
mutex_lock(&dev_priv->dpio_lock); |
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
mutex_unlock(&dev_priv->dpio_lock); |
linkrate = (I915_READ(DPLL_CTRL1) & |
DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
|
divider = val & DISPLAY_FREQUENCY_VALUES; |
if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
linkrate == DPLL_CTRL1_LINK_RATE_1080) { |
/* vco 8640 */ |
switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
case CDCLK_FREQ_450_432: |
return 432000; |
case CDCLK_FREQ_337_308: |
return 308570; |
case CDCLK_FREQ_675_617: |
return 617140; |
default: |
WARN(1, "Unknown cd freq selection\n"); |
} |
} else { |
/* vco 8100 */ |
switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
case CDCLK_FREQ_450_432: |
return 450000; |
case CDCLK_FREQ_337_308: |
return 337500; |
case CDCLK_FREQ_675_617: |
return 675000; |
default: |
WARN(1, "Unknown cd freq selection\n"); |
} |
} |
|
WARN((val & DISPLAY_FREQUENCY_STATUS) != |
(divider << DISPLAY_FREQUENCY_STATUS_SHIFT), |
"cdclk change in progress\n"); |
/* error case, do as if DPLL0 isn't enabled */ |
return 24000; |
} |
|
return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
static int broxton_get_display_clock_speed(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = to_i915(dev); |
uint32_t cdctl = I915_READ(CDCLK_CTL); |
uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; |
uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); |
int cdclk; |
|
if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) |
return 19200; |
|
cdclk = 19200 * pll_ratio / 2; |
|
switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { |
case BXT_CDCLK_CD2X_DIV_SEL_1: |
return cdclk; /* 576MHz or 624MHz */ |
case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
return cdclk * 2 / 3; /* 384MHz */ |
case BXT_CDCLK_CD2X_DIV_SEL_2: |
return cdclk / 2; /* 288MHz */ |
case BXT_CDCLK_CD2X_DIV_SEL_4: |
return cdclk / 4; /* 144MHz */ |
} |
|
/* error case, do as if DE PLL isn't enabled */ |
return 19200; |
} |
|
static int broadwell_get_display_clock_speed(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t lcpll = I915_READ(LCPLL_CTL); |
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
|
if (lcpll & LCPLL_CD_SOURCE_FCLK) |
return 800000; |
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
return 450000; |
else if (freq == LCPLL_CLK_FREQ_450) |
return 450000; |
else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
return 540000; |
else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
return 337500; |
else |
return 675000; |
} |
|
static int haswell_get_display_clock_speed(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t lcpll = I915_READ(LCPLL_CTL); |
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
|
if (lcpll & LCPLL_CD_SOURCE_FCLK) |
return 800000; |
else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
return 450000; |
else if (freq == LCPLL_CLK_FREQ_450) |
return 450000; |
else if (IS_HSW_ULT(dev)) |
return 337500; |
else |
return 540000; |
} |
|
static int valleyview_get_display_clock_speed(struct drm_device *dev) |
{ |
return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
CCK_DISPLAY_CLOCK_CONTROL); |
} |
|
static int ilk_get_display_clock_speed(struct drm_device *dev) |
{ |
return 450000; |
} |
|
static int i945_get_display_clock_speed(struct drm_device *dev) |
{ |
return 400000; |
5625,7 → 6804,7 |
|
static int i915_get_display_clock_speed(struct drm_device *dev) |
{ |
return 333000; |
return 333333; |
} |
|
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5641,19 → 6820,19 |
|
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
return 267000; |
return 266667; |
case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
return 333000; |
return 333333; |
case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
return 444000; |
return 444444; |
case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
return 200000; |
default: |
DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
return 133000; |
return 133333; |
case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
return 167000; |
return 166667; |
} |
} |
|
5664,11 → 6843,11 |
pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
|
if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
return 133000; |
return 133333; |
else { |
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
case GC_DISPLAY_CLOCK_333_MHZ: |
return 333000; |
return 333333; |
default: |
case GC_DISPLAY_CLOCK_190_200_MHZ: |
return 190000; |
5678,23 → 6857,40 |
|
static int i865_get_display_clock_speed(struct drm_device *dev) |
{ |
return 266000; |
return 266667; |
} |
|
static int i855_get_display_clock_speed(struct drm_device *dev) |
static int i85x_get_display_clock_speed(struct drm_device *dev) |
{ |
u16 hpllcc = 0; |
|
/* |
* 852GM/852GMV only supports 133 MHz and the HPLLCC |
* encoding is different :( |
* FIXME is this the right way to detect 852GM/852GMV? |
*/ |
if (dev->pdev->revision == 0x1) |
return 133333; |
|
// pci_bus_read_config_word(dev->pdev->bus, |
// PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
|
/* Assume that the hardware is in the high speed state. This |
* should be the default. |
*/ |
switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
case GC_CLOCK_133_200: |
case GC_CLOCK_133_200_2: |
case GC_CLOCK_100_200: |
return 200000; |
case GC_CLOCK_166_250: |
return 250000; |
case GC_CLOCK_100_133: |
return 133000; |
return 133333; |
case GC_CLOCK_133_266: |
case GC_CLOCK_133_266_2: |
case GC_CLOCK_166_266: |
return 266667; |
} |
|
/* Shouldn't happen */ |
5703,9 → 6899,178 |
|
static int i830_get_display_clock_speed(struct drm_device *dev) |
{ |
return 133000; |
return 133333; |
} |
|
static unsigned int intel_hpll_vco(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
static const unsigned int blb_vco[8] = { |
[0] = 3200000, |
[1] = 4000000, |
[2] = 5333333, |
[3] = 4800000, |
[4] = 6400000, |
}; |
static const unsigned int pnv_vco[8] = { |
[0] = 3200000, |
[1] = 4000000, |
[2] = 5333333, |
[3] = 4800000, |
[4] = 2666667, |
}; |
static const unsigned int cl_vco[8] = { |
[0] = 3200000, |
[1] = 4000000, |
[2] = 5333333, |
[3] = 6400000, |
[4] = 3333333, |
[5] = 3566667, |
[6] = 4266667, |
}; |
static const unsigned int elk_vco[8] = { |
[0] = 3200000, |
[1] = 4000000, |
[2] = 5333333, |
[3] = 4800000, |
}; |
static const unsigned int ctg_vco[8] = { |
[0] = 3200000, |
[1] = 4000000, |
[2] = 5333333, |
[3] = 6400000, |
[4] = 2666667, |
[5] = 4266667, |
}; |
const unsigned int *vco_table; |
unsigned int vco; |
uint8_t tmp = 0; |
|
/* FIXME other chipsets? */ |
if (IS_GM45(dev)) |
vco_table = ctg_vco; |
else if (IS_G4X(dev)) |
vco_table = elk_vco; |
else if (IS_CRESTLINE(dev)) |
vco_table = cl_vco; |
else if (IS_PINEVIEW(dev)) |
vco_table = pnv_vco; |
else if (IS_G33(dev)) |
vco_table = blb_vco; |
else |
return 0; |
|
tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); |
|
vco = vco_table[tmp & 0x7]; |
if (vco == 0) |
DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); |
else |
DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); |
|
return vco; |
} |
|
static int gm45_get_display_clock_speed(struct drm_device *dev) |
{ |
unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
uint16_t tmp = 0; |
|
pci_read_config_word(dev->pdev, GCFGC, &tmp); |
|
cdclk_sel = (tmp >> 12) & 0x1; |
|
switch (vco) { |
case 2666667: |
case 4000000: |
case 5333333: |
return cdclk_sel ? 333333 : 222222; |
case 3200000: |
return cdclk_sel ? 320000 : 228571; |
default: |
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); |
return 222222; |
} |
} |
|
static int i965gm_get_display_clock_speed(struct drm_device *dev) |
{ |
static const uint8_t div_3200[] = { 16, 10, 8 }; |
static const uint8_t div_4000[] = { 20, 12, 10 }; |
static const uint8_t div_5333[] = { 24, 16, 14 }; |
const uint8_t *div_table; |
unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
uint16_t tmp = 0; |
|
pci_read_config_word(dev->pdev, GCFGC, &tmp); |
|
cdclk_sel = ((tmp >> 8) & 0x1f) - 1; |
|
if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
goto fail; |
|
switch (vco) { |
case 3200000: |
div_table = div_3200; |
break; |
case 4000000: |
div_table = div_4000; |
break; |
case 5333333: |
div_table = div_5333; |
break; |
default: |
goto fail; |
} |
|
return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
|
fail: |
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
return 200000; |
} |
|
static int g33_get_display_clock_speed(struct drm_device *dev) |
{ |
static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; |
static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; |
static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; |
const uint8_t *div_table; |
unsigned int cdclk_sel, vco = intel_hpll_vco(dev); |
uint16_t tmp = 0; |
|
pci_read_config_word(dev->pdev, GCFGC, &tmp); |
|
cdclk_sel = (tmp >> 4) & 0x7; |
|
if (cdclk_sel >= ARRAY_SIZE(div_3200)) |
goto fail; |
|
switch (vco) { |
case 3200000: |
div_table = div_3200; |
break; |
case 4000000: |
div_table = div_4000; |
break; |
case 4800000: |
div_table = div_4800; |
break; |
case 5333333: |
div_table = div_5333; |
break; |
default: |
goto fail; |
} |
|
return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); |
|
fail: |
DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
return 190476; |
} |
|
static void |
intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
{ |
5747,15 → 7112,18 |
&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
} |
|
static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
int num_connectors) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int refclk; |
|
if (IS_VALLEYVIEW(dev)) { |
WARN_ON(!crtc_state->base.state); |
|
if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
refclk = 100000; |
} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
refclk = dev_priv->vbt.lvds_ssc_freq; |
DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
5779,6 → 7147,7 |
} |
|
static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state, |
intel_clock_t *reduced_clock) |
{ |
struct drm_device *dev = crtc->base.dev; |
5785,24 → 7154,24 |
u32 fp, fp2 = 0; |
|
if (IS_PINEVIEW(dev)) { |
fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); |
fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
if (reduced_clock) |
fp2 = pnv_dpll_compute_fp(reduced_clock); |
} else { |
fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); |
fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
if (reduced_clock) |
fp2 = i9xx_dpll_compute_fp(reduced_clock); |
} |
|
crtc->new_config->dpll_hw_state.fp0 = fp; |
crtc_state->dpll_hw_state.fp0 = fp; |
|
crtc->lowfreq_avail = false; |
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
reduced_clock && i915.powersave) { |
crtc->new_config->dpll_hw_state.fp1 = fp2; |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
reduced_clock) { |
crtc_state->dpll_hw_state.fp1 = fp2; |
crtc->lowfreq_avail = true; |
} else { |
crtc->new_config->dpll_hw_state.fp1 = fp; |
crtc_state->dpll_hw_state.fp1 = fp; |
} |
} |
|
5855,7 → 7224,7 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = crtc->pipe; |
enum transcoder transcoder = crtc->config.cpu_transcoder; |
enum transcoder transcoder = crtc->config->cpu_transcoder; |
|
if (INTEL_INFO(dev)->gen >= 5) { |
I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5866,8 → 7235,8 |
* for gen < 8) and if DRRS is supported (to make sure the |
* registers are not unnecessarily accessed). |
*/ |
if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
crtc->config.has_drrs) { |
if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
crtc->config->has_drrs) { |
I915_WRITE(PIPE_DATA_M2(transcoder), |
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); |
I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); |
5882,17 → 7251,33 |
} |
} |
|
void intel_dp_set_m_n(struct intel_crtc *crtc) |
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
{ |
if (crtc->config.has_pch_encoder) |
intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
|
if (m_n == M1_N1) { |
dp_m_n = &crtc->config->dp_m_n; |
dp_m2_n2 = &crtc->config->dp_m2_n2; |
} else if (m_n == M2_N2) { |
|
/* |
* M2_N2 registers are not supported. Hence m2_n2 divider value |
* needs to be programmed into M1_N1. |
*/ |
dp_m_n = &crtc->config->dp_m2_n2; |
} else { |
DRM_ERROR("Unsupported divider value\n"); |
return; |
} |
|
if (crtc->config->has_pch_encoder) |
intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); |
else |
intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
&crtc->config.dp_m2_n2); |
intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
} |
|
static void vlv_update_pll(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
static void vlv_compute_dpll(struct intel_crtc *crtc, |
struct intel_crtc_state *pipe_config) |
{ |
u32 dpll, dpll_md; |
|
5901,8 → 7286,8 |
* clock for pipe B, since VGA hotplug / manual detection depends |
* on it. |
*/ |
dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; |
/* We should never disable this, set it here for state tracking */ |
if (crtc->pipe == PIPE_B) |
dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
5915,7 → 7300,7 |
} |
|
static void vlv_prepare_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config) |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
5924,7 → 7309,7 |
u32 bestn, bestm1, bestm2, bestp1, bestp2; |
u32 coreclk, reg_val; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
bestn = pipe_config->dpll.n; |
bestm1 = pipe_config->dpll.m1; |
5976,7 → 7361,7 |
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
0x00d0000f); |
|
if (crtc->config.has_dp_encoder) { |
if (pipe_config->has_dp_encoder) { |
/* Use SSC source */ |
if (pipe == PIPE_A) |
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
6002,14 → 7387,14 |
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
|
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
static void chv_update_pll(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
static void chv_compute_dpll(struct intel_crtc *crtc, |
struct intel_crtc_state *pipe_config) |
{ |
pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
DPLL_VCO_ENABLE; |
if (crtc->pipe != PIPE_A) |
pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
6019,7 → 7404,7 |
} |
|
static void chv_prepare_pll(struct intel_crtc *crtc, |
const struct intel_crtc_config *pipe_config) |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6026,9 → 7411,10 |
int pipe = crtc->pipe; |
int dpll_reg = DPLL(crtc->pipe); |
enum dpio_channel port = vlv_pipe_to_channel(pipe); |
u32 loopfilter, intcoeff; |
u32 loopfilter, tribuf_calcntr; |
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
int refclk; |
u32 dpio_val; |
int vco; |
|
bestn = pipe_config->dpll.n; |
bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; |
6036,6 → 7422,9 |
bestm2 = pipe_config->dpll.m2 >> 22; |
bestp1 = pipe_config->dpll.p1; |
bestp2 = pipe_config->dpll.p2; |
vco = pipe_config->dpll.vco; |
dpio_val = 0; |
loopfilter = 0; |
|
/* |
* Enable Refclk and SSC |
6043,7 → 7432,7 |
I915_WRITE(dpll_reg, |
pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
/* p1 and p2 divider */ |
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), |
6064,29 → 7453,58 |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
|
/* M2 fraction division enable */ |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), |
DPIO_CHV_FRAC_DIV_EN | |
(2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); |
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); |
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); |
if (bestm2_frac) |
dpio_val |= DPIO_CHV_FRAC_DIV_EN; |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); |
|
/* Program digital lock detect threshold */ |
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); |
dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | |
DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); |
dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); |
if (!bestm2_frac) |
dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); |
|
/* Loop filter */ |
refclk = i9xx_get_refclk(crtc, 0); |
loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
2 << DPIO_CHV_GAIN_CTRL_SHIFT; |
if (refclk == 100000) |
intcoeff = 11; |
else if (refclk == 38400) |
intcoeff = 10; |
else |
intcoeff = 9; |
loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; |
if (vco == 5400000) { |
loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); |
loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); |
loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); |
tribuf_calcntr = 0x9; |
} else if (vco <= 6200000) { |
loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); |
loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); |
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
tribuf_calcntr = 0x9; |
} else if (vco <= 6480000) { |
loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
tribuf_calcntr = 0x8; |
} else { |
/* Not supported. Apply the same limits as in the max case */ |
loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); |
loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); |
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); |
tribuf_calcntr = 0; |
} |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
|
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); |
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); |
|
/* AFC Recal */ |
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), |
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | |
DPIO_AFC_RECAL); |
|
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
/** |
6104,17 → 7522,18 |
{ |
struct intel_crtc *crtc = |
to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
struct intel_crtc_config pipe_config = { |
struct intel_crtc_state pipe_config = { |
.base.crtc = &crtc->base, |
.pixel_multiplier = 1, |
.dpll = *dpll, |
}; |
|
if (IS_CHERRYVIEW(dev)) { |
chv_update_pll(crtc, &pipe_config); |
chv_compute_dpll(crtc, &pipe_config); |
chv_prepare_pll(crtc, &pipe_config); |
chv_enable_pll(crtc, &pipe_config); |
} else { |
vlv_update_pll(crtc, &pipe_config); |
vlv_compute_dpll(crtc, &pipe_config); |
vlv_prepare_pll(crtc, &pipe_config); |
vlv_enable_pll(crtc, &pipe_config); |
} |
6136,7 → 7555,8 |
vlv_disable_pll(to_i915(dev), pipe); |
} |
|
static void i9xx_update_pll(struct intel_crtc *crtc, |
static void i9xx_compute_dpll(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state, |
intel_clock_t *reduced_clock, |
int num_connectors) |
{ |
6144,22 → 7564,22 |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 dpll; |
bool is_sdvo; |
struct dpll *clock = &crtc->new_config->dpll; |
struct dpll *clock = &crtc_state->dpll; |
|
i9xx_update_pll_dividers(crtc, reduced_clock); |
i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
|
is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); |
is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); |
|
dpll = DPLL_VGA_MODE_DIS; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
dpll |= DPLLB_MODE_LVDS; |
else |
dpll |= DPLLB_MODE_DAC_SERIAL; |
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
dpll |= (crtc->new_config->pixel_multiplier - 1) |
dpll |= (crtc_state->pixel_multiplier - 1) |
<< SDVO_MULTIPLIER_SHIFT_HIRES; |
} |
|
6166,7 → 7586,7 |
if (is_sdvo) |
dpll |= DPLL_SDVO_HIGH_SPEED; |
|
if (crtc->new_config->has_dp_encoder) |
if (crtc_state->has_dp_encoder) |
dpll |= DPLL_SDVO_HIGH_SPEED; |
|
/* compute bitmask from p1 value */ |
6194,9 → 7614,9 |
if (INTEL_INFO(dev)->gen >= 4) |
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
|
if (crtc->new_config->sdvo_tv_clock) |
if (crtc_state->sdvo_tv_clock) |
dpll |= PLL_REF_INPUT_TVCLKINBC; |
else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
else |
6203,16 → 7623,17 |
dpll |= PLL_REF_INPUT_DREFCLK; |
|
dpll |= DPLL_VCO_ENABLE; |
crtc->new_config->dpll_hw_state.dpll = dpll; |
crtc_state->dpll_hw_state.dpll = dpll; |
|
if (INTEL_INFO(dev)->gen >= 4) { |
u32 dpll_md = (crtc->new_config->pixel_multiplier - 1) |
u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
<< DPLL_MD_UDI_MULTIPLIER_SHIFT; |
crtc->new_config->dpll_hw_state.dpll_md = dpll_md; |
crtc_state->dpll_hw_state.dpll_md = dpll_md; |
} |
} |
|
static void i8xx_update_pll(struct intel_crtc *crtc, |
static void i8xx_compute_dpll(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state, |
intel_clock_t *reduced_clock, |
int num_connectors) |
{ |
6219,13 → 7640,13 |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 dpll; |
struct dpll *clock = &crtc->new_config->dpll; |
struct dpll *clock = &crtc_state->dpll; |
|
i9xx_update_pll_dividers(crtc, reduced_clock); |
i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
|
dpll = DPLL_VGA_MODE_DIS; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
} else { |
if (clock->p1 == 2) |
6236,10 → 7657,10 |
dpll |= PLL_P2_DIVIDE_BY_4; |
} |
|
if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
dpll |= DPLL_DVO_2X_MODE; |
|
if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
else |
6246,7 → 7667,7 |
dpll |= PLL_REF_INPUT_DREFCLK; |
|
dpll |= DPLL_VCO_ENABLE; |
crtc->new_config->dpll_hw_state.dpll = dpll; |
crtc_state->dpll_hw_state.dpll = dpll; |
} |
|
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
6254,9 → 7675,8 |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
enum pipe pipe = intel_crtc->pipe; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
struct drm_display_mode *adjusted_mode = |
&intel_crtc->config.adjusted_mode; |
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
uint32_t crtc_vtotal, crtc_vblank_end; |
int vsyncshift = 0; |
|
6314,12 → 7734,12 |
* always be the user's requested size. |
*/ |
I915_WRITE(PIPESRC(pipe), |
((intel_crtc->config.pipe_src_w - 1) << 16) | |
(intel_crtc->config.pipe_src_h - 1)); |
((intel_crtc->config->pipe_src_w - 1) << 16) | |
(intel_crtc->config->pipe_src_h - 1)); |
} |
|
static void intel_get_pipe_timings(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6327,29 → 7747,29 |
uint32_t tmp; |
|
tmp = I915_READ(HTOTAL(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
tmp = I915_READ(HBLANK(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
tmp = I915_READ(HSYNC(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
|
tmp = I915_READ(VTOTAL(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
tmp = I915_READ(VBLANK(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
tmp = I915_READ(VSYNC(cpu_transcoder)); |
pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
|
if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
pipe_config->adjusted_mode.crtc_vtotal += 1; |
pipe_config->adjusted_mode.crtc_vblank_end += 1; |
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
pipe_config->base.adjusted_mode.crtc_vtotal += 1; |
pipe_config->base.adjusted_mode.crtc_vblank_end += 1; |
} |
|
tmp = I915_READ(PIPESRC(crtc->pipe)); |
6356,27 → 7776,32 |
pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
|
pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; |
} |
|
void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; |
mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; |
mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; |
|
mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; |
mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; |
mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; |
|
mode->flags = pipe_config->adjusted_mode.flags; |
mode->flags = pipe_config->base.adjusted_mode.flags; |
mode->type = DRM_MODE_TYPE_DRIVER; |
|
mode->clock = pipe_config->adjusted_mode.crtc_clock; |
mode->flags |= pipe_config->adjusted_mode.flags; |
mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
mode->flags |= pipe_config->base.adjusted_mode.flags; |
|
mode->hsync = drm_mode_hsync(mode); |
mode->vrefresh = drm_mode_vrefresh(mode); |
drm_mode_set_name(mode); |
} |
|
static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6391,17 → 7816,17 |
(intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
|
if (intel_crtc->config.double_wide) |
if (intel_crtc->config->double_wide) |
pipeconf |= PIPECONF_DOUBLE_WIDE; |
|
/* only g4x and later have fancy bpc/dither controls */ |
if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
/* Bspec claims that we can't use dithering for 30bpp pipes. */ |
if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
pipeconf |= PIPECONF_DITHER_EN | |
PIPECONF_DITHER_TYPE_SP; |
|
switch (intel_crtc->config.pipe_bpp) { |
switch (intel_crtc->config->pipe_bpp) { |
case 18: |
pipeconf |= PIPECONF_6BPC; |
break; |
6426,7 → 7851,7 |
} |
} |
|
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
if (INTEL_INFO(dev)->gen < 4 || |
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6435,7 → 7860,7 |
} else |
pipeconf |= PIPECONF_PROGRESSIVE; |
|
if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
|
I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6442,25 → 7867,32 |
POSTING_READ(PIPECONF(intel_crtc->pipe)); |
} |
|
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc) |
static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int refclk, num_connectors = 0; |
intel_clock_t clock, reduced_clock; |
bool ok, has_reduced_clock = false; |
bool is_lvds = false, is_dsi = false; |
intel_clock_t clock; |
bool ok; |
bool is_dsi = false; |
struct intel_encoder *encoder; |
const intel_limit_t *limit; |
struct drm_atomic_state *state = crtc_state->base.state; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
int i; |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->new_crtc != crtc) |
memset(&crtc_state->dpll_hw_state, 0, |
sizeof(crtc_state->dpll_hw_state)); |
|
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != &crtc->base) |
continue; |
|
encoder = to_intel_encoder(connector_state->best_encoder); |
|
switch (encoder->type) { |
case INTEL_OUTPUT_LVDS: |
is_lvds = true; |
break; |
case INTEL_OUTPUT_DSI: |
is_dsi = true; |
break; |
6474,8 → 7906,8 |
if (is_dsi) |
return 0; |
|
if (!crtc->new_config->clock_set) { |
refclk = i9xx_get_refclk(crtc, num_connectors); |
if (!crtc_state->clock_set) { |
refclk = i9xx_get_refclk(crtc_state, num_connectors); |
|
/* |
* Returns a set of divisors for the desired target clock with |
6483,9 → 7915,9 |
* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
* 2) / p1 / p2. |
*/ |
limit = intel_limit(crtc, refclk); |
ok = dev_priv->display.find_dpll(limit, crtc, |
crtc->new_config->port_clock, |
limit = intel_limit(crtc_state, refclk); |
ok = dev_priv->display.find_dpll(limit, crtc_state, |
crtc_state->port_clock, |
refclk, NULL, &clock); |
if (!ok) { |
DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6492,38 → 7924,23 |
return -EINVAL; |
} |
|
if (is_lvds && dev_priv->lvds_downclock_avail) { |
/* |
* Ensure we match the reduced clock's P to the target |
* clock. If the clocks don't match, we can't switch |
* the display clock by using the FP0/FP1. In such case |
* we will disable the LVDS downclock feature. |
*/ |
has_reduced_clock = |
dev_priv->display.find_dpll(limit, crtc, |
dev_priv->lvds_downclock, |
refclk, &clock, |
&reduced_clock); |
} |
/* Compat-code for transition, will disappear. */ |
crtc->new_config->dpll.n = clock.n; |
crtc->new_config->dpll.m1 = clock.m1; |
crtc->new_config->dpll.m2 = clock.m2; |
crtc->new_config->dpll.p1 = clock.p1; |
crtc->new_config->dpll.p2 = clock.p2; |
crtc_state->dpll.n = clock.n; |
crtc_state->dpll.m1 = clock.m1; |
crtc_state->dpll.m2 = clock.m2; |
crtc_state->dpll.p1 = clock.p1; |
crtc_state->dpll.p2 = clock.p2; |
} |
|
if (IS_GEN2(dev)) { |
i8xx_update_pll(crtc, |
has_reduced_clock ? &reduced_clock : NULL, |
i8xx_compute_dpll(crtc, crtc_state, NULL, |
num_connectors); |
} else if (IS_CHERRYVIEW(dev)) { |
chv_update_pll(crtc, crtc->new_config); |
chv_compute_dpll(crtc, crtc_state); |
} else if (IS_VALLEYVIEW(dev)) { |
vlv_update_pll(crtc, crtc->new_config); |
vlv_compute_dpll(crtc, crtc_state); |
} else { |
i9xx_update_pll(crtc, |
has_reduced_clock ? &reduced_clock : NULL, |
i9xx_compute_dpll(crtc, crtc_state, NULL, |
num_connectors); |
} |
|
6531,7 → 7948,7 |
} |
|
static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6561,7 → 7978,7 |
} |
|
static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6574,9 → 7991,9 |
if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) |
return; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
|
clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
clock.m2 = mdiv & DPIO_M2DIV_MASK; |
6584,14 → 8001,12 |
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
|
vlv_clock(refclk, &clock); |
|
/* clock.dot is the fast clock */ |
pipe_config->port_clock = clock.dot / 5; |
pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
} |
|
static void i9xx_get_plane_config(struct intel_crtc *crtc, |
struct intel_plane_config *plane_config) |
static void |
i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
struct intel_initial_plane_config *plane_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6598,28 → 8013,36 |
u32 val, base, offset; |
int pipe = crtc->pipe, plane = crtc->plane; |
int fourcc, pixel_format; |
int aligned_height; |
unsigned int aligned_height; |
struct drm_framebuffer *fb; |
struct intel_framebuffer *intel_fb; |
|
crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
if (!crtc->base.primary->fb) { |
val = I915_READ(DSPCNTR(plane)); |
if (!(val & DISPLAY_PLANE_ENABLE)) |
return; |
|
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
if (!intel_fb) { |
DRM_DEBUG_KMS("failed to alloc fb\n"); |
return; |
} |
|
val = I915_READ(DSPCNTR(plane)); |
fb = &intel_fb->base; |
|
if (INTEL_INFO(dev)->gen >= 4) |
if (val & DISPPLANE_TILED) |
plane_config->tiled = true; |
if (INTEL_INFO(dev)->gen >= 4) { |
if (val & DISPPLANE_TILED) { |
plane_config->tiling = I915_TILING_X; |
fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
} |
} |
|
pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
fourcc = intel_format_to_fourcc(pixel_format); |
crtc->base.primary->fb->pixel_format = fourcc; |
crtc->base.primary->fb->bits_per_pixel = |
drm_format_plane_cpp(fourcc, 0) * 8; |
fourcc = i9xx_format_to_fourcc(pixel_format); |
fb->pixel_format = fourcc; |
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
|
if (INTEL_INFO(dev)->gen >= 4) { |
if (plane_config->tiled) |
if (plane_config->tiling) |
offset = I915_READ(DSPTILEOFF(plane)); |
else |
offset = I915_READ(DSPLINOFF(plane)); |
6630,29 → 8053,30 |
plane_config->base = base; |
|
val = I915_READ(PIPESRC(pipe)); |
crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
fb->width = ((val >> 16) & 0xfff) + 1; |
fb->height = ((val >> 0) & 0xfff) + 1; |
|
val = I915_READ(DSPSTRIDE(pipe)); |
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
// fb->pitches[0] = val & 0xffffffc0; |
fb->pitches[0] = 2560*4; |
|
aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
plane_config->tiled); |
aligned_height = intel_fb_align_height(dev, fb->height, |
fb->pixel_format, |
fb->modifier[0]); |
|
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
aligned_height); |
// plane_config->size = fb->pitches[0] * aligned_height; |
plane_config->size = i915_fbsize*1024*1024; |
|
DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
pipe, plane, crtc->base.primary->fb->width, |
crtc->base.primary->fb->height, |
crtc->base.primary->fb->bits_per_pixel, base, |
crtc->base.primary->fb->pitches[0], |
DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
pipe_name(pipe), plane, fb->width, fb->height, |
fb->bits_per_pixel, base, fb->pitches[0], |
plane_config->size); |
|
plane_config->fb = intel_fb; |
} |
|
static void chv_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6659,30 → 8083,30 |
int pipe = pipe_config->cpu_transcoder; |
enum dpio_channel port = vlv_pipe_to_channel(pipe); |
intel_clock_t clock; |
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; |
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
int refclk = 100000; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); |
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); |
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); |
mutex_unlock(&dev_priv->dpio_lock); |
pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
mutex_unlock(&dev_priv->sb_lock); |
|
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; |
clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); |
clock.m2 = (pll_dw0 & 0xff) << 22; |
if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) |
clock.m2 |= pll_dw2 & 0x3fffff; |
clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; |
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; |
|
chv_clock(refclk, &clock); |
|
/* clock.dot is the fast clock */ |
pipe_config->port_clock = clock.dot / 5; |
pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
} |
|
static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
6768,6 → 8192,14 |
else |
i9xx_crtc_clock_get(crtc, pipe_config); |
|
/* |
* Normally the dotclock is filled in by the encoder .get_config() |
* but in case the pipe is enabled w/o any ports we need a sane |
* default. |
*/ |
pipe_config->base.adjusted_mode.crtc_clock = |
pipe_config->port_clock / pipe_config->pixel_multiplier; |
|
return true; |
} |
|
7029,11 → 8461,10 |
|
if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
with_spread = true; |
if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
with_fdi, "LP PCH doesn't have FDI\n")) |
if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
with_fdi = false; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
tmp &= ~SBI_SSCCTL_DISABLE; |
7053,13 → 8484,12 |
} |
} |
|
reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
SBI_GEN0 : SBI_DBUFF0; |
reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
|
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
/* Sequence to disable CLKOUT_DP */ |
7068,10 → 8498,9 |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t reg, tmp; |
|
mutex_lock(&dev_priv->dpio_lock); |
mutex_lock(&dev_priv->sb_lock); |
|
reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
SBI_GEN0 : SBI_DBUFF0; |
reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
7087,7 → 8516,7 |
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
} |
|
mutex_unlock(&dev_priv->dpio_lock); |
mutex_unlock(&dev_priv->sb_lock); |
} |
|
static void lpt_init_pch_refclk(struct drm_device *dev) |
7122,18 → 8551,23 |
lpt_init_pch_refclk(dev); |
} |
|
static int ironlake_get_refclk(struct drm_crtc *crtc) |
static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_device *dev = crtc_state->base.crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_atomic_state *state = crtc_state->base.state; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
struct intel_encoder *encoder; |
int num_connectors = 0; |
int num_connectors = 0, i; |
bool is_lvds = false; |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->new_crtc != to_intel_crtc(crtc)) |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != crtc_state->base.crtc) |
continue; |
|
encoder = to_intel_encoder(connector_state->best_encoder); |
|
switch (encoder->type) { |
case INTEL_OUTPUT_LVDS: |
is_lvds = true; |
7162,7 → 8596,7 |
|
val = 0; |
|
switch (intel_crtc->config.pipe_bpp) { |
switch (intel_crtc->config->pipe_bpp) { |
case 18: |
val |= PIPECONF_6BPC; |
break; |
7180,15 → 8614,15 |
BUG(); |
} |
|
if (intel_crtc->config.dither) |
if (intel_crtc->config->dither) |
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
|
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
val |= PIPECONF_INTERLACED_ILK; |
else |
val |= PIPECONF_PROGRESSIVE; |
|
if (intel_crtc->config.limited_color_range) |
if (intel_crtc->config->limited_color_range) |
val |= PIPECONF_COLOR_RANGE_SELECT; |
|
I915_WRITE(PIPECONF(pipe), val); |
7217,7 → 8651,7 |
* consideration. |
*/ |
|
if (intel_crtc->config.limited_color_range) |
if (intel_crtc->config->limited_color_range) |
coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
|
/* |
7241,7 → 8675,7 |
if (INTEL_INFO(dev)->gen > 6) { |
uint16_t postoff = 0; |
|
if (intel_crtc->config.limited_color_range) |
if (intel_crtc->config->limited_color_range) |
postoff = (16 * (1 << 12) / 255) & 0x1fff; |
|
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
7252,7 → 8686,7 |
} else { |
uint32_t mode = CSC_MODE_YUV_TO_RGB; |
|
if (intel_crtc->config.limited_color_range) |
if (intel_crtc->config->limited_color_range) |
mode |= CSC_BLACK_SCREEN_OFFSET; |
|
I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
7265,15 → 8699,15 |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
uint32_t val; |
|
val = 0; |
|
if (IS_HASWELL(dev) && intel_crtc->config.dither) |
if (IS_HASWELL(dev) && intel_crtc->config->dither) |
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
|
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
val |= PIPECONF_INTERLACED_ILK; |
else |
val |= PIPECONF_PROGRESSIVE; |
7287,7 → 8721,7 |
if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
val = 0; |
|
switch (intel_crtc->config.pipe_bpp) { |
switch (intel_crtc->config->pipe_bpp) { |
case 18: |
val |= PIPEMISC_DITHER_6_BPC; |
break; |
7305,7 → 8739,7 |
BUG(); |
} |
|
if (intel_crtc->config.dither) |
if (intel_crtc->config->dither) |
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
|
I915_WRITE(PIPEMISC(pipe), val); |
7313,6 → 8747,7 |
} |
|
static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
struct intel_crtc_state *crtc_state, |
intel_clock_t *clock, |
bool *has_reduced_clock, |
intel_clock_t *reduced_clock) |
7319,41 → 8754,24 |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int refclk; |
const intel_limit_t *limit; |
bool ret, is_lvds = false; |
bool ret; |
|
is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
refclk = ironlake_get_refclk(crtc_state); |
|
refclk = ironlake_get_refclk(crtc); |
|
/* |
* Returns a set of divisors for the desired target clock with the given |
* refclk, or FALSE. The returned values represent the clock equation: |
* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
*/ |
limit = intel_limit(intel_crtc, refclk); |
ret = dev_priv->display.find_dpll(limit, intel_crtc, |
intel_crtc->new_config->port_clock, |
limit = intel_limit(crtc_state, refclk); |
ret = dev_priv->display.find_dpll(limit, crtc_state, |
crtc_state->port_clock, |
refclk, NULL, clock); |
if (!ret) |
return false; |
|
if (is_lvds && dev_priv->lvds_downclock_avail) { |
/* |
* Ensure we match the reduced clock's P to the target clock. |
* If the clocks don't match, we can't switch the display clock |
* by using the FP0/FP1. In such case we will disable the LVDS |
* downclock feature. |
*/ |
*has_reduced_clock = |
dev_priv->display.find_dpll(limit, intel_crtc, |
dev_priv->lvds_downclock, |
refclk, clock, |
reduced_clock); |
} |
|
return true; |
} |
|
7374,6 → 8792,7 |
} |
|
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
struct intel_crtc_state *crtc_state, |
u32 *fp, |
intel_clock_t *reduced_clock, u32 *fp2) |
{ |
7380,16 → 8799,21 |
struct drm_crtc *crtc = &intel_crtc->base; |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_encoder *intel_encoder; |
struct drm_atomic_state *state = crtc_state->base.state; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
struct intel_encoder *encoder; |
uint32_t dpll; |
int factor, num_connectors = 0; |
int factor, num_connectors = 0, i; |
bool is_lvds = false, is_sdvo = false; |
|
for_each_intel_encoder(dev, intel_encoder) { |
if (intel_encoder->new_crtc != to_intel_crtc(crtc)) |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != crtc_state->base.crtc) |
continue; |
|
switch (intel_encoder->type) { |
encoder = to_intel_encoder(connector_state->best_encoder); |
|
switch (encoder->type) { |
case INTEL_OUTPUT_LVDS: |
is_lvds = true; |
break; |
7411,10 → 8835,10 |
dev_priv->vbt.lvds_ssc_freq == 100000) || |
(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
factor = 25; |
} else if (intel_crtc->new_config->sdvo_tv_clock) |
} else if (crtc_state->sdvo_tv_clock) |
factor = 20; |
|
if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor)) |
if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
*fp |= FP_CB_TUNE; |
|
if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7427,20 → 8851,20 |
else |
dpll |= DPLLB_MODE_DAC_SERIAL; |
|
dpll |= (intel_crtc->new_config->pixel_multiplier - 1) |
dpll |= (crtc_state->pixel_multiplier - 1) |
<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
|
if (is_sdvo) |
dpll |= DPLL_SDVO_HIGH_SPEED; |
if (intel_crtc->new_config->has_dp_encoder) |
if (crtc_state->has_dp_encoder) |
dpll |= DPLL_SDVO_HIGH_SPEED; |
|
/* compute bitmask from p1 value */ |
dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
/* also FPA1 */ |
dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
|
switch (intel_crtc->new_config->dpll.p2) { |
switch (crtc_state->dpll.p2) { |
case 5: |
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
break; |
7463,7 → 8887,8 |
return dpll | DPLL_VCO_ENABLE; |
} |
|
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) |
static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->base.dev; |
intel_clock_t clock, reduced_clock; |
7472,44 → 8897,47 |
bool is_lvds = false; |
struct intel_shared_dpll *pll; |
|
memset(&crtc_state->dpll_hw_state, 0, |
sizeof(crtc_state->dpll_hw_state)); |
|
is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
|
WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
|
ok = ironlake_compute_clocks(&crtc->base, &clock, |
ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
&has_reduced_clock, &reduced_clock); |
if (!ok && !crtc->new_config->clock_set) { |
if (!ok && !crtc_state->clock_set) { |
DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
return -EINVAL; |
} |
/* Compat-code for transition, will disappear. */ |
if (!crtc->new_config->clock_set) { |
crtc->new_config->dpll.n = clock.n; |
crtc->new_config->dpll.m1 = clock.m1; |
crtc->new_config->dpll.m2 = clock.m2; |
crtc->new_config->dpll.p1 = clock.p1; |
crtc->new_config->dpll.p2 = clock.p2; |
if (!crtc_state->clock_set) { |
crtc_state->dpll.n = clock.n; |
crtc_state->dpll.m1 = clock.m1; |
crtc_state->dpll.m2 = clock.m2; |
crtc_state->dpll.p1 = clock.p1; |
crtc_state->dpll.p2 = clock.p2; |
} |
|
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
if (crtc->new_config->has_pch_encoder) { |
fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); |
if (crtc_state->has_pch_encoder) { |
fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
if (has_reduced_clock) |
fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
|
dpll = ironlake_compute_dpll(crtc, |
dpll = ironlake_compute_dpll(crtc, crtc_state, |
&fp, &reduced_clock, |
has_reduced_clock ? &fp2 : NULL); |
|
crtc->new_config->dpll_hw_state.dpll = dpll; |
crtc->new_config->dpll_hw_state.fp0 = fp; |
crtc_state->dpll_hw_state.dpll = dpll; |
crtc_state->dpll_hw_state.fp0 = fp; |
if (has_reduced_clock) |
crtc->new_config->dpll_hw_state.fp1 = fp2; |
crtc_state->dpll_hw_state.fp1 = fp2; |
else |
crtc->new_config->dpll_hw_state.fp1 = fp; |
crtc_state->dpll_hw_state.fp1 = fp; |
|
pll = intel_get_shared_dpll(crtc); |
pll = intel_get_shared_dpll(crtc, crtc_state); |
if (pll == NULL) { |
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
pipe_name(crtc->pipe)); |
7517,7 → 8945,7 |
} |
} |
|
if (is_lvds && has_reduced_clock && i915.powersave) |
if (is_lvds && has_reduced_clock) |
crtc->lowfreq_avail = true; |
else |
crtc->lowfreq_avail = false; |
7563,7 → 8991,7 |
* registers are not unnecessarily read). |
*/ |
if (m2_n2 && INTEL_INFO(dev)->gen < 8 && |
crtc->config.has_drrs) { |
crtc->config->has_drrs) { |
m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); |
m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) |
7584,9 → 9012,9 |
} |
|
void intel_dp_get_m_n(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
if (crtc->config.has_pch_encoder) |
if (pipe_config->has_pch_encoder) |
intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
else |
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
7595,7 → 9023,7 |
} |
|
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
&pipe_config->fdi_m_n, NULL); |
7602,23 → 9030,123 |
} |
|
static void skylake_get_pfit_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t tmp; |
struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
uint32_t ps_ctrl = 0; |
int id = -1; |
int i; |
|
tmp = I915_READ(PS_CTL(crtc->pipe)); |
|
if (tmp & PS_ENABLE) { |
/* find scaler attached to this pipe */ |
for (i = 0; i < crtc->num_scalers; i++) { |
ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); |
if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { |
id = i; |
pipe_config->pch_pfit.enabled = true; |
pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); |
pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); |
pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); |
pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); |
break; |
} |
} |
|
scaler_state->scaler_id = id; |
if (id >= 0) { |
scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); |
} else { |
scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); |
} |
} |
|
static void |
skylake_get_initial_plane_config(struct intel_crtc *crtc, |
struct intel_initial_plane_config *plane_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 val, base, offset, stride_mult, tiling; |
int pipe = crtc->pipe; |
int fourcc, pixel_format; |
unsigned int aligned_height; |
struct drm_framebuffer *fb; |
struct intel_framebuffer *intel_fb; |
|
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
if (!intel_fb) { |
DRM_DEBUG_KMS("failed to alloc fb\n"); |
return; |
} |
|
fb = &intel_fb->base; |
|
val = I915_READ(PLANE_CTL(pipe, 0)); |
if (!(val & PLANE_CTL_ENABLE)) |
goto error; |
|
pixel_format = val & PLANE_CTL_FORMAT_MASK; |
fourcc = skl_format_to_fourcc(pixel_format, |
val & PLANE_CTL_ORDER_RGBX, |
val & PLANE_CTL_ALPHA_MASK); |
fb->pixel_format = fourcc; |
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
|
tiling = val & PLANE_CTL_TILED_MASK; |
switch (tiling) { |
case PLANE_CTL_TILED_LINEAR: |
fb->modifier[0] = DRM_FORMAT_MOD_NONE; |
break; |
case PLANE_CTL_TILED_X: |
plane_config->tiling = I915_TILING_X; |
fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
break; |
case PLANE_CTL_TILED_Y: |
fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; |
break; |
case PLANE_CTL_TILED_YF: |
fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; |
break; |
default: |
MISSING_CASE(tiling); |
goto error; |
} |
|
base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
plane_config->base = base; |
|
offset = I915_READ(PLANE_OFFSET(pipe, 0)); |
|
val = I915_READ(PLANE_SIZE(pipe, 0)); |
fb->height = ((val >> 16) & 0xfff) + 1; |
fb->width = ((val >> 0) & 0x1fff) + 1; |
|
val = I915_READ(PLANE_STRIDE(pipe, 0)); |
stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
fb->pixel_format); |
// fb->pitches[0] = (val & 0x3ff) * stride_mult; |
fb->pitches[0] = 2560*4; |
|
aligned_height = intel_fb_align_height(dev, fb->height, |
fb->pixel_format, |
fb->modifier[0]); |
|
// plane_config->size = fb->pitches[0] * aligned_height; |
plane_config->size = i915_fbsize*1024*1024; |
|
DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
pipe_name(pipe), fb->width, fb->height, |
fb->bits_per_pixel, base, fb->pitches[0], |
plane_config->size); |
|
plane_config->fb = intel_fb; |
return; |
|
error: |
kfree(fb); |
} |
|
static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
7641,68 → 9169,79 |
} |
} |
|
static void ironlake_get_plane_config(struct intel_crtc *crtc, |
struct intel_plane_config *plane_config) |
static void |
ironlake_get_initial_plane_config(struct intel_crtc *crtc, |
struct intel_initial_plane_config *plane_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 val, base, offset; |
int pipe = crtc->pipe, plane = crtc->plane; |
int pipe = crtc->pipe; |
int fourcc, pixel_format; |
int aligned_height; |
unsigned int aligned_height; |
struct drm_framebuffer *fb; |
struct intel_framebuffer *intel_fb; |
|
crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
if (!crtc->base.primary->fb) { |
val = I915_READ(DSPCNTR(pipe)); |
if (!(val & DISPLAY_PLANE_ENABLE)) |
return; |
|
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
if (!intel_fb) { |
DRM_DEBUG_KMS("failed to alloc fb\n"); |
return; |
} |
|
val = I915_READ(DSPCNTR(plane)); |
fb = &intel_fb->base; |
|
if (INTEL_INFO(dev)->gen >= 4) |
if (val & DISPPLANE_TILED) |
plane_config->tiled = true; |
if (INTEL_INFO(dev)->gen >= 4) { |
if (val & DISPPLANE_TILED) { |
plane_config->tiling = I915_TILING_X; |
fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
} |
} |
|
pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
fourcc = intel_format_to_fourcc(pixel_format); |
crtc->base.primary->fb->pixel_format = fourcc; |
crtc->base.primary->fb->bits_per_pixel = |
drm_format_plane_cpp(fourcc, 0) * 8; |
fourcc = i9xx_format_to_fourcc(pixel_format); |
fb->pixel_format = fourcc; |
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; |
|
base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
offset = I915_READ(DSPOFFSET(plane)); |
offset = I915_READ(DSPOFFSET(pipe)); |
} else { |
if (plane_config->tiled) |
offset = I915_READ(DSPTILEOFF(plane)); |
if (plane_config->tiling) |
offset = I915_READ(DSPTILEOFF(pipe)); |
else |
offset = I915_READ(DSPLINOFF(plane)); |
offset = I915_READ(DSPLINOFF(pipe)); |
} |
plane_config->base = base; |
|
val = I915_READ(PIPESRC(pipe)); |
crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; |
fb->width = ((val >> 16) & 0xfff) + 1; |
fb->height = ((val >> 0) & 0xfff) + 1; |
|
val = I915_READ(DSPSTRIDE(pipe)); |
crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
// fb->pitches[0] = val & 0xffffffc0; |
fb->pitches[0] = 2560*4; |
|
aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
plane_config->tiled); |
aligned_height = intel_fb_align_height(dev, fb->height, |
fb->pixel_format, |
fb->modifier[0]); |
|
plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
aligned_height); |
// plane_config->size = fb->pitches[0] * aligned_height; |
plane_config->size = i915_fbsize*1024*1024; |
|
DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
pipe, plane, crtc->base.primary->fb->width, |
crtc->base.primary->fb->height, |
crtc->base.primary->fb->bits_per_pixel, base, |
crtc->base.primary->fb->pitches[0], |
DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
pipe_name(pipe), fb->width, fb->height, |
fb->bits_per_pixel, base, fb->pitches[0], |
plane_config->size); |
|
plane_config->fb = intel_fb; |
} |
|
static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
7789,24 → 9328,24 |
struct intel_crtc *crtc; |
|
for_each_intel_crtc(dev, crtc) |
WARN(crtc->active, "CRTC for pipe %c enabled\n", |
I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
pipe_name(crtc->pipe)); |
|
WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); |
I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
"CPU PWM1 enabled\n"); |
if (IS_HASWELL(dev)) |
WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
"CPU PWM2 enabled\n"); |
WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
"PCH PWM1 enabled\n"); |
WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
"Utility pin enabled\n"); |
WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
|
/* |
* In theory we can still leave IRQs enabled, as long as only the HPD |
7814,7 → 9353,7 |
* gen-specific and since we only disable LCPLL after we fully disable |
* the interrupts, the check below should be enough. |
*/ |
WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
} |
|
static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7912,19 → 9451,8 |
/* |
* Make sure we're not on PC8 state before disabling PC8, otherwise |
* we'll hang the machine. To prevent PC8 state, just enable force_wake. |
* |
* The other problem is that hsw_restore_lcpll() is called as part of |
* the runtime PM resume sequence, so we can't just call |
* gen6_gt_force_wake_get() because that function calls |
* intel_runtime_pm_get(), and we can't change the runtime PM refcount |
* while we are on the resume sequence. So to solve this problem we have |
* to call special forcewake code that doesn't touch runtime PM and |
* doesn't enable the forcewake delayed work. |
*/ |
spin_lock_irq(&dev_priv->uncore.lock); |
if (dev_priv->uncore.forcewake_count++ == 0) |
dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
spin_unlock_irq(&dev_priv->uncore.lock); |
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
|
if (val & LCPLL_POWER_DOWN_ALLOW) { |
val &= ~LCPLL_POWER_DOWN_ALLOW; |
7954,11 → 9482,8 |
DRM_ERROR("Switching back to LCPLL failed\n"); |
} |
|
/* See the big comment above. */ |
spin_lock_irq(&dev_priv->uncore.lock); |
if (--dev_priv->uncore.forcewake_count == 0) |
dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
spin_unlock_irq(&dev_priv->uncore.lock); |
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
intel_update_cdclk(dev_priv->dev); |
} |
|
/* |
7991,7 → 9516,7 |
|
DRM_DEBUG_KMS("Enabling package C8+\n"); |
|
if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
if (HAS_PCH_LPT_LP(dev)) { |
val = I915_READ(SOUTH_DSPCLK_GATE_D); |
val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
8011,7 → 9536,7 |
hsw_restore_lcpll(dev_priv); |
lpt_init_pch_refclk(dev); |
|
if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
if (HAS_PCH_LPT_LP(dev)) { |
val = I915_READ(SOUTH_DSPCLK_GATE_D); |
val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
8020,9 → 9545,166 |
intel_prepare_ddi(dev); |
} |
|
static int haswell_crtc_compute_clock(struct intel_crtc *crtc) |
static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
{ |
if (!intel_ddi_pll_select(crtc)) |
struct drm_device *dev = old_state->dev; |
unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
|
broxton_set_cdclk(dev, req_cdclk); |
} |
|
/* compute the max rate for new configuration */ |
static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
{ |
struct intel_crtc *intel_crtc; |
struct intel_crtc_state *crtc_state; |
int max_pixel_rate = 0; |
|
for_each_intel_crtc(state->dev, intel_crtc) { |
int pixel_rate; |
|
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
if (IS_ERR(crtc_state)) |
return PTR_ERR(crtc_state); |
|
if (!crtc_state->base.enable) |
continue; |
|
pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
|
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
|
max_pixel_rate = max(max_pixel_rate, pixel_rate); |
} |
|
return max_pixel_rate; |
} |
|
static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t val, data; |
int ret; |
|
if (WARN((I915_READ(LCPLL_CTL) & |
(LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | |
LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | |
LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | |
LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, |
"trying to change cdclk frequency with cdclk not enabled\n")) |
return; |
|
mutex_lock(&dev_priv->rps.hw_lock); |
ret = sandybridge_pcode_write(dev_priv, |
BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); |
mutex_unlock(&dev_priv->rps.hw_lock); |
if (ret) { |
DRM_ERROR("failed to inform pcode about cdclk change\n"); |
return; |
} |
|
val = I915_READ(LCPLL_CTL); |
val |= LCPLL_CD_SOURCE_FCLK; |
I915_WRITE(LCPLL_CTL, val); |
|
if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
DRM_ERROR("Switching to FCLK failed\n"); |
|
val = I915_READ(LCPLL_CTL); |
val &= ~LCPLL_CLK_FREQ_MASK; |
|
switch (cdclk) { |
case 450000: |
val |= LCPLL_CLK_FREQ_450; |
data = 0; |
break; |
case 540000: |
val |= LCPLL_CLK_FREQ_54O_BDW; |
data = 1; |
break; |
case 337500: |
val |= LCPLL_CLK_FREQ_337_5_BDW; |
data = 2; |
break; |
case 675000: |
val |= LCPLL_CLK_FREQ_675_BDW; |
data = 3; |
break; |
default: |
WARN(1, "invalid cdclk frequency\n"); |
return; |
} |
|
I915_WRITE(LCPLL_CTL, val); |
|
val = I915_READ(LCPLL_CTL); |
val &= ~LCPLL_CD_SOURCE_FCLK; |
I915_WRITE(LCPLL_CTL, val); |
|
if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
DRM_ERROR("Switching back to LCPLL failed\n"); |
|
mutex_lock(&dev_priv->rps.hw_lock); |
sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
mutex_unlock(&dev_priv->rps.hw_lock); |
|
intel_update_cdclk(dev); |
|
WARN(cdclk != dev_priv->cdclk_freq, |
"cdclk requested %d kHz but got %d kHz\n", |
cdclk, dev_priv->cdclk_freq); |
} |
|
static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
{ |
struct drm_i915_private *dev_priv = to_i915(state->dev); |
int max_pixclk = ilk_max_pixel_rate(state); |
int cdclk; |
|
/* |
* FIXME should also account for plane ratio |
* once 64bpp pixel formats are supported. |
*/ |
if (max_pixclk > 540000) |
cdclk = 675000; |
else if (max_pixclk > 450000) |
cdclk = 540000; |
else if (max_pixclk > 337500) |
cdclk = 450000; |
else |
cdclk = 337500; |
|
/* |
* FIXME move the cdclk caclulation to |
* compute_config() so we can fail gracegully. |
*/ |
if (cdclk > dev_priv->max_cdclk_freq) { |
DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
cdclk, dev_priv->max_cdclk_freq); |
cdclk = dev_priv->max_cdclk_freq; |
} |
|
to_intel_atomic_state(state)->cdclk = cdclk; |
|
return 0; |
} |
|
static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
{ |
struct drm_device *dev = old_state->dev; |
unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
|
broadwell_set_cdclk(dev, req_cdclk); |
} |
|
static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
struct intel_crtc_state *crtc_state) |
{ |
if (!intel_ddi_pll_select(crtc, crtc_state)) |
return -EINVAL; |
|
crtc->lowfreq_avail = false; |
8030,16 → 9712,47 |
return 0; |
} |
|
static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
enum port port, |
struct intel_crtc_state *pipe_config) |
{ |
switch (port) { |
case PORT_A: |
pipe_config->ddi_pll_sel = SKL_DPLL0; |
pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
break; |
case PORT_B: |
pipe_config->ddi_pll_sel = SKL_DPLL1; |
pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; |
break; |
case PORT_C: |
pipe_config->ddi_pll_sel = SKL_DPLL2; |
pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; |
break; |
default: |
DRM_ERROR("Incorrect port type\n"); |
} |
} |
|
static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
enum port port, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
u32 temp; |
u32 temp, dpll_ctl1; |
|
temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); |
pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); |
|
switch (pipe_config->ddi_pll_sel) { |
case SKL_DPLL0: |
/* |
* On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part |
* of the shared DPLL framework and thus needs to be read out |
* separately |
*/ |
dpll_ctl1 = I915_READ(DPLL_CTRL1); |
pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; |
break; |
case SKL_DPLL1: |
pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; |
break; |
8054,7 → 9767,7 |
|
static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
enum port port, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
|
8065,11 → 9778,13 |
case PORT_CLK_SEL_WRPLL2: |
pipe_config->shared_dpll = DPLL_ID_WRPLL2; |
break; |
case PORT_CLK_SEL_SPLL: |
pipe_config->shared_dpll = DPLL_ID_SPLL; |
} |
} |
|
static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
8083,6 → 9798,8 |
|
if (IS_SKYLAKE(dev)) |
skylake_get_ddi_pll(dev_priv, port, pipe_config); |
else if (IS_BROXTON(dev)) |
bxt_get_ddi_pll(dev_priv, port, pipe_config); |
else |
haswell_get_ddi_pll(dev_priv, port, pipe_config); |
|
8111,7 → 9828,7 |
} |
|
static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
8159,9 → 9876,19 |
|
intel_get_pipe_timings(crtc, pipe_config); |
|
if (INTEL_INFO(dev)->gen >= 9) { |
skl_init_scalers(dev, crtc, pipe_config); |
} |
|
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
|
if (INTEL_INFO(dev)->gen >= 9) { |
pipe_config->scaler_state.scaler_id = -1; |
pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); |
} |
|
if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
if (IS_SKYLAKE(dev)) |
if (INTEL_INFO(dev)->gen >= 9) |
skylake_get_pfit_config(crtc, pipe_config); |
else |
ironlake_get_pfit_config(crtc, pipe_config); |
8181,7 → 9908,7 |
return true; |
} |
|
static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
8188,9 → 9915,9 |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
uint32_t cntl = 0, size = 0; |
|
if (base) { |
unsigned int width = intel_crtc->cursor_width; |
unsigned int height = intel_crtc->cursor_height; |
if (on) { |
unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
unsigned int height = intel_crtc->base.cursor->state->crtc_h; |
unsigned int stride = roundup_pow_of_two(width) * 4; |
|
switch (stride) { |
8221,13 → 9948,13 |
/* On these chipsets we can only modify the base/size/stride |
* whilst the cursor is disabled. |
*/ |
I915_WRITE(_CURACNTR, 0); |
POSTING_READ(_CURACNTR); |
I915_WRITE(CURCNTR(PIPE_A), 0); |
POSTING_READ(CURCNTR(PIPE_A)); |
intel_crtc->cursor_cntl = 0; |
} |
|
if (intel_crtc->cursor_base != base) { |
I915_WRITE(_CURABASE, base); |
I915_WRITE(CURBASE(PIPE_A), base); |
intel_crtc->cursor_base = base; |
} |
|
8237,24 → 9964,23 |
} |
|
if (intel_crtc->cursor_cntl != cntl) { |
I915_WRITE(_CURACNTR, cntl); |
POSTING_READ(_CURACNTR); |
I915_WRITE(CURCNTR(PIPE_A), cntl); |
POSTING_READ(CURCNTR(PIPE_A)); |
intel_crtc->cursor_cntl = cntl; |
} |
} |
|
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int pipe = intel_crtc->pipe; |
uint32_t cntl; |
uint32_t cntl = 0; |
|
cntl = 0; |
if (base) { |
if (on) { |
cntl = MCURSOR_GAMMA_ENABLE; |
switch (intel_crtc->cursor_width) { |
switch (intel_crtc->base.cursor->state->crtc_w) { |
case 64: |
cntl |= CURSOR_MODE_64_ARGB_AX; |
break; |
8265,16 → 9991,16 |
cntl |= CURSOR_MODE_256_ARGB_AX; |
break; |
default: |
WARN_ON(1); |
MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
return; |
} |
cntl |= pipe << 28; /* Connect to correct pipe */ |
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
if (HAS_DDI(dev)) |
cntl |= CURSOR_PIPE_CSC_ENABLE; |
} |
|
if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) |
if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
cntl |= CURSOR_ROTATE_180; |
|
if (intel_crtc->cursor_cntl != cntl) { |
8298,22 → 10024,22 |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int pipe = intel_crtc->pipe; |
int x = crtc->cursor_x; |
int y = crtc->cursor_y; |
struct drm_plane_state *cursor_state = crtc->cursor->state; |
int x = cursor_state->crtc_x; |
int y = cursor_state->crtc_y; |
u32 base = 0, pos = 0; |
|
if (on) |
base = intel_crtc->cursor_addr; |
|
if (x >= intel_crtc->config.pipe_src_w) |
base = 0; |
if (x >= intel_crtc->config->pipe_src_w) |
on = false; |
|
if (y >= intel_crtc->config.pipe_src_h) |
base = 0; |
if (y >= intel_crtc->config->pipe_src_h) |
on = false; |
|
if (x < 0) { |
if (x + intel_crtc->cursor_width <= 0) |
base = 0; |
if (x + cursor_state->crtc_w <= 0) |
on = false; |
|
pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
x = -x; |
8321,8 → 10047,8 |
pos |= x << CURSOR_X_SHIFT; |
|
if (y < 0) { |
if (y + intel_crtc->cursor_height <= 0) |
base = 0; |
if (y + cursor_state->crtc_h <= 0) |
on = false; |
|
pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
y = -y; |
8329,22 → 10055,19 |
} |
pos |= y << CURSOR_Y_SHIFT; |
|
if (base == 0 && intel_crtc->cursor_base == 0) |
return; |
|
I915_WRITE(CURPOS(pipe), pos); |
|
/* ILK+ do this automagically */ |
if (HAS_GMCH_DISPLAY(dev) && |
to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) { |
base += (intel_crtc->cursor_height * |
intel_crtc->cursor_width - 1) * 4; |
crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
base += (cursor_state->crtc_h * |
cursor_state->crtc_w - 1) * 4; |
} |
|
if (IS_845G(dev) || IS_I865G(dev)) |
i845_update_cursor(crtc, base); |
i845_update_cursor(crtc, base, on); |
else |
i9xx_update_cursor(crtc, base); |
i9xx_update_cursor(crtc, base, on); |
} |
|
static bool cursor_size_ok(struct drm_device *dev, |
8384,109 → 10107,6 |
return true; |
} |
|
static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, |
struct drm_i915_gem_object *obj, |
uint32_t width, uint32_t height) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = to_i915(dev); |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
unsigned old_width; |
uint32_t addr; |
int ret; |
|
/* if we want to turn off the cursor ignore width and height */ |
if (!obj) { |
DRM_DEBUG_KMS("cursor off\n"); |
addr = 0; |
mutex_lock(&dev->struct_mutex); |
goto finish; |
} |
|
/* we only need to pin inside GTT if cursor is non-phy */ |
mutex_lock(&dev->struct_mutex); |
if (!INTEL_INFO(dev)->cursor_needs_physical) { |
unsigned alignment; |
|
/* |
* Global gtt pte registers are special registers which actually |
* forward writes to a chunk of system memory. Which means that |
* there is no risk that the register values disappear as soon |
* as we call intel_runtime_pm_put(), so it is correct to wrap |
* only the pin/unpin/fence and not more. |
*/ |
intel_runtime_pm_get(dev_priv); |
|
/* Note that the w/a also requires 2 PTE of padding following |
* the bo. We currently fill all unused PTE with the shadow |
* page and so we should always have valid PTE following the |
* cursor preventing the VT-d warning. |
*/ |
alignment = 0; |
if (need_vtd_wa(dev)) |
alignment = 64*1024; |
|
ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
if (ret) { |
DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
intel_runtime_pm_put(dev_priv); |
goto fail_locked; |
} |
|
ret = i915_gem_object_put_fence(obj); |
if (ret) { |
DRM_DEBUG_KMS("failed to release fence for cursor"); |
intel_runtime_pm_put(dev_priv); |
goto fail_unpin; |
} |
|
addr = i915_gem_obj_ggtt_offset(obj); |
|
intel_runtime_pm_put(dev_priv); |
} else { |
int align = IS_I830(dev) ? 16 * 1024 : 256; |
ret = 1;//i915_gem_object_attach_phys(obj, align); |
if (ret) { |
DRM_DEBUG_KMS("failed to attach phys object\n"); |
goto fail_locked; |
} |
addr = obj->phys_handle->busaddr; |
} |
|
finish: |
if (intel_crtc->cursor_bo) { |
if (!INTEL_INFO(dev)->cursor_needs_physical) |
i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
} |
|
i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
INTEL_FRONTBUFFER_CURSOR(pipe)); |
mutex_unlock(&dev->struct_mutex); |
|
old_width = intel_crtc->cursor_width; |
|
intel_crtc->cursor_addr = addr; |
intel_crtc->cursor_bo = obj; |
intel_crtc->cursor_width = width; |
intel_crtc->cursor_height = height; |
|
if (intel_crtc->active) { |
if (old_width != width) |
intel_update_watermarks(crtc); |
intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
|
intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
} |
|
return 0; |
fail_unpin: |
i915_gem_object_unpin_from_display_plane(obj); |
fail_locked: |
mutex_unlock(&dev->struct_mutex); |
return ret; |
} |
|
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
u16 *blue, uint32_t start, uint32_t size) |
{ |
8591,7 → 10211,7 |
mode_fits_in_fbdev(struct drm_device *dev, |
struct drm_display_mode *mode) |
{ |
#ifdef CONFIG_DRM_I915_FBDEV |
#ifdef CONFIG_DRM_FBDEV_EMULATION |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *obj; |
struct drm_framebuffer *fb; |
8619,6 → 10239,41 |
#endif |
} |
|
static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
struct drm_framebuffer *fb, |
int x, int y) |
{ |
struct drm_plane_state *plane_state; |
int hdisplay, vdisplay; |
int ret; |
|
plane_state = drm_atomic_get_plane_state(state, crtc->primary); |
if (IS_ERR(plane_state)) |
return PTR_ERR(plane_state); |
|
if (mode) |
drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
else |
hdisplay = vdisplay = 0; |
|
ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); |
if (ret) |
return ret; |
drm_atomic_set_fb_for_plane(plane_state, fb); |
plane_state->crtc_x = 0; |
plane_state->crtc_y = 0; |
plane_state->crtc_w = hdisplay; |
plane_state->crtc_h = vdisplay; |
plane_state->src_x = x << 16; |
plane_state->src_y = y << 16; |
plane_state->src_w = hdisplay << 16; |
plane_state->src_h = vdisplay << 16; |
|
return 0; |
} |
|
bool intel_get_load_detect_pipe(struct drm_connector *connector, |
struct drm_display_mode *mode, |
struct intel_load_detect_pipe *old, |
8633,6 → 10288,9 |
struct drm_device *dev = encoder->dev; |
struct drm_framebuffer *fb; |
struct drm_mode_config *config = &dev->mode_config; |
struct drm_atomic_state *state = NULL; |
struct drm_connector_state *connector_state; |
struct intel_crtc_state *crtc_state; |
int ret, i = -1; |
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8642,7 → 10300,7 |
retry: |
ret = drm_modeset_lock(&config->connection_mutex, ctx); |
if (ret) |
goto fail_unlock; |
goto fail; |
|
/* |
* Algorithm gets a little messy: |
8660,10 → 10318,10 |
|
ret = drm_modeset_lock(&crtc->mutex, ctx); |
if (ret) |
goto fail_unlock; |
goto fail; |
ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
if (ret) |
goto fail_unlock; |
goto fail; |
|
old->dpms_mode = connector->dpms; |
old->load_detect_temp = false; |
8680,11 → 10338,8 |
i++; |
if (!(encoder->possible_crtcs & (1 << i))) |
continue; |
if (possible_crtc->enabled) |
if (possible_crtc->state->enable) |
continue; |
/* This can occur when applying the pipe A quirk on resume. */ |
if (to_intel_crtc(possible_crtc)->new_enabled) |
continue; |
|
crtc = possible_crtc; |
break; |
8695,25 → 10350,44 |
*/ |
if (!crtc) { |
DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
goto fail_unlock; |
goto fail; |
} |
|
ret = drm_modeset_lock(&crtc->mutex, ctx); |
if (ret) |
goto fail_unlock; |
goto fail; |
ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
if (ret) |
goto fail_unlock; |
intel_encoder->new_crtc = to_intel_crtc(crtc); |
to_intel_connector(connector)->new_encoder = intel_encoder; |
goto fail; |
|
intel_crtc = to_intel_crtc(crtc); |
intel_crtc->new_enabled = true; |
intel_crtc->new_config = &intel_crtc->config; |
old->dpms_mode = connector->dpms; |
old->load_detect_temp = true; |
old->release_fb = NULL; |
|
state = drm_atomic_state_alloc(dev); |
if (!state) |
return false; |
|
state->acquire_ctx = ctx; |
|
connector_state = drm_atomic_get_connector_state(state, connector); |
if (IS_ERR(connector_state)) { |
ret = PTR_ERR(connector_state); |
goto fail; |
} |
|
connector_state->crtc = crtc; |
connector_state->best_encoder = &intel_encoder->base; |
|
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
if (IS_ERR(crtc_state)) { |
ret = PTR_ERR(crtc_state); |
goto fail; |
} |
|
crtc_state->base.active = crtc_state->base.enable = true; |
|
if (!mode) |
mode = &load_detect_mode; |
|
8736,12 → 10410,19 |
goto fail; |
} |
|
if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
if (ret) |
goto fail; |
|
drm_mode_copy(&crtc_state->base.mode, mode); |
|
if (drm_atomic_commit(state)) { |
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
if (old->release_fb) |
old->release_fb->funcs->destroy(old->release_fb); |
goto fail; |
} |
crtc->primary->crtc = crtc; |
|
/* let the connector get through one full cycle before testing */ |
intel_wait_for_vblank(dev, intel_crtc->pipe); |
8748,12 → 10429,9 |
return true; |
|
fail: |
intel_crtc->new_enabled = crtc->enabled; |
if (intel_crtc->new_enabled) |
intel_crtc->new_config = &intel_crtc->config; |
else |
intel_crtc->new_config = NULL; |
fail_unlock: |
drm_atomic_state_free(state); |
state = NULL; |
|
if (ret == -EDEADLK) { |
drm_modeset_backoff(ctx); |
goto retry; |
8763,13 → 10441,19 |
} |
|
void intel_release_load_detect_pipe(struct drm_connector *connector, |
struct intel_load_detect_pipe *old) |
struct intel_load_detect_pipe *old, |
struct drm_modeset_acquire_ctx *ctx) |
{ |
struct drm_device *dev = connector->dev; |
struct intel_encoder *intel_encoder = |
intel_attached_encoder(connector); |
struct drm_encoder *encoder = &intel_encoder->base; |
struct drm_crtc *crtc = encoder->crtc; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_atomic_state *state; |
struct drm_connector_state *connector_state; |
struct intel_crtc_state *crtc_state; |
int ret; |
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
connector->base.id, connector->name, |
8776,12 → 10460,34 |
encoder->base.id, encoder->name); |
|
if (old->load_detect_temp) { |
to_intel_connector(connector)->new_encoder = NULL; |
intel_encoder->new_crtc = NULL; |
intel_crtc->new_enabled = false; |
intel_crtc->new_config = NULL; |
intel_set_mode(crtc, NULL, 0, 0, NULL); |
state = drm_atomic_state_alloc(dev); |
if (!state) |
goto fail; |
|
state->acquire_ctx = ctx; |
|
connector_state = drm_atomic_get_connector_state(state, connector); |
if (IS_ERR(connector_state)) |
goto fail; |
|
crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
if (IS_ERR(crtc_state)) |
goto fail; |
|
connector_state->best_encoder = NULL; |
connector_state->crtc = NULL; |
|
crtc_state->base.enable = crtc_state->base.active = false; |
|
ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
0, 0); |
if (ret) |
goto fail; |
|
ret = drm_atomic_commit(state); |
if (ret) |
goto fail; |
|
if (old->release_fb) { |
drm_framebuffer_unregister_private(old->release_fb); |
drm_framebuffer_unreference(old->release_fb); |
8793,10 → 10499,15 |
/* Switch crtc and encoder back off if necessary */ |
if (old->dpms_mode != DRM_MODE_DPMS_ON) |
connector->funcs->dpms(connector, old->dpms_mode); |
|
return; |
fail: |
DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); |
drm_atomic_state_free(state); |
} |
|
static int i9xx_pll_refclk(struct drm_device *dev, |
const struct intel_crtc_config *pipe_config) |
const struct intel_crtc_state *pipe_config) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 dpll = pipe_config->dpll_hw_state.dpll; |
8813,7 → 10524,7 |
|
/* Returns the clock of the currently programmed mode of the given pipe. */ |
static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
8821,6 → 10532,7 |
u32 dpll = pipe_config->dpll_hw_state.dpll; |
u32 fp; |
intel_clock_t clock; |
int port_clock; |
int refclk = i9xx_pll_refclk(dev, pipe_config); |
|
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
8861,9 → 10573,9 |
} |
|
if (IS_PINEVIEW(dev)) |
pineview_clock(refclk, &clock); |
port_clock = pnv_calc_dpll_params(refclk, &clock); |
else |
i9xx_clock(refclk, &clock); |
port_clock = i9xx_calc_dpll_params(refclk, &clock); |
} else { |
u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
8889,7 → 10601,7 |
clock.p2 = 2; |
} |
|
i9xx_clock(refclk, &clock); |
port_clock = i9xx_calc_dpll_params(refclk, &clock); |
} |
|
/* |
8897,7 → 10609,7 |
* port_clock to compute adjusted_mode.crtc_clock in the |
* encoder's get_config() function. |
*/ |
pipe_config->port_clock = clock.dot; |
pipe_config->port_clock = port_clock; |
} |
|
int intel_dotclock_calculate(int link_freq, |
8920,7 → 10632,7 |
} |
|
static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
|
8933,7 → 10645,7 |
* agree once we know their relationship in the encoder's |
* get_config() function. |
*/ |
pipe_config->adjusted_mode.crtc_clock = |
pipe_config->base.adjusted_mode.crtc_clock = |
intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
&pipe_config->fdi_m_n); |
} |
8944,9 → 10656,9 |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
struct drm_display_mode *mode; |
struct intel_crtc_config pipe_config; |
struct intel_crtc_state pipe_config; |
int htot = I915_READ(HTOTAL(cpu_transcoder)); |
int hsync = I915_READ(HSYNC(cpu_transcoder)); |
int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
8986,42 → 10698,6 |
return mode; |
} |
|
static void intel_decrease_pllclock(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
if (!HAS_GMCH_DISPLAY(dev)) |
return; |
|
if (!dev_priv->lvds_downclock_avail) |
return; |
|
/* |
* Since this is called by a timer, we should never get here in |
* the manual case. |
*/ |
if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
int pipe = intel_crtc->pipe; |
int dpll_reg = DPLL(pipe); |
int dpll; |
|
DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
|
assert_panel_unlocked(dev_priv, pipe); |
|
dpll = I915_READ(dpll_reg); |
dpll |= DISPLAY_RATE_SELECT_FPA1; |
I915_WRITE(dpll_reg, dpll); |
intel_wait_for_vblank(dev, pipe); |
dpll = I915_READ(dpll_reg); |
if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
} |
|
} |
|
void intel_mark_busy(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
9031,6 → 10707,8 |
|
intel_runtime_pm_get(dev_priv); |
i915_update_gfx_val(dev_priv); |
if (INTEL_INFO(dev)->gen >= 6) |
gen6_rps_busy(dev_priv); |
dev_priv->mm.busy = true; |
} |
|
9037,7 → 10715,6 |
void intel_mark_idle(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *crtc; |
|
if (!dev_priv->mm.busy) |
return; |
9044,20 → 10721,9 |
|
dev_priv->mm.busy = false; |
|
if (!i915.powersave) |
goto out; |
|
for_each_crtc(dev, crtc) { |
if (!crtc->primary->fb) |
continue; |
|
intel_decrease_pllclock(crtc); |
} |
|
if (INTEL_INFO(dev)->gen >= 6) |
gen6_rps_idle(dev->dev_private); |
|
out: |
intel_runtime_pm_put(dev_priv); |
} |
|
9087,21 → 10753,23 |
{ |
struct intel_unpin_work *work = |
container_of(__work, struct intel_unpin_work, work); |
struct drm_device *dev = work->crtc->dev; |
enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
struct drm_device *dev = crtc->base.dev; |
struct drm_plane *primary = crtc->base.primary; |
|
mutex_lock(&dev->struct_mutex); |
intel_unpin_fb_obj(work->old_fb_obj); |
intel_unpin_fb_obj(work->old_fb, primary->state); |
drm_gem_object_unreference(&work->pending_flip_obj->base); |
drm_gem_object_unreference(&work->old_fb_obj->base); |
|
intel_update_fbc(dev); |
if (work->flip_queued_req) |
i915_gem_request_assign(&work->flip_queued_req, NULL); |
mutex_unlock(&dev->struct_mutex); |
|
intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
drm_framebuffer_unreference(work->old_fb); |
|
BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
atomic_dec(&crtc->unpin_work_count); |
|
kfree(work); |
} |
9195,7 → 10863,7 |
*/ |
return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == |
crtc->unpin_work->gtt_offset && |
g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), |
g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
crtc->unpin_work->flip_count); |
} |
|
9221,11 → 10889,11 |
spin_unlock_irqrestore(&dev->event_lock, flags); |
} |
|
static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
{ |
/* Ensure that the work item is consistent when activating it ... */ |
smp_wmb(); |
atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
atomic_set(&work->pending, INTEL_FLIP_PENDING); |
/* and that it is marked active as soon as the irq could fire. */ |
smp_wmb(); |
} |
9234,14 → 10902,15 |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct intel_engine_cs *ring, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
struct intel_engine_cs *ring = req->ring; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
u32 flip_mask; |
int ret; |
|
ret = intel_ring_begin(ring, 6); |
ret = intel_ring_begin(req, 6); |
if (ret) |
return ret; |
|
9260,8 → 10929,7 |
intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
intel_ring_emit(ring, 0); /* aux display base address, unused */ |
|
intel_mark_page_flip_active(intel_crtc); |
__intel_ring_advance(ring); |
intel_mark_page_flip_active(intel_crtc->unpin_work); |
return 0; |
} |
|
9269,14 → 10937,15 |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct intel_engine_cs *ring, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
struct intel_engine_cs *ring = req->ring; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
u32 flip_mask; |
int ret; |
|
ret = intel_ring_begin(ring, 6); |
ret = intel_ring_begin(req, 6); |
if (ret) |
return ret; |
|
9292,8 → 10961,7 |
intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
intel_ring_emit(ring, MI_NOOP); |
|
intel_mark_page_flip_active(intel_crtc); |
__intel_ring_advance(ring); |
intel_mark_page_flip_active(intel_crtc->unpin_work); |
return 0; |
} |
|
9301,15 → 10969,16 |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct intel_engine_cs *ring, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
struct intel_engine_cs *ring = req->ring; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
uint32_t pf, pipesrc; |
int ret; |
|
ret = intel_ring_begin(ring, 4); |
ret = intel_ring_begin(req, 4); |
if (ret) |
return ret; |
|
9331,8 → 11000,7 |
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
intel_ring_emit(ring, pf | pipesrc); |
|
intel_mark_page_flip_active(intel_crtc); |
__intel_ring_advance(ring); |
intel_mark_page_flip_active(intel_crtc->unpin_work); |
return 0; |
} |
|
9340,15 → 11008,16 |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct intel_engine_cs *ring, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
struct intel_engine_cs *ring = req->ring; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
uint32_t pf, pipesrc; |
int ret; |
|
ret = intel_ring_begin(ring, 4); |
ret = intel_ring_begin(req, 4); |
if (ret) |
return ret; |
|
9367,8 → 11036,7 |
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
intel_ring_emit(ring, pf | pipesrc); |
|
intel_mark_page_flip_active(intel_crtc); |
__intel_ring_advance(ring); |
intel_mark_page_flip_active(intel_crtc->unpin_work); |
return 0; |
} |
|
9376,9 → 11044,10 |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct intel_engine_cs *ring, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
struct intel_engine_cs *ring = req->ring; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
uint32_t plane_bit = 0; |
int len, ret; |
9420,11 → 11089,11 |
* then do the cacheline alignment, and finally emit the |
* MI_DISPLAY_FLIP. |
*/ |
ret = intel_ring_cacheline_align(ring); |
ret = intel_ring_cacheline_align(req); |
if (ret) |
return ret; |
|
ret = intel_ring_begin(ring, len); |
ret = intel_ring_begin(req, len); |
if (ret) |
return ret; |
|
9444,10 → 11113,10 |
DERRMR_PIPEB_PRI_FLIP_DONE | |
DERRMR_PIPEC_PRI_FLIP_DONE)); |
if (IS_GEN8(dev)) |
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | |
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
MI_SRM_LRM_GLOBAL_GTT); |
else |
intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
MI_SRM_LRM_GLOBAL_GTT); |
intel_ring_emit(ring, DERRMR); |
intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
9462,12 → 11131,154 |
intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
intel_ring_emit(ring, (MI_NOOP)); |
|
intel_mark_page_flip_active(intel_crtc); |
__intel_ring_advance(ring); |
intel_mark_page_flip_active(intel_crtc->unpin_work); |
return 0; |
} |
|
static int intel_default_queue_flip(struct drm_device *dev, |
static bool use_mmio_flip(struct intel_engine_cs *ring, |
struct drm_i915_gem_object *obj) |
{ |
/* |
* This is not being used for older platforms, because |
* non-availability of flip done interrupt forces us to use |
* CS flips. Older platforms derive flip done using some clever |
* tricks involving the flip_pending status bits and vblank irqs. |
* So using MMIO flips there would disrupt this mechanism. |
*/ |
|
if (ring == NULL) |
return true; |
|
if (INTEL_INFO(ring->dev)->gen < 5) |
return false; |
|
if (i915.use_mmio_flip < 0) |
return false; |
else if (i915.use_mmio_flip > 0) |
return true; |
else if (i915.enable_execlists) |
return true; |
else |
return ring != i915_gem_request_get_ring(obj->last_write_req); |
} |
|
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
struct intel_unpin_work *work) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
const enum pipe pipe = intel_crtc->pipe; |
u32 ctl, stride; |
|
ctl = I915_READ(PLANE_CTL(pipe, 0)); |
ctl &= ~PLANE_CTL_TILED_MASK; |
switch (fb->modifier[0]) { |
case DRM_FORMAT_MOD_NONE: |
break; |
case I915_FORMAT_MOD_X_TILED: |
ctl |= PLANE_CTL_TILED_X; |
break; |
case I915_FORMAT_MOD_Y_TILED: |
ctl |= PLANE_CTL_TILED_Y; |
break; |
case I915_FORMAT_MOD_Yf_TILED: |
ctl |= PLANE_CTL_TILED_YF; |
break; |
default: |
MISSING_CASE(fb->modifier[0]); |
} |
|
/* |
* The stride is either expressed as a multiple of 64 bytes chunks for |
* linear buffers or in number of tiles for tiled buffers. |
*/ |
stride = fb->pitches[0] / |
intel_fb_stride_alignment(dev, fb->modifier[0], |
fb->pixel_format); |
|
/* |
* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on |
* PLANE_SURF updates, the update is then guaranteed to be atomic. |
*/ |
I915_WRITE(PLANE_CTL(pipe, 0), ctl); |
I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
|
I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
POSTING_READ(PLANE_SURF(pipe, 0)); |
} |
|
static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
struct intel_unpin_work *work) |
{ |
struct drm_device *dev = intel_crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_framebuffer *intel_fb = |
to_intel_framebuffer(intel_crtc->base.primary->fb); |
struct drm_i915_gem_object *obj = intel_fb->obj; |
u32 dspcntr; |
u32 reg; |
|
reg = DSPCNTR(intel_crtc->plane); |
dspcntr = I915_READ(reg); |
|
if (obj->tiling_mode != I915_TILING_NONE) |
dspcntr |= DISPPLANE_TILED; |
else |
dspcntr &= ~DISPPLANE_TILED; |
|
I915_WRITE(reg, dspcntr); |
|
I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
POSTING_READ(DSPSURF(intel_crtc->plane)); |
} |
|
/* |
* XXX: This is the temporary way to update the plane registers until we get |
* around to using the usual plane update functions for MMIO flips |
*/ |
static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
{ |
struct intel_crtc *crtc = mmio_flip->crtc; |
struct intel_unpin_work *work; |
|
spin_lock_irq(&crtc->base.dev->event_lock); |
work = crtc->unpin_work; |
spin_unlock_irq(&crtc->base.dev->event_lock); |
if (work == NULL) |
return; |
|
intel_mark_page_flip_active(work); |
|
intel_pipe_update_start(crtc); |
|
if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
skl_do_mmio_flip(crtc, work); |
else |
/* use_mmio_flip() retricts MMIO flips to ilk+ */ |
ilk_do_mmio_flip(crtc, work); |
|
intel_pipe_update_end(crtc); |
} |
|
static void intel_mmio_flip_work_func(struct work_struct *work) |
{ |
struct intel_mmio_flip *mmio_flip = |
container_of(work, struct intel_mmio_flip, work); |
|
if (mmio_flip->req) { |
WARN_ON(__i915_wait_request(mmio_flip->req, |
mmio_flip->crtc->reset_counter, |
false, NULL, |
&mmio_flip->i915->rps.mmioflips)); |
i915_gem_request_unreference__unlocked(mmio_flip->req); |
} |
|
intel_do_mmio_flip(mmio_flip); |
kfree(mmio_flip); |
} |
|
static int intel_queue_mmio_flip(struct drm_device *dev, |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
9474,9 → 11285,100 |
struct intel_engine_cs *ring, |
uint32_t flags) |
{ |
struct intel_mmio_flip *mmio_flip; |
|
mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); |
if (mmio_flip == NULL) |
return -ENOMEM; |
|
mmio_flip->i915 = to_i915(dev); |
mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
mmio_flip->crtc = to_intel_crtc(crtc); |
|
INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
schedule_work(&mmio_flip->work); |
|
return 0; |
} |
|
static int intel_default_queue_flip(struct drm_device *dev, |
struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_i915_gem_object *obj, |
struct drm_i915_gem_request *req, |
uint32_t flags) |
{ |
return -ENODEV; |
} |
|
static bool __intel_pageflip_stall_check(struct drm_device *dev, |
struct drm_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_unpin_work *work = intel_crtc->unpin_work; |
u32 addr; |
|
if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) |
return true; |
|
if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
return false; |
|
if (!work->enable_stall_check) |
return false; |
|
if (work->flip_ready_vblank == 0) { |
if (work->flip_queued_req && |
!i915_gem_request_completed(work->flip_queued_req, true)) |
return false; |
|
work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
} |
|
if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
return false; |
|
/* Potential stall - if we see that the flip has happened, |
* assume a missed interrupt. */ |
if (INTEL_INFO(dev)->gen >= 4) |
addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); |
else |
addr = I915_READ(DSPADDR(intel_crtc->plane)); |
|
/* There is a potential issue here with a false positive after a flip |
* to the same address. We could address this by checking for a |
* non-incrementing frame counter. |
*/ |
return addr == work->gtt_offset; |
} |
|
void intel_check_page_flip(struct drm_device *dev, int pipe) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_unpin_work *work; |
|
WARN_ON(!in_interrupt()); |
|
if (crtc == NULL) |
return; |
|
spin_lock(&dev->event_lock); |
work = intel_crtc->unpin_work; |
if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { |
WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
page_flip_completed(intel_crtc); |
work = NULL; |
} |
if (work != NULL && |
drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) |
intel_queue_rps_boost_for_request(dev, work->flip_queued_req); |
spin_unlock(&dev->event_lock); |
} |
|
static int intel_crtc_page_flip(struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_pending_vblank_event *event, |
9487,9 → 11389,12 |
struct drm_framebuffer *old_fb = crtc->primary->fb; |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_plane *primary = crtc->primary; |
enum pipe pipe = intel_crtc->pipe; |
struct intel_unpin_work *work; |
struct intel_engine_cs *ring; |
bool mmio_flip; |
struct drm_i915_gem_request *request = NULL; |
int ret; |
|
/* |
9522,7 → 11427,7 |
|
work->event = event; |
work->crtc = crtc; |
work->old_fb_obj = intel_fb_obj(old_fb); |
work->old_fb = old_fb; |
INIT_WORK(&work->work, intel_unpin_work_fn); |
|
ret = drm_crtc_vblank_get(crtc); |
9553,33 → 11458,34 |
if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
flush_workqueue(dev_priv->wq); |
|
ret = i915_mutex_lock_interruptible(dev); |
if (ret) |
goto cleanup; |
|
/* Reference the objects for the scheduled work. */ |
drm_gem_object_reference(&work->old_fb_obj->base); |
drm_framebuffer_reference(work->old_fb); |
drm_gem_object_reference(&obj->base); |
|
crtc->primary->fb = fb; |
update_state_fb(crtc->primary); |
|
work->pending_flip_obj = obj; |
|
ret = i915_mutex_lock_interruptible(dev); |
if (ret) |
goto cleanup; |
|
atomic_inc(&intel_crtc->unpin_work_count); |
intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
|
if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
|
if (IS_VALLEYVIEW(dev)) { |
ring = &dev_priv->ring[BCS]; |
if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
/* vlv: DISPLAY_FLIP fails to change tiling */ |
ring = NULL; |
} else if (IS_IVYBRIDGE(dev)) { |
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
ring = &dev_priv->ring[BCS]; |
} else if (INTEL_INFO(dev)->gen >= 7) { |
ring = obj->ring; |
ring = i915_gem_request_get_ring(obj->last_write_req); |
if (ring == NULL || ring->id != RCS) |
ring = &dev_priv->ring[BCS]; |
} else { |
9586,55 → 11492,78 |
ring = &dev_priv->ring[RCS]; |
} |
|
ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring); |
mmio_flip = use_mmio_flip(ring, obj); |
|
/* When using CS flips, we want to emit semaphores between rings. |
* However, when using mmio flips we will create a task to do the |
* synchronisation, so all we want here is to pin the framebuffer |
* into the display plane and skip any waits. |
*/ |
ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
crtc->primary->state, |
mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
if (ret) |
goto cleanup_pending; |
|
work->gtt_offset = |
i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; |
work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
obj, 0); |
work->gtt_offset += intel_crtc->dspaddr_offset; |
|
if (use_mmio_flip(ring, obj)) { |
if (mmio_flip) { |
ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
page_flip_flags); |
if (ret) |
goto cleanup_unpin; |
|
work->flip_queued_seqno = obj->last_write_seqno; |
work->flip_queued_ring = obj->ring; |
i915_gem_request_assign(&work->flip_queued_req, |
obj->last_write_req); |
} else { |
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
if (!request) { |
ret = i915_gem_request_alloc(ring, ring->default_context, &request); |
if (ret) |
goto cleanup_unpin; |
} |
|
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
page_flip_flags); |
if (ret) |
goto cleanup_unpin; |
|
work->flip_queued_seqno = intel_ring_get_seqno(ring); |
work->flip_queued_ring = ring; |
i915_gem_request_assign(&work->flip_queued_req, request); |
} |
|
work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe); |
if (request) |
i915_add_request_no_flush(request); |
|
work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
work->enable_stall_check = true; |
|
i915_gem_track_fb(work->old_fb_obj, obj, |
INTEL_FRONTBUFFER_PRIMARY(pipe)); |
|
intel_disable_fbc(dev); |
intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
to_intel_plane(primary)->frontbuffer_bit); |
mutex_unlock(&dev->struct_mutex); |
|
intel_fbc_disable_crtc(intel_crtc); |
intel_frontbuffer_flip_prepare(dev, |
to_intel_plane(primary)->frontbuffer_bit); |
|
trace_i915_flip_request(intel_crtc->plane, obj); |
|
return 0; |
|
cleanup_unpin: |
intel_unpin_fb_obj(obj); |
intel_unpin_fb_obj(fb, crtc->primary->state); |
cleanup_pending: |
if (request) |
i915_gem_request_cancel(request); |
atomic_dec(&intel_crtc->unpin_work_count); |
mutex_unlock(&dev->struct_mutex); |
cleanup: |
crtc->primary->fb = old_fb; |
drm_gem_object_unreference(&work->old_fb_obj->base); |
drm_gem_object_unreference(&obj->base); |
mutex_unlock(&dev->struct_mutex); |
update_state_fb(crtc->primary); |
|
cleanup: |
drm_gem_object_unreference_unlocked(&obj->base); |
drm_framebuffer_unreference(work->old_fb); |
|
spin_lock_irq(&dev->event_lock); |
intel_crtc->unpin_work = NULL; |
spin_unlock_irq(&dev->event_lock); |
9644,9 → 11573,35 |
kfree(work); |
|
if (ret == -EIO) { |
struct drm_atomic_state *state; |
struct drm_plane_state *plane_state; |
|
out_hang: |
// intel_crtc_wait_for_pending_flips(crtc); |
ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); |
state = drm_atomic_state_alloc(dev); |
if (!state) |
return -ENOMEM; |
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
|
retry: |
plane_state = drm_atomic_get_plane_state(state, primary); |
ret = PTR_ERR_OR_ZERO(plane_state); |
if (!ret) { |
drm_atomic_set_fb_for_plane(plane_state, fb); |
|
ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); |
if (!ret) |
ret = drm_atomic_commit(state); |
} |
|
if (ret == -EDEADLK) { |
drm_modeset_backoff(state->acquire_ctx); |
drm_atomic_state_clear(state); |
goto retry; |
} |
|
if (ret) |
drm_atomic_state_free(state); |
|
if (ret == 0 && event) { |
spin_lock_irq(&dev->event_lock); |
drm_send_vblank_event(dev, pipe, event); |
9657,72 → 11612,294 |
} |
#endif |
|
static struct drm_crtc_helper_funcs intel_helper_funcs = { |
.mode_set_base_atomic = intel_pipe_set_base_atomic, |
.load_lut = intel_crtc_load_lut, |
}; |
|
/** |
* intel_modeset_update_staged_output_state |
* intel_wm_need_update - Check whether watermarks need updating |
* @plane: drm plane |
* @state: new plane state |
* |
* Updates the staged output configuration state, e.g. after we've read out the |
* current hw state. |
* Check current plane state versus the new one to determine whether |
* watermarks need to be recalculated. |
* |
* Returns true or false. |
*/ |
static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
static bool intel_wm_need_update(struct drm_plane *plane, |
struct drm_plane_state *state) |
{ |
struct intel_crtc *crtc; |
struct intel_encoder *encoder; |
struct intel_connector *connector; |
/* Update watermarks on tiling changes. */ |
if (!plane->state->fb || !state->fb || |
plane->state->fb->modifier[0] != state->fb->modifier[0] || |
plane->state->rotation != state->rotation) |
return true; |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
connector->new_encoder = |
to_intel_encoder(connector->base.encoder); |
if (plane->state->crtc_w != state->crtc_w) |
return true; |
|
return false; |
} |
|
for_each_intel_encoder(dev, encoder) { |
encoder->new_crtc = |
to_intel_crtc(encoder->base.crtc); |
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
struct drm_plane_state *plane_state) |
{ |
struct drm_crtc *crtc = crtc_state->crtc; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct drm_plane *plane = plane_state->plane; |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_plane_state *old_plane_state = |
to_intel_plane_state(plane->state); |
int idx = intel_crtc->base.base.id, ret; |
int i = drm_plane_index(plane); |
bool mode_changed = needs_modeset(crtc_state); |
bool was_crtc_enabled = crtc->state->active; |
bool is_crtc_enabled = crtc_state->active; |
|
bool turn_off, turn_on, visible, was_visible; |
struct drm_framebuffer *fb = plane_state->fb; |
|
if (crtc_state && INTEL_INFO(dev)->gen >= 9 && |
plane->type != DRM_PLANE_TYPE_CURSOR) { |
ret = skl_update_scaler_plane( |
to_intel_crtc_state(crtc_state), |
to_intel_plane_state(plane_state)); |
if (ret) |
return ret; |
} |
|
for_each_intel_crtc(dev, crtc) { |
crtc->new_enabled = crtc->base.enabled; |
/* |
* Disabling a plane is always okay; we just need to update |
* fb tracking in a special way since cleanup_fb() won't |
* get called by the plane helpers. |
*/ |
if (old_plane_state->base.fb && !fb) |
intel_crtc->atomic.disabled_planes |= 1 << i; |
|
if (crtc->new_enabled) |
crtc->new_config = &crtc->config; |
else |
crtc->new_config = NULL; |
was_visible = old_plane_state->visible; |
visible = to_intel_plane_state(plane_state)->visible; |
|
if (!was_crtc_enabled && WARN_ON(was_visible)) |
was_visible = false; |
|
if (!is_crtc_enabled && WARN_ON(visible)) |
visible = false; |
|
if (!was_visible && !visible) |
return 0; |
|
turn_off = was_visible && (!visible || mode_changed); |
turn_on = visible && (!was_visible || mode_changed); |
|
DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, |
plane->base.id, fb ? fb->base.id : -1); |
|
DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", |
plane->base.id, was_visible, visible, |
turn_off, turn_on, mode_changed); |
|
if (turn_on) { |
intel_crtc->atomic.update_wm_pre = true; |
/* must disable cxsr around plane enable/disable */ |
if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
intel_crtc->atomic.disable_cxsr = true; |
/* to potentially re-enable cxsr */ |
intel_crtc->atomic.wait_vblank = true; |
intel_crtc->atomic.update_wm_post = true; |
} |
} else if (turn_off) { |
intel_crtc->atomic.update_wm_post = true; |
/* must disable cxsr around plane enable/disable */ |
if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
if (is_crtc_enabled) |
intel_crtc->atomic.wait_vblank = true; |
intel_crtc->atomic.disable_cxsr = true; |
} |
} else if (intel_wm_need_update(plane, plane_state)) { |
intel_crtc->atomic.update_wm_pre = true; |
} |
|
/** |
* intel_modeset_commit_output_state |
if (visible || was_visible) |
intel_crtc->atomic.fb_bits |= |
to_intel_plane(plane)->frontbuffer_bit; |
|
switch (plane->type) { |
case DRM_PLANE_TYPE_PRIMARY: |
intel_crtc->atomic.wait_for_flips = true; |
intel_crtc->atomic.pre_disable_primary = turn_off; |
intel_crtc->atomic.post_enable_primary = turn_on; |
|
if (turn_off) { |
/* |
* FIXME: Actually if we will still have any other |
* plane enabled on the pipe we could let IPS enabled |
* still, but for now lets consider that when we make |
* primary invisible by setting DSPCNTR to 0 on |
* update_primary_plane function IPS needs to be |
* disable. |
*/ |
intel_crtc->atomic.disable_ips = true; |
|
intel_crtc->atomic.disable_fbc = true; |
} |
|
/* |
* FBC does not work on some platforms for rotated |
* planes, so disable it when rotation is not 0 and |
* update it when rotation is set back to 0. |
* |
* This function copies the stage display pipe configuration to the real one. |
* FIXME: This is redundant with the fbc update done in |
* the primary plane enable function except that that |
* one is done too late. We eventually need to unify |
* this. |
*/ |
static void intel_modeset_commit_output_state(struct drm_device *dev) |
|
if (visible && |
INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
dev_priv->fbc.crtc == intel_crtc && |
plane_state->rotation != BIT(DRM_ROTATE_0)) |
intel_crtc->atomic.disable_fbc = true; |
|
/* |
* BDW signals flip done immediately if the plane |
* is disabled, even if the plane enable is already |
* armed to occur at the next vblank :( |
*/ |
if (turn_on && IS_BROADWELL(dev)) |
intel_crtc->atomic.wait_vblank = true; |
|
intel_crtc->atomic.update_fbc |= visible || mode_changed; |
break; |
case DRM_PLANE_TYPE_CURSOR: |
break; |
case DRM_PLANE_TYPE_OVERLAY: |
if (turn_off && !mode_changed) { |
intel_crtc->atomic.wait_vblank = true; |
intel_crtc->atomic.update_sprite_watermarks |= |
1 << i; |
} |
} |
return 0; |
} |
|
static bool encoders_cloneable(const struct intel_encoder *a, |
const struct intel_encoder *b) |
{ |
struct intel_crtc *crtc; |
/* masks could be asymmetric, so check both ways */ |
return a == b || (a->cloneable & (1 << b->type) && |
b->cloneable & (1 << a->type)); |
} |
|
static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
struct intel_crtc *crtc, |
struct intel_encoder *encoder) |
{ |
struct intel_encoder *source_encoder; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
int i; |
|
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != &crtc->base) |
continue; |
|
source_encoder = |
to_intel_encoder(connector_state->best_encoder); |
if (!encoders_cloneable(encoder, source_encoder)) |
return false; |
} |
|
return true; |
} |
|
static bool check_encoder_cloning(struct drm_atomic_state *state, |
struct intel_crtc *crtc) |
{ |
struct intel_encoder *encoder; |
struct intel_connector *connector; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
int i; |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
connector->base.encoder = &connector->new_encoder->base; |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != &crtc->base) |
continue; |
|
encoder = to_intel_encoder(connector_state->best_encoder); |
if (!check_single_encoder_cloning(state, crtc, encoder)) |
return false; |
} |
|
for_each_intel_encoder(dev, encoder) { |
encoder->base.crtc = &encoder->new_crtc->base; |
return true; |
} |
|
for_each_intel_crtc(dev, crtc) { |
crtc->base.enabled = crtc->new_enabled; |
static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
struct drm_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_crtc_state *pipe_config = |
to_intel_crtc_state(crtc_state); |
struct drm_atomic_state *state = crtc_state->state; |
int ret; |
bool mode_changed = needs_modeset(crtc_state); |
|
if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { |
DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
return -EINVAL; |
} |
|
if (mode_changed && !crtc_state->active) |
intel_crtc->atomic.update_wm_post = true; |
|
if (mode_changed && crtc_state->enable && |
dev_priv->display.crtc_compute_clock && |
!WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { |
ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
pipe_config); |
if (ret) |
return ret; |
} |
|
ret = 0; |
if (INTEL_INFO(dev)->gen >= 9) { |
if (mode_changed) |
ret = skl_update_scaler_crtc(pipe_config); |
|
if (!ret) |
ret = intel_atomic_setup_scalers(dev, intel_crtc, |
pipe_config); |
} |
|
return ret; |
} |
|
static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
.mode_set_base_atomic = intel_pipe_set_base_atomic, |
.load_lut = intel_crtc_load_lut, |
.atomic_begin = intel_begin_crtc_commit, |
.atomic_flush = intel_finish_crtc_commit, |
.atomic_check = intel_crtc_atomic_check, |
}; |
|
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
{ |
struct intel_connector *connector; |
|
for_each_intel_connector(dev, connector) { |
if (connector->base.encoder) { |
connector->base.state->best_encoder = |
connector->base.encoder; |
connector->base.state->crtc = |
connector->base.encoder->crtc; |
} else { |
connector->base.state->best_encoder = NULL; |
connector->base.state->crtc = NULL; |
} |
} |
} |
|
static void |
connected_sink_compute_bpp(struct intel_connector *connector, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
int bpp = pipe_config->pipe_bpp; |
|
9748,59 → 11925,33 |
|
static int |
compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
struct drm_framebuffer *fb, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_connector *connector; |
int bpp; |
struct drm_atomic_state *state; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
int bpp, i; |
|
switch (fb->pixel_format) { |
case DRM_FORMAT_C8: |
bpp = 8*3; /* since we go through a colormap */ |
break; |
case DRM_FORMAT_XRGB1555: |
case DRM_FORMAT_ARGB1555: |
/* checked in intel_framebuffer_init already */ |
if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
return -EINVAL; |
case DRM_FORMAT_RGB565: |
bpp = 6*3; /* min is 18bpp */ |
break; |
case DRM_FORMAT_XBGR8888: |
case DRM_FORMAT_ABGR8888: |
/* checked in intel_framebuffer_init already */ |
if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
return -EINVAL; |
case DRM_FORMAT_XRGB8888: |
case DRM_FORMAT_ARGB8888: |
if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
bpp = 10*3; |
else if (INTEL_INFO(dev)->gen >= 5) |
bpp = 12*3; |
else |
bpp = 8*3; |
break; |
case DRM_FORMAT_XRGB2101010: |
case DRM_FORMAT_ARGB2101010: |
case DRM_FORMAT_XBGR2101010: |
case DRM_FORMAT_ABGR2101010: |
/* checked in intel_framebuffer_init already */ |
if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
return -EINVAL; |
bpp = 10*3; |
break; |
/* TODO: gen4+ supports 16 bpc floating point, too. */ |
default: |
DRM_DEBUG_KMS("unsupported depth\n"); |
return -EINVAL; |
} |
|
|
pipe_config->pipe_bpp = bpp; |
|
state = pipe_config->base.state; |
|
/* Clamp display bpp to EDID value */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
if (!connector->new_encoder || |
connector->new_encoder->new_crtc != crtc) |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != &crtc->base) |
continue; |
|
connected_sink_compute_bpp(connector, pipe_config); |
connected_sink_compute_bpp(to_intel_connector(connector), |
pipe_config); |
} |
|
return bpp; |
9818,12 → 11969,18 |
} |
|
static void intel_dump_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config, |
struct intel_crtc_state *pipe_config, |
const char *context) |
{ |
DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
context, pipe_name(crtc->pipe)); |
struct drm_device *dev = crtc->base.dev; |
struct drm_plane *plane; |
struct intel_plane *intel_plane; |
struct intel_plane_state *state; |
struct drm_framebuffer *fb; |
|
DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, |
context, pipe_config, pipe_name(crtc->pipe)); |
|
DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
pipe_config->pipe_bpp, pipe_config->dither); |
9833,14 → 11990,16 |
pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
pipe_config->fdi_m_n.tu); |
DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
pipe_config->has_dp_encoder, |
pipe_config->lane_count, |
pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
pipe_config->dp_m_n.tu); |
|
DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
pipe_config->has_dp_encoder, |
pipe_config->lane_count, |
pipe_config->dp_m2_n2.gmch_m, |
pipe_config->dp_m2_n2.gmch_n, |
pipe_config->dp_m2_n2.link_m, |
9852,13 → 12011,17 |
pipe_config->has_infoframe); |
|
DRM_DEBUG_KMS("requested mode:\n"); |
drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
drm_mode_debug_printmodeline(&pipe_config->base.mode); |
DRM_DEBUG_KMS("adjusted mode:\n"); |
drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); |
DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
crtc->num_scalers, |
pipe_config->scaler_state.scaler_users, |
pipe_config->scaler_state.scaler_id); |
DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
pipe_config->gmch_pfit.control, |
pipe_config->gmch_pfit.pgm_ratios, |
9869,52 → 12032,83 |
pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
} |
|
static bool encoders_cloneable(const struct intel_encoder *a, |
const struct intel_encoder *b) |
{ |
/* masks could be asymmetric, so check both ways */ |
return a == b || (a->cloneable & (1 << b->type) && |
b->cloneable & (1 << a->type)); |
if (IS_BROXTON(dev)) { |
DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
pipe_config->ddi_pll_sel, |
pipe_config->dpll_hw_state.ebb0, |
pipe_config->dpll_hw_state.ebb4, |
pipe_config->dpll_hw_state.pll0, |
pipe_config->dpll_hw_state.pll1, |
pipe_config->dpll_hw_state.pll2, |
pipe_config->dpll_hw_state.pll3, |
pipe_config->dpll_hw_state.pll6, |
pipe_config->dpll_hw_state.pll8, |
pipe_config->dpll_hw_state.pll9, |
pipe_config->dpll_hw_state.pll10, |
pipe_config->dpll_hw_state.pcsdw12); |
} else if (IS_SKYLAKE(dev)) { |
DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
pipe_config->ddi_pll_sel, |
pipe_config->dpll_hw_state.ctrl1, |
pipe_config->dpll_hw_state.cfgcr1, |
pipe_config->dpll_hw_state.cfgcr2); |
} else if (HAS_DDI(dev)) { |
DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
pipe_config->ddi_pll_sel, |
pipe_config->dpll_hw_state.wrpll, |
pipe_config->dpll_hw_state.spll); |
} else { |
DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " |
"fp0: 0x%x, fp1: 0x%x\n", |
pipe_config->dpll_hw_state.dpll, |
pipe_config->dpll_hw_state.dpll_md, |
pipe_config->dpll_hw_state.fp0, |
pipe_config->dpll_hw_state.fp1); |
} |
|
static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
struct intel_encoder *encoder) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_encoder *source_encoder; |
DRM_DEBUG_KMS("planes on this crtc\n"); |
list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
intel_plane = to_intel_plane(plane); |
if (intel_plane->pipe != crtc->pipe) |
continue; |
|
for_each_intel_encoder(dev, source_encoder) { |
if (source_encoder->new_crtc != crtc) |
state = to_intel_plane_state(plane->state); |
fb = state->base.fb; |
if (!fb) { |
DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " |
"disabled, scaler_id = %d\n", |
plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
plane->base.id, intel_plane->pipe, |
(crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, |
drm_plane_index(plane), state->scaler_id); |
continue; |
|
if (!encoders_cloneable(encoder, source_encoder)) |
return false; |
} |
|
return true; |
DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", |
plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", |
plane->base.id, intel_plane->pipe, |
crtc->base.primary == plane ? 0 : intel_plane->plane + 1, |
drm_plane_index(plane)); |
DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", |
fb->base.id, fb->width, fb->height, fb->pixel_format); |
DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", |
state->scaler_id, |
state->src.x1 >> 16, state->src.y1 >> 16, |
drm_rect_width(&state->src) >> 16, |
drm_rect_height(&state->src) >> 16, |
state->dst.x1, state->dst.y1, |
drm_rect_width(&state->dst), drm_rect_height(&state->dst)); |
} |
|
static bool check_encoder_cloning(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_encoder *encoder; |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->new_crtc != crtc) |
continue; |
|
if (!check_single_encoder_cloning(crtc, encoder)) |
return false; |
} |
|
return true; |
} |
|
static bool check_digital_port_conflicts(struct drm_device *dev) |
static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
{ |
struct intel_connector *connector; |
struct drm_device *dev = state->dev; |
struct drm_connector *connector; |
unsigned int used_ports = 0; |
|
/* |
9922,15 → 12116,21 |
* list to detect the problem on ddi platforms |
* where there's just one encoder per digital port. |
*/ |
list_for_each_entry(connector, |
&dev->mode_config.connector_list, base.head) { |
struct intel_encoder *encoder = connector->new_encoder; |
drm_for_each_connector(connector, dev) { |
struct drm_connector_state *connector_state; |
struct intel_encoder *encoder; |
|
if (!encoder) |
connector_state = drm_atomic_get_existing_connector_state(state, connector); |
if (!connector_state) |
connector_state = connector->state; |
|
if (!connector_state->best_encoder) |
continue; |
|
WARN_ON(!encoder->new_crtc); |
encoder = to_intel_encoder(connector_state->best_encoder); |
|
WARN_ON(!connector_state->crtc); |
|
switch (encoder->type) { |
unsigned int port_mask; |
case INTEL_OUTPUT_UNKNOWN: |
9954,37 → 12154,54 |
return true; |
} |
|
static struct intel_crtc_config * |
intel_modeset_pipe_config(struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_display_mode *mode) |
static void |
clear_intel_crtc_state(struct intel_crtc_state *crtc_state) |
{ |
struct drm_device *dev = crtc->dev; |
struct intel_encoder *encoder; |
struct intel_crtc_config *pipe_config; |
int plane_bpp, ret = -EINVAL; |
bool retry = true; |
struct drm_crtc_state tmp_state; |
struct intel_crtc_scaler_state scaler_state; |
struct intel_dpll_hw_state dpll_hw_state; |
enum intel_dpll_id shared_dpll; |
uint32_t ddi_pll_sel; |
bool force_thru; |
|
if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
return ERR_PTR(-EINVAL); |
} |
/* FIXME: before the switch to atomic started, a new pipe_config was |
* kzalloc'd. Code that depends on any field being zero should be |
* fixed, so that the crtc_state can be safely duplicated. For now, |
* only fields that are know to not cause problems are preserved. */ |
|
if (!check_digital_port_conflicts(dev)) { |
DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
return ERR_PTR(-EINVAL); |
tmp_state = crtc_state->base; |
scaler_state = crtc_state->scaler_state; |
shared_dpll = crtc_state->shared_dpll; |
dpll_hw_state = crtc_state->dpll_hw_state; |
ddi_pll_sel = crtc_state->ddi_pll_sel; |
force_thru = crtc_state->pch_pfit.force_thru; |
|
memset(crtc_state, 0, sizeof *crtc_state); |
|
crtc_state->base = tmp_state; |
crtc_state->scaler_state = scaler_state; |
crtc_state->shared_dpll = shared_dpll; |
crtc_state->dpll_hw_state = dpll_hw_state; |
crtc_state->ddi_pll_sel = ddi_pll_sel; |
crtc_state->pch_pfit.force_thru = force_thru; |
} |
|
pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
if (!pipe_config) |
return ERR_PTR(-ENOMEM); |
static int |
intel_modeset_pipe_config(struct drm_crtc *crtc, |
struct intel_crtc_state *pipe_config) |
{ |
struct drm_atomic_state *state = pipe_config->base.state; |
struct intel_encoder *encoder; |
struct drm_connector *connector; |
struct drm_connector_state *connector_state; |
int base_bpp, ret = -EINVAL; |
int i; |
bool retry = true; |
|
drm_mode_copy(&pipe_config->adjusted_mode, mode); |
drm_mode_copy(&pipe_config->requested_mode, mode); |
clear_intel_crtc_state(pipe_config); |
|
pipe_config->cpu_transcoder = |
(enum transcoder) to_intel_crtc(crtc)->pipe; |
pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
|
/* |
* Sanitize sync polarity flags based on requested ones. If neither |
9991,21 → 12208,17 |
* positive or negative polarity is requested, treat this as meaning |
* negative polarity. |
*/ |
if (!(pipe_config->adjusted_mode.flags & |
if (!(pipe_config->base.adjusted_mode.flags & |
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
|
if (!(pipe_config->adjusted_mode.flags & |
if (!(pipe_config->base.adjusted_mode.flags & |
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
|
/* Compute a starting value for pipe_config->pipe_bpp taking the source |
* plane pixel format and any sink constraints into account. Returns the |
* source plane bpp so that dithering can be selected on mismatches |
* after encoders and crtc also have had their say. */ |
plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
fb, pipe_config); |
if (plane_bpp < 0) |
base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
pipe_config); |
if (base_bpp < 0) |
goto fail; |
|
/* |
10016,9 → 12229,9 |
* computation to clearly distinguish it from the adjusted mode, which |
* can be changed by the connectors in the below retry loop. |
*/ |
drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
drm_crtc_get_hv_timing(&pipe_config->base.mode, |
&pipe_config->pipe_src_w, |
&pipe_config->pipe_src_h); |
|
encoder_retry: |
/* Ensure the port clock defaults are reset when retrying. */ |
10026,17 → 12239,19 |
pipe_config->pixel_multiplier = 1; |
|
/* Fill in default crtc timings, allow encoders to overwrite them. */ |
drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
CRTC_STEREO_DOUBLE); |
|
/* Pass our mode to the connectors and the CRTC to give them a chance to |
* adjust it according to limitations or connector properties, and also |
* a chance to reject the mode entirely. |
*/ |
for_each_intel_encoder(dev, encoder) { |
|
if (&encoder->new_crtc->base != crtc) |
for_each_connector_in_state(state, connector, connector_state, i) { |
if (connector_state->crtc != crtc) |
continue; |
|
encoder = to_intel_encoder(connector_state->best_encoder); |
|
if (!(encoder->compute_config(encoder, pipe_config))) { |
DRM_DEBUG_KMS("Encoder config failure\n"); |
goto fail; |
10046,7 → 12261,7 |
/* Set default port clock if not overwritten by the encoder. Needs to be |
* done afterwards in case the encoder adjusts the mode. */ |
if (!pipe_config->port_clock) |
pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
* pipe_config->pixel_multiplier; |
|
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
10066,216 → 12281,187 |
goto encoder_retry; |
} |
|
pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
/* Dithering seems to not pass-through bits correctly when it should, so |
* only enable it on 6bpc panels. */ |
pipe_config->dither = pipe_config->pipe_bpp == 6*3; |
DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
|
return pipe_config; |
fail: |
kfree(pipe_config); |
return ERR_PTR(ret); |
return ret; |
} |
|
/* Computes which crtcs are affected and sets the relevant bits in the mask. For |
* simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
static void |
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
unsigned *prepare_pipes, unsigned *disable_pipes) |
intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
{ |
struct intel_crtc *intel_crtc; |
struct drm_device *dev = crtc->dev; |
struct intel_encoder *encoder; |
struct intel_connector *connector; |
struct drm_crtc *tmp_crtc; |
struct drm_crtc *crtc; |
struct drm_crtc_state *crtc_state; |
int i; |
|
*disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
/* Double check state. */ |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
|
/* Check which crtcs have changed outputs connected to them, these need |
* to be part of the prepare_pipes mask. We don't (yet) support global |
* modeset across multiple crtcs, so modeset_pipes will only have one |
* bit set at most. */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
if (connector->base.encoder == &connector->new_encoder->base) |
continue; |
|
if (connector->base.encoder) { |
tmp_crtc = connector->base.encoder->crtc; |
|
*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
/* Update hwmode for vblank functions */ |
if (crtc->state->active) |
crtc->hwmode = crtc->state->adjusted_mode; |
else |
crtc->hwmode.crtc_clock = 0; |
} |
|
if (connector->new_encoder) |
*prepare_pipes |= |
1 << connector->new_encoder->new_crtc->pipe; |
} |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->base.crtc == &encoder->new_crtc->base) |
continue; |
static bool intel_fuzzy_clock_check(int clock1, int clock2) |
{ |
int diff; |
|
if (encoder->base.crtc) { |
tmp_crtc = encoder->base.crtc; |
if (clock1 == clock2) |
return true; |
|
*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
} |
if (!clock1 || !clock2) |
return false; |
|
if (encoder->new_crtc) |
*prepare_pipes |= 1 << encoder->new_crtc->pipe; |
} |
diff = abs(clock1 - clock2); |
|
/* Check for pipes that will be enabled/disabled ... */ |
for_each_intel_crtc(dev, intel_crtc) { |
if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
continue; |
if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
return true; |
|
if (!intel_crtc->new_enabled) |
*disable_pipes |= 1 << intel_crtc->pipe; |
else |
*prepare_pipes |= 1 << intel_crtc->pipe; |
return false; |
} |
|
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
list_for_each_entry((intel_crtc), \ |
&(dev)->mode_config.crtc_list, \ |
base.head) \ |
if (mask & (1 <<(intel_crtc)->pipe)) |
|
/* set_mode is also used to update properties on life display pipes. */ |
intel_crtc = to_intel_crtc(crtc); |
if (intel_crtc->new_enabled) |
*prepare_pipes |= 1 << intel_crtc->pipe; |
|
/* |
* For simplicity do a full modeset on any pipe where the output routing |
* changed. We could be more clever, but that would require us to be |
* more careful with calling the relevant encoder->mode_set functions. |
*/ |
if (*prepare_pipes) |
*modeset_pipes = *prepare_pipes; |
|
/* ... and mask these out. */ |
*modeset_pipes &= ~(*disable_pipes); |
*prepare_pipes &= ~(*disable_pipes); |
|
/* |
* HACK: We don't (yet) fully support global modesets. intel_set_config |
* obies this rule, but the modeset restore mode of |
* intel_modeset_setup_hw_state does not. |
*/ |
*modeset_pipes &= 1 << intel_crtc->pipe; |
*prepare_pipes &= 1 << intel_crtc->pipe; |
|
DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
*modeset_pipes, *prepare_pipes, *disable_pipes); |
} |
|
static bool intel_crtc_in_use(struct drm_crtc *crtc) |
static bool |
intel_compare_m_n(unsigned int m, unsigned int n, |
unsigned int m2, unsigned int n2, |
bool exact) |
{ |
struct drm_encoder *encoder; |
struct drm_device *dev = crtc->dev; |
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
if (encoder->crtc == crtc) |
if (m == m2 && n == n2) |
return true; |
|
if (exact || !m || !n || !m2 || !n2) |
return false; |
} |
|
static void |
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_encoder *intel_encoder; |
struct intel_crtc *intel_crtc; |
struct drm_connector *connector; |
BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
|
intel_shared_dpll_commit(dev_priv); |
|
for_each_intel_encoder(dev, intel_encoder) { |
if (!intel_encoder->base.crtc) |
continue; |
|
intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
|
if (prepare_pipes & (1 << intel_crtc->pipe)) |
intel_encoder->connectors_active = false; |
if (m > m2) { |
while (m > m2) { |
m2 <<= 1; |
n2 <<= 1; |
} |
|
intel_modeset_commit_output_state(dev); |
|
/* Double check state. */ |
for_each_intel_crtc(dev, intel_crtc) { |
WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
WARN_ON(intel_crtc->new_config && |
intel_crtc->new_config != &intel_crtc->config); |
WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
} else if (m < m2) { |
while (m < m2) { |
m <<= 1; |
n <<= 1; |
} |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
if (!connector->encoder || !connector->encoder->crtc) |
continue; |
|
intel_crtc = to_intel_crtc(connector->encoder->crtc); |
|
if (prepare_pipes & (1 << intel_crtc->pipe)) { |
struct drm_property *dpms_property = |
dev->mode_config.dpms_property; |
|
connector->dpms = DRM_MODE_DPMS_ON; |
drm_object_property_set_value(&connector->base, |
dpms_property, |
DRM_MODE_DPMS_ON); |
|
intel_encoder = to_intel_encoder(connector->encoder); |
intel_encoder->connectors_active = true; |
} |
} |
|
return m == m2 && n == n2; |
} |
|
static bool intel_fuzzy_clock_check(int clock1, int clock2) |
static bool |
intel_compare_link_m_n(const struct intel_link_m_n *m_n, |
struct intel_link_m_n *m2_n2, |
bool adjust) |
{ |
int diff; |
if (m_n->tu == m2_n2->tu && |
intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, |
m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && |
intel_compare_m_n(m_n->link_m, m_n->link_n, |
m2_n2->link_m, m2_n2->link_n, !adjust)) { |
if (adjust) |
*m2_n2 = *m_n; |
|
if (clock1 == clock2) |
return true; |
} |
|
if (!clock1 || !clock2) |
return false; |
|
diff = abs(clock1 - clock2); |
|
if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
return true; |
|
return false; |
} |
|
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
list_for_each_entry((intel_crtc), \ |
&(dev)->mode_config.crtc_list, \ |
base.head) \ |
if (mask & (1 <<(intel_crtc)->pipe)) |
|
static bool |
intel_pipe_config_compare(struct drm_device *dev, |
struct intel_crtc_config *current_config, |
struct intel_crtc_config *pipe_config) |
struct intel_crtc_state *current_config, |
struct intel_crtc_state *pipe_config, |
bool adjust) |
{ |
bool ret = true; |
|
#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ |
do { \ |
if (!adjust) \ |
DRM_ERROR(fmt, ##__VA_ARGS__); \ |
else \ |
DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ |
} while (0) |
|
#define PIPE_CONF_CHECK_X(name) \ |
if (current_config->name != pipe_config->name) { \ |
DRM_ERROR("mismatch in " #name " " \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected 0x%08x, found 0x%08x)\n", \ |
current_config->name, \ |
pipe_config->name); \ |
return false; \ |
ret = false; \ |
} |
|
#define PIPE_CONF_CHECK_I(name) \ |
if (current_config->name != pipe_config->name) { \ |
DRM_ERROR("mismatch in " #name " " \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected %i, found %i)\n", \ |
current_config->name, \ |
pipe_config->name); \ |
return false; \ |
ret = false; \ |
} |
|
#define PIPE_CONF_CHECK_M_N(name) \ |
if (!intel_compare_link_m_n(¤t_config->name, \ |
&pipe_config->name,\ |
adjust)) { \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected tu %i gmch %i/%i link %i/%i, " \ |
"found tu %i, gmch %i/%i link %i/%i)\n", \ |
current_config->name.tu, \ |
current_config->name.gmch_m, \ |
current_config->name.gmch_n, \ |
current_config->name.link_m, \ |
current_config->name.link_n, \ |
pipe_config->name.tu, \ |
pipe_config->name.gmch_m, \ |
pipe_config->name.gmch_n, \ |
pipe_config->name.link_m, \ |
pipe_config->name.link_n); \ |
ret = false; \ |
} |
|
#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
if (!intel_compare_link_m_n(¤t_config->name, \ |
&pipe_config->name, adjust) && \ |
!intel_compare_link_m_n(¤t_config->alt_name, \ |
&pipe_config->name, adjust)) { \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected tu %i gmch %i/%i link %i/%i, " \ |
"or tu %i gmch %i/%i link %i/%i, " \ |
"found tu %i, gmch %i/%i link %i/%i)\n", \ |
current_config->name.tu, \ |
current_config->name.gmch_m, \ |
current_config->name.gmch_n, \ |
current_config->name.link_m, \ |
current_config->name.link_n, \ |
current_config->alt_name.tu, \ |
current_config->alt_name.gmch_m, \ |
current_config->alt_name.gmch_n, \ |
current_config->alt_name.link_m, \ |
current_config->alt_name.link_n, \ |
pipe_config->name.tu, \ |
pipe_config->name.gmch_m, \ |
pipe_config->name.gmch_n, \ |
pipe_config->name.link_m, \ |
pipe_config->name.link_n); \ |
ret = false; \ |
} |
|
/* This is required for BDW+ where there is only one set of registers for |
* switching between high and low RR. |
* This macro can be used whenever a comparison has to be made between one |
10284,30 → 12470,30 |
#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ |
if ((current_config->name != pipe_config->name) && \ |
(current_config->alt_name != pipe_config->name)) { \ |
DRM_ERROR("mismatch in " #name " " \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected %i or %i, found %i)\n", \ |
current_config->name, \ |
current_config->alt_name, \ |
pipe_config->name); \ |
return false; \ |
ret = false; \ |
} |
|
#define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
"(expected %i, found %i)\n", \ |
current_config->name & (mask), \ |
pipe_config->name & (mask)); \ |
return false; \ |
ret = false; \ |
} |
|
#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
DRM_ERROR("mismatch in " #name " " \ |
INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
"(expected %i, found %i)\n", \ |
current_config->name, \ |
pipe_config->name); \ |
return false; \ |
ret = false; \ |
} |
|
#define PIPE_CONF_QUIRK(quirk) \ |
10317,49 → 12503,32 |
|
PIPE_CONF_CHECK_I(has_pch_encoder); |
PIPE_CONF_CHECK_I(fdi_lanes); |
PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
PIPE_CONF_CHECK_I(fdi_m_n.tu); |
PIPE_CONF_CHECK_M_N(fdi_m_n); |
|
PIPE_CONF_CHECK_I(has_dp_encoder); |
PIPE_CONF_CHECK_I(lane_count); |
|
if (INTEL_INFO(dev)->gen < 8) { |
PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
PIPE_CONF_CHECK_I(dp_m_n.link_m); |
PIPE_CONF_CHECK_I(dp_m_n.link_n); |
PIPE_CONF_CHECK_I(dp_m_n.tu); |
PIPE_CONF_CHECK_M_N(dp_m_n); |
|
if (current_config->has_drrs) { |
PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); |
PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); |
PIPE_CONF_CHECK_I(dp_m2_n2.link_m); |
PIPE_CONF_CHECK_I(dp_m2_n2.link_n); |
PIPE_CONF_CHECK_I(dp_m2_n2.tu); |
} |
} else { |
PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); |
PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); |
PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); |
PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); |
PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); |
} |
if (current_config->has_drrs) |
PIPE_CONF_CHECK_M_N(dp_m2_n2); |
} else |
PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
|
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); |
|
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); |
PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); |
|
PIPE_CONF_CHECK_I(pixel_multiplier); |
PIPE_CONF_CHECK_I(has_hdmi_sink); |
10370,45 → 12539,39 |
|
PIPE_CONF_CHECK_I(has_audio); |
|
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
DRM_MODE_FLAG_INTERLACE); |
|
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
DRM_MODE_FLAG_PHSYNC); |
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
DRM_MODE_FLAG_NHSYNC); |
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
DRM_MODE_FLAG_PVSYNC); |
PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
DRM_MODE_FLAG_NVSYNC); |
} |
|
PIPE_CONF_CHECK_I(pipe_src_w); |
PIPE_CONF_CHECK_I(pipe_src_h); |
|
/* |
* FIXME: BIOS likes to set up a cloned config with lvds+external |
* screen. Since we don't yet re-compute the pipe config when moving |
* just the lvds port away to another pipe the sw tracking won't match. |
* |
* Proper atomic modesets with recomputed global state will fix this. |
* Until then just don't check gmch state for inherited modes. |
*/ |
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { |
PIPE_CONF_CHECK_I(gmch_pfit.control); |
PIPE_CONF_CHECK_X(gmch_pfit.control); |
/* pfit ratios are autocomputed by the hw on gen4+ */ |
if (INTEL_INFO(dev)->gen < 4) |
PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
} |
PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
|
if (!adjust) { |
PIPE_CONF_CHECK_I(pipe_src_w); |
PIPE_CONF_CHECK_I(pipe_src_h); |
|
PIPE_CONF_CHECK_I(pch_pfit.enabled); |
if (current_config->pch_pfit.enabled) { |
PIPE_CONF_CHECK_I(pch_pfit.pos); |
PIPE_CONF_CHECK_I(pch_pfit.size); |
PIPE_CONF_CHECK_X(pch_pfit.pos); |
PIPE_CONF_CHECK_X(pch_pfit.size); |
} |
|
PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
} |
|
/* BDW+ don't expose a synchronous way to read the state */ |
if (IS_HASWELL(dev)) |
PIPE_CONF_CHECK_I(ips_enabled); |
10423,6 → 12586,7 |
PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); |
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); |
10430,7 → 12594,7 |
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
PIPE_CONF_CHECK_I(pipe_bpp); |
|
PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
|
#undef PIPE_CONF_CHECK_X |
10439,8 → 12603,9 |
#undef PIPE_CONF_CHECK_FLAGS |
#undef PIPE_CONF_CHECK_CLOCK_FUZZY |
#undef PIPE_CONF_QUIRK |
#undef INTEL_ERR_OR_DBG_KMS |
|
return true; |
return ret; |
} |
|
static void check_wm_state(struct drm_device *dev) |
10464,7 → 12629,7 |
continue; |
|
/* planes */ |
for_each_plane(pipe, plane) { |
for_each_plane(dev_priv, pipe, plane) { |
hw_entry = &hw_ddb.plane[pipe][plane]; |
sw_entry = &sw_ddb->plane[pipe][plane]; |
|
10479,8 → 12644,8 |
} |
|
/* cursor */ |
hw_entry = &hw_ddb.cursor[pipe]; |
sw_entry = &sw_ddb->cursor[pipe]; |
hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; |
|
if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
continue; |
10494,18 → 12659,23 |
} |
|
static void |
check_connector_state(struct drm_device *dev) |
check_connector_state(struct drm_device *dev, |
struct drm_atomic_state *old_state) |
{ |
struct intel_connector *connector; |
struct drm_connector_state *old_conn_state; |
struct drm_connector *connector; |
int i; |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
struct drm_encoder *encoder = connector->encoder; |
struct drm_connector_state *state = connector->state; |
|
/* This also checks the encoder/connector hw state with the |
* ->get_hw_state callbacks. */ |
intel_connector_check_state(connector); |
intel_connector_check_state(to_intel_connector(connector)); |
|
WARN(&connector->new_encoder->base != connector->base.encoder, |
"connector's staged encoder doesn't match current encoder\n"); |
I915_STATE_WARN(state->best_encoder != encoder, |
"connector's atomic encoder doesn't match legacy encoder\n"); |
} |
} |
|
10517,124 → 12687,107 |
|
for_each_intel_encoder(dev, encoder) { |
bool enabled = false; |
bool active = false; |
enum pipe pipe, tracked_pipe; |
enum pipe pipe; |
|
DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
encoder->base.base.id, |
encoder->base.name); |
|
WARN(&encoder->new_crtc->base != encoder->base.crtc, |
"encoder's stage crtc doesn't match current crtc\n"); |
WARN(encoder->connectors_active && !encoder->base.crtc, |
"encoder's active_connectors set, but no crtc\n"); |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
if (connector->base.encoder != &encoder->base) |
for_each_intel_connector(dev, connector) { |
if (connector->base.state->best_encoder != &encoder->base) |
continue; |
enabled = true; |
if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
active = true; |
|
I915_STATE_WARN(connector->base.state->crtc != |
encoder->base.crtc, |
"connector's crtc doesn't match encoder crtc\n"); |
} |
/* |
* for MST connectors if we unplug the connector is gone |
* away but the encoder is still connected to a crtc |
* until a modeset happens in response to the hotplug. |
*/ |
if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) |
continue; |
|
WARN(!!encoder->base.crtc != enabled, |
I915_STATE_WARN(!!encoder->base.crtc != enabled, |
"encoder's enabled state mismatch " |
"(expected %i, found %i)\n", |
!!encoder->base.crtc, enabled); |
WARN(active && !encoder->base.crtc, |
"active encoder with no crtc\n"); |
|
WARN(encoder->connectors_active != active, |
"encoder's computed active state doesn't match tracked active state " |
"(expected %i, found %i)\n", active, encoder->connectors_active); |
if (!encoder->base.crtc) { |
bool active; |
|
active = encoder->get_hw_state(encoder, &pipe); |
WARN(active != encoder->connectors_active, |
"encoder's hw state doesn't match sw tracking " |
"(expected %i, found %i)\n", |
encoder->connectors_active, active); |
|
if (!encoder->base.crtc) |
continue; |
|
tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
WARN(active && pipe != tracked_pipe, |
"active encoder's pipe doesn't match" |
"(expected %i, found %i)\n", |
tracked_pipe, pipe); |
|
I915_STATE_WARN(active, |
"encoder detached but still enabled on pipe %c.\n", |
pipe_name(pipe)); |
} |
} |
} |
|
static void |
check_crtc_state(struct drm_device *dev) |
check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *crtc; |
struct intel_encoder *encoder; |
struct intel_crtc_config pipe_config; |
struct drm_crtc_state *old_crtc_state; |
struct drm_crtc *crtc; |
int i; |
|
for_each_intel_crtc(dev, crtc) { |
bool enabled = false; |
bool active = false; |
for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_crtc_state *pipe_config, *sw_config; |
bool active; |
|
memset(&pipe_config, 0, sizeof(pipe_config)); |
if (!needs_modeset(crtc->state) && |
!to_intel_crtc_state(crtc->state)->update_pipe) |
continue; |
|
__drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
pipe_config = to_intel_crtc_state(old_crtc_state); |
memset(pipe_config, 0, sizeof(*pipe_config)); |
pipe_config->base.crtc = crtc; |
pipe_config->base.state = old_state; |
|
DRM_DEBUG_KMS("[CRTC:%d]\n", |
crtc->base.base.id); |
crtc->base.id); |
|
WARN(crtc->active && !crtc->base.enabled, |
"active crtc, but not enabled in sw tracking\n"); |
active = dev_priv->display.get_pipe_config(intel_crtc, |
pipe_config); |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->base.crtc != &crtc->base) |
continue; |
enabled = true; |
if (encoder->connectors_active) |
active = true; |
} |
/* hw state is inconsistent with the pipe quirk */ |
if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
(intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
active = crtc->state->active; |
|
WARN(active != crtc->active, |
"crtc's computed active state doesn't match tracked active state " |
"(expected %i, found %i)\n", active, crtc->active); |
WARN(enabled != crtc->base.enabled, |
"crtc's computed enabled state doesn't match tracked enabled state " |
"(expected %i, found %i)\n", enabled, crtc->base.enabled); |
I915_STATE_WARN(crtc->state->active != active, |
"crtc active state doesn't match with hw state " |
"(expected %i, found %i)\n", crtc->state->active, active); |
|
active = dev_priv->display.get_pipe_config(crtc, |
&pipe_config); |
I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
"transitional active state does not match atomic hw state " |
"(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
|
/* hw state is inconsistent with the pipe quirk */ |
if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
(crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) |
active = crtc->active; |
for_each_encoder_on_crtc(dev, crtc, encoder) { |
enum pipe pipe; |
|
for_each_intel_encoder(dev, encoder) { |
enum pipe pipe; |
if (encoder->base.crtc != &crtc->base) |
continue; |
if (encoder->get_hw_state(encoder, &pipe)) |
encoder->get_config(encoder, &pipe_config); |
active = encoder->get_hw_state(encoder, &pipe); |
I915_STATE_WARN(active != crtc->state->active, |
"[ENCODER:%i] active %i with crtc active %i\n", |
encoder->base.base.id, active, crtc->state->active); |
|
I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
"Encoder connected to wrong pipe %c\n", |
pipe_name(pipe)); |
|
if (active) |
encoder->get_config(encoder, pipe_config); |
} |
|
WARN(crtc->active != active, |
"crtc active state doesn't match with hw state " |
"(expected %i, found %i)\n", crtc->active, active); |
if (!crtc->state->active) |
continue; |
|
if (active && |
!intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
WARN(1, "pipe state doesn't match!\n"); |
intel_dump_pipe_config(crtc, &pipe_config, |
sw_config = to_intel_crtc_state(crtc->state); |
if (!intel_pipe_config_compare(dev, sw_config, |
pipe_config, false)) { |
I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
intel_dump_pipe_config(intel_crtc, pipe_config, |
"[hw state]"); |
intel_dump_pipe_config(crtc, &crtc->config, |
intel_dump_pipe_config(intel_crtc, sw_config, |
"[sw state]"); |
} |
} |
10659,47 → 12812,48 |
|
active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
|
WARN(pll->active > hweight32(pll->config.crtc_mask), |
I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
"more active pll users than references: %i vs %i\n", |
pll->active, hweight32(pll->config.crtc_mask)); |
WARN(pll->active && !pll->on, |
I915_STATE_WARN(pll->active && !pll->on, |
"pll in active use but not on in sw tracking\n"); |
WARN(pll->on && !pll->active, |
I915_STATE_WARN(pll->on && !pll->active, |
"pll in on but not on in use in sw tracking\n"); |
WARN(pll->on != active, |
I915_STATE_WARN(pll->on != active, |
"pll on state mismatch (expected %i, found %i)\n", |
pll->on, active); |
|
for_each_intel_crtc(dev, crtc) { |
if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
enabled_crtcs++; |
if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
active_crtcs++; |
} |
WARN(pll->active != active_crtcs, |
I915_STATE_WARN(pll->active != active_crtcs, |
"pll active crtcs mismatch (expected %i, found %i)\n", |
pll->active, active_crtcs); |
WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
"pll enabled crtcs mismatch (expected %i, found %i)\n", |
hweight32(pll->config.crtc_mask), enabled_crtcs); |
|
WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
sizeof(dpll_hw_state)), |
"pll hw state mismatch\n"); |
} |
} |
|
void |
intel_modeset_check_state(struct drm_device *dev) |
static void |
intel_modeset_check_state(struct drm_device *dev, |
struct drm_atomic_state *old_state) |
{ |
check_wm_state(dev); |
check_connector_state(dev); |
check_connector_state(dev, old_state); |
check_encoder_state(dev); |
check_crtc_state(dev); |
check_crtc_state(dev, old_state); |
check_shared_dpll_state(dev); |
} |
|
void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
int dotclock) |
{ |
/* |
10706,9 → 12860,9 |
* FDI already provided one idea for the dotclock. |
* Yell if the encoder disagrees. |
*/ |
WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
pipe_config->adjusted_mode.crtc_clock, dotclock); |
pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
} |
|
static void update_scanline_offset(struct intel_crtc *crtc) |
10734,11 → 12888,11 |
* one to the value. |
*/ |
if (IS_GEN2(dev)) { |
const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
int vtotal; |
|
vtotal = mode->crtc_vtotal; |
if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
vtotal = adjusted_mode->crtc_vtotal; |
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
vtotal /= 2; |
|
crtc->scanline_offset = vtotal - 1; |
10749,679 → 12903,412 |
crtc->scanline_offset = 1; |
} |
|
static struct intel_crtc_config * |
intel_modeset_compute_config(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
struct drm_framebuffer *fb, |
unsigned *modeset_pipes, |
unsigned *prepare_pipes, |
unsigned *disable_pipes) |
static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
{ |
struct intel_crtc_config *pipe_config = NULL; |
|
intel_modeset_affected_pipes(crtc, modeset_pipes, |
prepare_pipes, disable_pipes); |
|
if ((*modeset_pipes) == 0) |
goto out; |
|
/* |
* Note this needs changes when we start tracking multiple modes |
* and crtcs. At that point we'll need to compute the whole config |
* (i.e. one pipe_config for each crtc) rather than just the one |
* for this crtc. |
*/ |
pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
if (IS_ERR(pipe_config)) { |
goto out; |
} |
intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
"[modeset]"); |
|
out: |
return pipe_config; |
} |
|
static int __intel_set_mode(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
int x, int y, struct drm_framebuffer *fb, |
struct intel_crtc_config *pipe_config, |
unsigned modeset_pipes, |
unsigned prepare_pipes, |
unsigned disable_pipes) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_display_mode *saved_mode; |
struct drm_device *dev = state->dev; |
struct drm_i915_private *dev_priv = to_i915(dev); |
struct intel_shared_dpll_config *shared_dpll = NULL; |
struct intel_crtc *intel_crtc; |
int ret = 0; |
struct intel_crtc_state *intel_crtc_state; |
struct drm_crtc *crtc; |
struct drm_crtc_state *crtc_state; |
int i; |
|
saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
if (!saved_mode) |
return -ENOMEM; |
if (!dev_priv->display.crtc_compute_clock) |
return; |
|
*saved_mode = crtc->mode; |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
int dpll; |
|
if (modeset_pipes) |
to_intel_crtc(crtc)->new_config = pipe_config; |
intel_crtc = to_intel_crtc(crtc); |
intel_crtc_state = to_intel_crtc_state(crtc_state); |
dpll = intel_crtc_state->shared_dpll; |
|
/* |
* See if the config requires any additional preparation, e.g. |
* to adjust global state with pipes off. We need to do this |
* here so we can get the modeset_pipe updated config for the new |
* mode set on this crtc. For other crtcs we need to use the |
* adjusted_mode bits in the crtc directly. |
*/ |
if (IS_VALLEYVIEW(dev)) { |
valleyview_modeset_global_pipes(dev, &prepare_pipes); |
if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
continue; |
|
/* may have added more to prepare_pipes than we should */ |
prepare_pipes &= ~disable_pipes; |
} |
intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
|
if (dev_priv->display.crtc_compute_clock) { |
unsigned clear_pipes = modeset_pipes | disable_pipes; |
if (!shared_dpll) |
shared_dpll = intel_atomic_get_shared_dpll_state(state); |
|
ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |
if (ret) |
goto done; |
|
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
ret = dev_priv->display.crtc_compute_clock(intel_crtc); |
if (ret) { |
intel_shared_dpll_abort_config(dev_priv); |
goto done; |
shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
} |
} |
} |
|
for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
intel_crtc_disable(&intel_crtc->base); |
|
for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
if (intel_crtc->base.enabled) |
dev_priv->display.crtc_disable(&intel_crtc->base); |
} |
|
/* crtc->mode is already used by the ->mode_set callbacks, hence we need |
* to set it here already despite that we pass it down the callchain. |
* |
* Note we'll need to fix this up when we start tracking multiple |
* pipes; here we assume a single modeset_pipe and only track the |
* single crtc and mode. |
*/ |
if (modeset_pipes) { |
crtc->mode = *mode; |
/* mode_set/enable/disable functions rely on a correct pipe |
* config. */ |
to_intel_crtc(crtc)->config = *pipe_config; |
to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
|
/* |
* Calculate and store various constants which |
* are later needed by vblank and swap-completion |
* timestamping. They are derived from true hwmode. |
* This implements the workaround described in the "notes" section of the mode |
* set sequence documentation. When going from no pipes or single pipe to |
* multiple pipes, and planes are enabled after the pipe, we need to wait at |
* least 2 vblanks on the first pipe before enabling planes on the second pipe. |
*/ |
drm_calc_timestamping_constants(crtc, |
&pipe_config->adjusted_mode); |
} |
static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) |
{ |
struct drm_crtc_state *crtc_state; |
struct intel_crtc *intel_crtc; |
struct drm_crtc *crtc; |
struct intel_crtc_state *first_crtc_state = NULL; |
struct intel_crtc_state *other_crtc_state = NULL; |
enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; |
int i; |
|
/* Only after disabling all output pipelines that will be changed can we |
* update the the output configuration. */ |
intel_modeset_update_state(dev, prepare_pipes); |
/* look at all crtc's that are going to be enabled in during modeset */ |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
intel_crtc = to_intel_crtc(crtc); |
|
modeset_update_crtc_power_domains(dev); |
if (!crtc_state->active || !needs_modeset(crtc_state)) |
continue; |
|
/* Set up the DPLL and any encoders state that needs to adjust or depend |
* on the DPLL. |
*/ |
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
struct drm_framebuffer *old_fb = crtc->primary->fb; |
struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
mutex_lock(&dev->struct_mutex); |
ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL); |
if (ret != 0) { |
DRM_ERROR("pin & fence failed\n"); |
mutex_unlock(&dev->struct_mutex); |
goto done; |
if (first_crtc_state) { |
other_crtc_state = to_intel_crtc_state(crtc_state); |
break; |
} else { |
first_crtc_state = to_intel_crtc_state(crtc_state); |
first_pipe = intel_crtc->pipe; |
} |
if (old_fb) |
intel_unpin_fb_obj(old_obj); |
i915_gem_track_fb(old_obj, obj, |
INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
mutex_unlock(&dev->struct_mutex); |
|
crtc->primary->fb = fb; |
crtc->x = x; |
crtc->y = y; |
} |
|
/* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
update_scanline_offset(intel_crtc); |
/* No workaround needed? */ |
if (!first_crtc_state) |
return 0; |
|
dev_priv->display.crtc_enable(&intel_crtc->base); |
} |
/* w/a possibly needed, check how many crtc's are already enabled. */ |
for_each_intel_crtc(state->dev, intel_crtc) { |
struct intel_crtc_state *pipe_config; |
|
/* FIXME: add subpixel order */ |
done: |
if (ret && crtc->enabled) |
crtc->mode = *saved_mode; |
pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); |
if (IS_ERR(pipe_config)) |
return PTR_ERR(pipe_config); |
|
kfree(pipe_config); |
kfree(saved_mode); |
return ret; |
} |
pipe_config->hsw_workaround_pipe = INVALID_PIPE; |
|
static int intel_set_mode_pipes(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
int x, int y, struct drm_framebuffer *fb, |
struct intel_crtc_config *pipe_config, |
unsigned modeset_pipes, |
unsigned prepare_pipes, |
unsigned disable_pipes) |
{ |
int ret; |
if (!pipe_config->base.active || |
needs_modeset(&pipe_config->base)) |
continue; |
|
ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
prepare_pipes, disable_pipes); |
/* 2 or more enabled crtcs means no need for w/a */ |
if (enabled_pipe != INVALID_PIPE) |
return 0; |
|
if (ret == 0) |
intel_modeset_check_state(crtc->dev); |
|
return ret; |
enabled_pipe = intel_crtc->pipe; |
} |
|
static int intel_set_mode(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
int x, int y, struct drm_framebuffer *fb) |
{ |
struct intel_crtc_config *pipe_config; |
unsigned modeset_pipes, prepare_pipes, disable_pipes; |
if (enabled_pipe != INVALID_PIPE) |
first_crtc_state->hsw_workaround_pipe = enabled_pipe; |
else if (other_crtc_state) |
other_crtc_state->hsw_workaround_pipe = first_pipe; |
|
pipe_config = intel_modeset_compute_config(crtc, mode, fb, |
&modeset_pipes, |
&prepare_pipes, |
&disable_pipes); |
|
if (IS_ERR(pipe_config)) |
return PTR_ERR(pipe_config); |
|
return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, |
modeset_pipes, prepare_pipes, |
disable_pipes); |
return 0; |
} |
|
void intel_crtc_restore_mode(struct drm_crtc *crtc) |
static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
{ |
intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
} |
|
#undef for_each_intel_crtc_masked |
|
static void intel_set_config_free(struct intel_set_config *config) |
{ |
if (!config) |
return; |
|
kfree(config->save_connector_encoders); |
kfree(config->save_encoder_crtcs); |
kfree(config->save_crtc_enabled); |
kfree(config); |
} |
|
static int intel_set_config_save_state(struct drm_device *dev, |
struct intel_set_config *config) |
{ |
struct drm_crtc *crtc; |
struct drm_encoder *encoder; |
struct drm_connector *connector; |
int count; |
struct drm_crtc_state *crtc_state; |
int ret = 0; |
|
config->save_crtc_enabled = |
kcalloc(dev->mode_config.num_crtc, |
sizeof(bool), GFP_KERNEL); |
if (!config->save_crtc_enabled) |
return -ENOMEM; |
/* add all active pipes to the state */ |
for_each_crtc(state->dev, crtc) { |
crtc_state = drm_atomic_get_crtc_state(state, crtc); |
if (IS_ERR(crtc_state)) |
return PTR_ERR(crtc_state); |
|
config->save_encoder_crtcs = |
kcalloc(dev->mode_config.num_encoder, |
sizeof(struct drm_crtc *), GFP_KERNEL); |
if (!config->save_encoder_crtcs) |
return -ENOMEM; |
if (!crtc_state->active || needs_modeset(crtc_state)) |
continue; |
|
config->save_connector_encoders = |
kcalloc(dev->mode_config.num_connector, |
sizeof(struct drm_encoder *), GFP_KERNEL); |
if (!config->save_connector_encoders) |
return -ENOMEM; |
crtc_state->mode_changed = true; |
|
/* Copy data. Note that driver private data is not affected. |
* Should anything bad happen only the expected state is |
* restored, not the drivers personal bookkeeping. |
*/ |
count = 0; |
for_each_crtc(dev, crtc) { |
config->save_crtc_enabled[count++] = crtc->enabled; |
} |
ret = drm_atomic_add_affected_connectors(state, crtc); |
if (ret) |
break; |
|
count = 0; |
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
config->save_encoder_crtcs[count++] = encoder->crtc; |
ret = drm_atomic_add_affected_planes(state, crtc); |
if (ret) |
break; |
} |
|
count = 0; |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
config->save_connector_encoders[count++] = connector->encoder; |
return ret; |
} |
|
return 0; |
} |
|
static void intel_set_config_restore_state(struct drm_device *dev, |
struct intel_set_config *config) |
static int intel_modeset_checks(struct drm_atomic_state *state) |
{ |
struct intel_crtc *crtc; |
struct intel_encoder *encoder; |
struct intel_connector *connector; |
int count; |
struct drm_device *dev = state->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int ret; |
|
count = 0; |
for_each_intel_crtc(dev, crtc) { |
crtc->new_enabled = config->save_crtc_enabled[count++]; |
|
if (crtc->new_enabled) |
crtc->new_config = &crtc->config; |
else |
crtc->new_config = NULL; |
if (!check_digital_port_conflicts(state)) { |
DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
return -EINVAL; |
} |
|
count = 0; |
for_each_intel_encoder(dev, encoder) { |
encoder->new_crtc = |
to_intel_crtc(config->save_encoder_crtcs[count++]); |
} |
/* |
* See if the config requires any additional preparation, e.g. |
* to adjust global state with pipes off. We need to do this |
* here so we can get the modeset_pipe updated config for the new |
* mode set on this crtc. For other crtcs we need to use the |
* adjusted_mode bits in the crtc directly. |
*/ |
if (dev_priv->display.modeset_calc_cdclk) { |
unsigned int cdclk; |
|
count = 0; |
list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
connector->new_encoder = |
to_intel_encoder(config->save_connector_encoders[count++]); |
} |
} |
ret = dev_priv->display.modeset_calc_cdclk(state); |
|
static bool |
is_crtc_connector_off(struct drm_mode_set *set) |
{ |
int i; |
cdclk = to_intel_atomic_state(state)->cdclk; |
if (!ret && cdclk != dev_priv->cdclk_freq) |
ret = intel_modeset_all_pipes(state); |
|
if (set->num_connectors == 0) |
return false; |
if (ret < 0) |
return ret; |
} else |
to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; |
|
if (WARN_ON(set->connectors == NULL)) |
return false; |
intel_modeset_clear_plls(state); |
|
for (i = 0; i < set->num_connectors; i++) |
if (set->connectors[i]->encoder && |
set->connectors[i]->encoder->crtc == set->crtc && |
set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
return true; |
if (IS_HASWELL(dev)) |
return haswell_mode_set_planes_workaround(state); |
|
return false; |
return 0; |
} |
|
static void |
intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
struct intel_set_config *config) |
/** |
* intel_atomic_check - validate state object |
* @dev: drm device |
* @state: state to validate |
*/ |
static int intel_atomic_check(struct drm_device *dev, |
struct drm_atomic_state *state) |
{ |
struct drm_crtc *crtc; |
struct drm_crtc_state *crtc_state; |
int ret, i; |
bool any_ms = false; |
|
/* We should be able to check here if the fb has the same properties |
* and then just flip_or_move it */ |
if (is_crtc_connector_off(set)) { |
config->mode_changed = true; |
} else if (set->crtc->primary->fb != set->fb) { |
/* |
* If we have no fb, we can only flip as long as the crtc is |
* active, otherwise we need a full mode set. The crtc may |
* be active if we've only disabled the primary plane, or |
* in fastboot situations. |
*/ |
if (set->crtc->primary->fb == NULL) { |
struct intel_crtc *intel_crtc = |
to_intel_crtc(set->crtc); |
ret = drm_atomic_helper_check_modeset(dev, state); |
if (ret) |
return ret; |
|
if (intel_crtc->active) { |
DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
config->fb_changed = true; |
} else { |
DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
config->mode_changed = true; |
} |
} else if (set->fb == NULL) { |
config->mode_changed = true; |
} else if (set->fb->pixel_format != |
set->crtc->primary->fb->pixel_format) { |
config->mode_changed = true; |
} else { |
config->fb_changed = true; |
} |
} |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
struct intel_crtc_state *pipe_config = |
to_intel_crtc_state(crtc_state); |
|
if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
config->fb_changed = true; |
memset(&to_intel_crtc(crtc)->atomic, 0, |
sizeof(struct intel_crtc_atomic_commit)); |
|
if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
DRM_DEBUG_KMS("modes are different, full mode set\n"); |
drm_mode_debug_printmodeline(&set->crtc->mode); |
drm_mode_debug_printmodeline(set->mode); |
config->mode_changed = true; |
} |
/* Catch I915_MODE_FLAG_INHERITED */ |
if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) |
crtc_state->mode_changed = true; |
|
DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
set->crtc->base.id, config->mode_changed, config->fb_changed); |
if (!crtc_state->enable) { |
if (needs_modeset(crtc_state)) |
any_ms = true; |
continue; |
} |
|
static int |
intel_modeset_stage_output_state(struct drm_device *dev, |
struct drm_mode_set *set, |
struct intel_set_config *config) |
{ |
struct intel_connector *connector; |
struct intel_encoder *encoder; |
struct intel_crtc *crtc; |
int ro; |
if (!needs_modeset(crtc_state)) |
continue; |
|
/* The upper layers ensure that we either disable a crtc or have a list |
* of connectors. For paranoia, double-check this. */ |
WARN_ON(!set->fb && (set->num_connectors != 0)); |
WARN_ON(set->fb && (set->num_connectors == 0)); |
/* FIXME: For only active_changed we shouldn't need to do any |
* state recomputation at all. */ |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
/* Otherwise traverse passed in connector list and get encoders |
* for them. */ |
for (ro = 0; ro < set->num_connectors; ro++) { |
if (set->connectors[ro] == &connector->base) { |
connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
break; |
} |
} |
ret = drm_atomic_add_affected_connectors(state, crtc); |
if (ret) |
return ret; |
|
/* If we disable the crtc, disable all its connectors. Also, if |
* the connector is on the changing crtc but not on the new |
* connector list, disable it. */ |
if ((!set->fb || ro == set->num_connectors) && |
connector->base.encoder && |
connector->base.encoder->crtc == set->crtc) { |
connector->new_encoder = NULL; |
ret = intel_modeset_pipe_config(crtc, pipe_config); |
if (ret) |
return ret; |
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
connector->base.base.id, |
connector->base.name); |
if (i915.fastboot && |
intel_pipe_config_compare(state->dev, |
to_intel_crtc_state(crtc->state), |
pipe_config, true)) { |
crtc_state->mode_changed = false; |
to_intel_crtc_state(crtc_state)->update_pipe = true; |
} |
|
if (needs_modeset(crtc_state)) { |
any_ms = true; |
|
if (&connector->new_encoder->base != connector->base.encoder) { |
DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
config->mode_changed = true; |
ret = drm_atomic_add_affected_planes(state, crtc); |
if (ret) |
return ret; |
} |
|
intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
needs_modeset(crtc_state) ? |
"[modeset]" : "[fastset]"); |
} |
/* connector->new_encoder is now updated for all connectors. */ |
|
/* Update crtc of enabled connectors. */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
struct drm_crtc *new_crtc; |
if (any_ms) { |
ret = intel_modeset_checks(state); |
|
if (!connector->new_encoder) |
continue; |
if (ret) |
return ret; |
} else |
to_intel_atomic_state(state)->cdclk = |
to_i915(state->dev)->cdclk_freq; |
|
new_crtc = connector->new_encoder->base.crtc; |
|
for (ro = 0; ro < set->num_connectors; ro++) { |
if (set->connectors[ro] == &connector->base) |
new_crtc = set->crtc; |
return drm_atomic_helper_check_planes(state->dev, state); |
} |
|
/* Make sure the new CRTC will work with the encoder */ |
if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
new_crtc)) { |
/** |
* intel_atomic_commit - commit validated state object |
* @dev: DRM device |
* @state: the top-level driver state object |
* @async: asynchronous commit |
* |
* This function commits a top-level state object that has been validated |
* with drm_atomic_helper_check(). |
* |
* FIXME: Atomic modeset support for i915 is not yet complete. At the moment |
* we can only handle plane-related operations and do not yet support |
* asynchronous commit. |
* |
* RETURNS |
* Zero for success or -errno. |
*/ |
static int intel_atomic_commit(struct drm_device *dev, |
struct drm_atomic_state *state, |
bool async) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *crtc; |
struct drm_crtc_state *crtc_state; |
int ret = 0; |
int i; |
bool any_ms = false; |
|
if (async) { |
DRM_DEBUG_KMS("i915 does not yet support async commit\n"); |
return -EINVAL; |
} |
connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
connector->base.base.id, |
connector->base.name, |
new_crtc->base.id); |
} |
ret = drm_atomic_helper_prepare_planes(dev, state); |
if (ret) |
return ret; |
|
/* Check for any encoders that needs to be disabled. */ |
for_each_intel_encoder(dev, encoder) { |
int num_connectors = 0; |
list_for_each_entry(connector, |
&dev->mode_config.connector_list, |
base.head) { |
if (connector->new_encoder == encoder) { |
WARN_ON(!connector->new_encoder->new_crtc); |
num_connectors++; |
} |
} |
drm_atomic_helper_swap_state(dev, state); |
|
if (num_connectors == 0) |
encoder->new_crtc = NULL; |
else if (num_connectors > 1) |
return -EINVAL; |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
/* Only now check for crtc changes so we don't miss encoders |
* that will be disabled. */ |
if (&encoder->new_crtc->base != encoder->base.crtc) { |
DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
config->mode_changed = true; |
} |
} |
/* Now we've also updated encoder->new_crtc for all encoders. */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
if (connector->new_encoder) |
if (connector->new_encoder != connector->encoder) |
connector->encoder = connector->new_encoder; |
} |
for_each_intel_crtc(dev, crtc) { |
crtc->new_enabled = false; |
if (!needs_modeset(crtc->state)) |
continue; |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->new_crtc == crtc) { |
crtc->new_enabled = true; |
break; |
any_ms = true; |
intel_pre_plane_update(intel_crtc); |
|
if (crtc_state->active) { |
intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
dev_priv->display.crtc_disable(crtc); |
intel_crtc->active = false; |
intel_disable_shared_dpll(intel_crtc); |
} |
} |
|
if (crtc->new_enabled != crtc->base.enabled) { |
DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
crtc->new_enabled ? "en" : "dis"); |
config->mode_changed = true; |
} |
/* Only after disabling all output pipelines that will be changed can we |
* update the the output configuration. */ |
intel_modeset_update_crtc_state(state); |
|
if (crtc->new_enabled) |
crtc->new_config = &crtc->config; |
else |
crtc->new_config = NULL; |
} |
if (any_ms) { |
intel_shared_dpll_commit(state); |
|
return 0; |
drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
modeset_update_crtc_power_domains(state); |
} |
|
static void disable_crtc_nofb(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_encoder *encoder; |
struct intel_connector *connector; |
/* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
for_each_crtc_in_state(state, crtc, crtc_state, i) { |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bool modeset = needs_modeset(crtc->state); |
bool update_pipe = !modeset && |
to_intel_crtc_state(crtc->state)->update_pipe; |
unsigned long put_domains = 0; |
|
DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", |
pipe_name(crtc->pipe)); |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
if (connector->new_encoder && |
connector->new_encoder->new_crtc == crtc) |
connector->new_encoder = NULL; |
if (modeset && crtc->state->active) { |
update_scanline_offset(to_intel_crtc(crtc)); |
dev_priv->display.crtc_enable(crtc); |
} |
|
for_each_intel_encoder(dev, encoder) { |
if (encoder->new_crtc == crtc) |
encoder->new_crtc = NULL; |
} |
if (update_pipe) { |
put_domains = modeset_get_crtc_power_domains(crtc); |
|
crtc->new_enabled = false; |
crtc->new_config = NULL; |
/* make sure intel_modeset_check_state runs */ |
any_ms = true; |
} |
|
static int intel_crtc_set_config(struct drm_mode_set *set) |
{ |
struct drm_device *dev; |
struct drm_mode_set save_set; |
struct intel_set_config *config; |
struct intel_crtc_config *pipe_config; |
unsigned modeset_pipes, prepare_pipes, disable_pipes; |
int ret; |
if (!modeset) |
intel_pre_plane_update(intel_crtc); |
|
BUG_ON(!set); |
BUG_ON(!set->crtc); |
BUG_ON(!set->crtc->helper_private); |
drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
|
/* Enforce sane interface api - has been abused by the fb helper. */ |
BUG_ON(!set->mode && set->fb); |
BUG_ON(set->fb && set->num_connectors == 0); |
if (put_domains) |
modeset_put_power_domains(dev_priv, put_domains); |
|
if (set->fb) { |
DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
set->crtc->base.id, set->fb->base.id, |
(int)set->num_connectors, set->x, set->y); |
} else { |
DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
intel_post_plane_update(intel_crtc); |
} |
|
dev = set->crtc->dev; |
/* FIXME: add subpixel order */ |
|
ret = -ENOMEM; |
config = kzalloc(sizeof(*config), GFP_KERNEL); |
if (!config) |
goto out_config; |
// drm_atomic_helper_wait_for_vblanks(dev, state); |
|
ret = intel_set_config_save_state(dev, config); |
if (ret) |
goto out_config; |
drm_atomic_helper_cleanup_planes(dev, state); |
|
save_set.crtc = set->crtc; |
save_set.mode = &set->crtc->mode; |
save_set.x = set->crtc->x; |
save_set.y = set->crtc->y; |
save_set.fb = set->crtc->primary->fb; |
if (any_ms) |
intel_modeset_check_state(dev, state); |
|
/* Compute whether we need a full modeset, only an fb base update or no |
* change at all. In the future we might also check whether only the |
* mode changed, e.g. for LVDS where we only change the panel fitter in |
* such cases. */ |
intel_set_config_compute_mode_changes(set, config); |
drm_atomic_state_free(state); |
|
ret = intel_modeset_stage_output_state(dev, set, config); |
if (ret) |
goto fail; |
return 0; |
} |
|
pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
set->fb, |
&modeset_pipes, |
&prepare_pipes, |
&disable_pipes); |
if (IS_ERR(pipe_config)) { |
ret = PTR_ERR(pipe_config); |
goto fail; |
} else if (pipe_config) { |
if (pipe_config->has_audio != |
to_intel_crtc(set->crtc)->config.has_audio) |
config->mode_changed = true; |
void intel_crtc_restore_mode(struct drm_crtc *crtc) |
{ |
struct drm_device *dev = crtc->dev; |
struct drm_atomic_state *state; |
struct drm_crtc_state *crtc_state; |
int ret; |
|
/* |
* Note we have an issue here with infoframes: current code |
* only updates them on the full mode set path per hw |
* requirements. So here we should be checking for any |
* required changes and forcing a mode set. |
*/ |
state = drm_atomic_state_alloc(dev); |
if (!state) { |
DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
crtc->base.id); |
return; |
} |
|
/* set_mode will free it in the mode_changed case */ |
if (!config->mode_changed) |
kfree(pipe_config); |
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
|
intel_update_pipe_size(to_intel_crtc(set->crtc)); |
retry: |
crtc_state = drm_atomic_get_crtc_state(state, crtc); |
ret = PTR_ERR_OR_ZERO(crtc_state); |
if (!ret) { |
if (!crtc_state->active) |
goto out; |
|
if (config->mode_changed) { |
ret = intel_set_mode_pipes(set->crtc, set->mode, |
set->x, set->y, set->fb, pipe_config, |
modeset_pipes, prepare_pipes, |
disable_pipes); |
} else if (config->fb_changed) { |
struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
|
// intel_crtc_wait_for_pending_flips(set->crtc); |
|
ret = intel_pipe_set_base(set->crtc, |
set->x, set->y, set->fb); |
|
/* |
* We need to make sure the primary plane is re-enabled if it |
* has previously been turned off. |
*/ |
if (!intel_crtc->primary_enabled && ret == 0) { |
WARN_ON(!intel_crtc->active); |
intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
crtc_state->mode_changed = true; |
ret = drm_atomic_commit(state); |
} |
|
/* |
* In the fastboot case this may be our only check of the |
* state after boot. It would be better to only do it on |
* the first update, but we don't have a nice way of doing that |
* (and really, set_config isn't used much for high freq page |
* flipping, so increasing its cost here shouldn't be a big |
* deal). |
*/ |
if (i915.fastboot && ret == 0) |
intel_modeset_check_state(set->crtc->dev); |
if (ret == -EDEADLK) { |
drm_atomic_state_clear(state); |
drm_modeset_backoff(state->acquire_ctx); |
goto retry; |
} |
|
if (ret) { |
DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
set->crtc->base.id, ret); |
fail: |
intel_set_config_restore_state(dev, config); |
|
/* |
* HACK: if the pipe was on, but we didn't have a framebuffer, |
* force the pipe off to avoid oopsing in the modeset code |
* due to fb==NULL. This should only happen during boot since |
* we don't yet reconstruct the FB from the hardware state. |
*/ |
if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
|
/* Try to restore the config */ |
if (config->mode_changed && |
intel_set_mode(save_set.crtc, save_set.mode, |
save_set.x, save_set.y, save_set.fb)) |
DRM_ERROR("failed to restore config after modeset failure\n"); |
if (ret) |
out: |
drm_atomic_state_free(state); |
} |
|
out_config: |
intel_set_config_free(config); |
return ret; |
} |
#undef for_each_intel_crtc_masked |
|
static const struct drm_crtc_funcs intel_crtc_funcs = { |
.gamma_set = intel_crtc_gamma_set, |
.set_config = intel_crtc_set_config, |
.set_config = drm_atomic_helper_set_config, |
.destroy = intel_crtc_destroy, |
// .page_flip = intel_crtc_page_flip, |
.atomic_duplicate_state = intel_crtc_duplicate_state, |
.atomic_destroy_state = intel_crtc_destroy_state, |
}; |
|
static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11524,91 → 13411,131 |
BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
} |
|
static int |
intel_primary_plane_disable(struct drm_plane *plane) |
/** |
* intel_prepare_plane_fb - Prepare fb for usage on plane |
* @plane: drm plane to prepare for |
* @fb: framebuffer to prepare for presentation |
* |
* Prepares a framebuffer for usage on a display plane. Generally this |
* involves pinning the underlying object and updating the frontbuffer tracking |
* bits. Some older platforms need special physical address handling for |
* cursor planes. |
* |
* Returns 0 on success, negative error code on failure. |
*/ |
int |
intel_prepare_plane_fb(struct drm_plane *plane, |
const struct drm_plane_state *new_state) |
{ |
struct drm_device *dev = plane->dev; |
struct intel_crtc *intel_crtc; |
struct drm_framebuffer *fb = new_state->fb; |
struct intel_plane *intel_plane = to_intel_plane(plane); |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
int ret = 0; |
|
if (!plane->fb) |
if (!obj) |
return 0; |
|
BUG_ON(!plane->crtc); |
mutex_lock(&dev->struct_mutex); |
|
intel_crtc = to_intel_crtc(plane->crtc); |
if (plane->type == DRM_PLANE_TYPE_CURSOR && |
INTEL_INFO(dev)->cursor_needs_physical) { |
int align = IS_I830(dev) ? 16 * 1024 : 256; |
ret = 1; |
if (ret) |
DRM_DEBUG_KMS("failed to attach phys object\n"); |
} else { |
ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
} |
|
/* |
* Even though we checked plane->fb above, it's still possible that |
* the primary plane has been implicitly disabled because the crtc |
* coordinates given weren't visible, or because we detected |
* that it was 100% covered by a sprite plane. Or, the CRTC may be |
* off and we've set a fb, but haven't actually turned on the CRTC yet. |
* In either case, we need to unpin the FB and let the fb pointer get |
* updated, but otherwise we don't need to touch the hardware. |
if (ret == 0) |
i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
|
mutex_unlock(&dev->struct_mutex); |
|
return ret; |
} |
|
/** |
* intel_cleanup_plane_fb - Cleans up an fb after plane use |
* @plane: drm plane to clean up for |
* @fb: old framebuffer that was on plane |
* |
* Cleans up a framebuffer that has just been removed from a plane. |
*/ |
if (!intel_crtc->primary_enabled) |
goto disable_unpin; |
void |
intel_cleanup_plane_fb(struct drm_plane *plane, |
const struct drm_plane_state *old_state) |
{ |
struct drm_device *dev = plane->dev; |
struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb); |
|
// intel_crtc_wait_for_pending_flips(plane->crtc); |
intel_disable_primary_hw_plane(plane, plane->crtc); |
if (!obj) |
return; |
|
disable_unpin: |
if (plane->type != DRM_PLANE_TYPE_CURSOR || |
!INTEL_INFO(dev)->cursor_needs_physical) { |
mutex_lock(&dev->struct_mutex); |
i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
intel_unpin_fb_obj(old_state->fb, old_state); |
mutex_unlock(&dev->struct_mutex); |
plane->fb = NULL; |
|
return 0; |
} |
} |
|
static int |
intel_check_primary_plane(struct drm_plane *plane, |
struct intel_plane_state *state) |
int |
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) |
{ |
struct drm_crtc *crtc = state->crtc; |
struct drm_framebuffer *fb = state->fb; |
struct drm_rect *dest = &state->dst; |
struct drm_rect *src = &state->src; |
const struct drm_rect *clip = &state->clip; |
int max_scale; |
struct drm_device *dev; |
struct drm_i915_private *dev_priv; |
int crtc_clock, cdclk; |
|
return drm_plane_helper_check_update(plane, crtc, fb, |
src, dest, clip, |
DRM_PLANE_HELPER_NO_SCALING, |
DRM_PLANE_HELPER_NO_SCALING, |
false, true, &state->visible); |
if (!intel_crtc || !crtc_state) |
return DRM_PLANE_HELPER_NO_SCALING; |
|
dev = intel_crtc->base.dev; |
dev_priv = dev->dev_private; |
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
|
if (!crtc_clock || !cdclk) |
return DRM_PLANE_HELPER_NO_SCALING; |
|
/* |
* skl max scale is lower of: |
* close to 3 but not 3, -1 is for that purpose |
* or |
* cdclk/crtc_clock |
*/ |
max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); |
|
return max_scale; |
} |
|
static int |
intel_prepare_primary_plane(struct drm_plane *plane, |
intel_check_primary_plane(struct drm_plane *plane, |
struct intel_crtc_state *crtc_state, |
struct intel_plane_state *state) |
{ |
struct drm_crtc *crtc = state->crtc; |
struct drm_framebuffer *fb = state->fb; |
struct drm_device *dev = crtc->dev; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
int ret; |
struct drm_crtc *crtc = state->base.crtc; |
struct drm_framebuffer *fb = state->base.fb; |
int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
bool can_position = false; |
|
|
|
if (old_obj != obj) { |
mutex_lock(&dev->struct_mutex); |
ret = intel_pin_and_fence_fb_obj(plane, fb, NULL); |
if (ret == 0) |
i915_gem_track_fb(old_obj, obj, |
INTEL_FRONTBUFFER_PRIMARY(pipe)); |
mutex_unlock(&dev->struct_mutex); |
if (ret != 0) { |
DRM_DEBUG_KMS("pin & fence failed\n"); |
return ret; |
/* use scaler when colorkey is not required */ |
if (INTEL_INFO(plane->dev)->gen >= 9 && |
state->ckey.flags == I915_SET_COLORKEY_NONE) { |
min_scale = 1; |
max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); |
can_position = true; |
} |
} |
|
return 0; |
return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
&state->dst, &state->clip, |
min_scale, max_scale, |
can_position, true, |
&state->visible); |
} |
|
static void |
11615,145 → 13542,80 |
intel_commit_primary_plane(struct drm_plane *plane, |
struct intel_plane_state *state) |
{ |
struct drm_crtc *crtc = state->crtc; |
struct drm_framebuffer *fb = state->fb; |
struct drm_device *dev = crtc->dev; |
struct drm_crtc *crtc = state->base.crtc; |
struct drm_framebuffer *fb = state->base.fb; |
struct drm_device *dev = plane->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
enum pipe pipe = intel_crtc->pipe; |
struct drm_framebuffer *old_fb = plane->fb; |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
struct intel_plane *intel_plane = to_intel_plane(plane); |
struct intel_crtc *intel_crtc; |
struct drm_rect *src = &state->src; |
|
crtc->primary->fb = fb; |
crtc = crtc ? crtc : plane->crtc; |
intel_crtc = to_intel_crtc(crtc); |
|
plane->fb = fb; |
crtc->x = src->x1 >> 16; |
crtc->y = src->y1 >> 16; |
|
intel_plane->crtc_x = state->orig_dst.x1; |
intel_plane->crtc_y = state->orig_dst.y1; |
intel_plane->crtc_w = drm_rect_width(&state->orig_dst); |
intel_plane->crtc_h = drm_rect_height(&state->orig_dst); |
intel_plane->src_x = state->orig_src.x1; |
intel_plane->src_y = state->orig_src.y1; |
intel_plane->src_w = drm_rect_width(&state->orig_src); |
intel_plane->src_h = drm_rect_height(&state->orig_src); |
intel_plane->obj = obj; |
if (!crtc->state->active) |
return; |
|
if (intel_crtc->active) { |
/* |
* FBC does not work on some platforms for rotated |
* planes, so disable it when rotation is not 0 and |
* update it when rotation is set back to 0. |
* |
* FIXME: This is redundant with the fbc update done in |
* the primary plane enable function except that that |
* one is done too late. We eventually need to unify |
* this. |
*/ |
if (intel_crtc->primary_enabled && |
INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
dev_priv->fbc.plane == intel_crtc->plane && |
intel_plane->rotation != BIT(DRM_ROTATE_0)) { |
intel_disable_fbc(dev); |
dev_priv->display.update_primary_plane(crtc, fb, |
state->src.x1 >> 16, |
state->src.y1 >> 16); |
} |
|
if (state->visible) { |
bool was_enabled = intel_crtc->primary_enabled; |
static void |
intel_disable_primary_plane(struct drm_plane *plane, |
struct drm_crtc *crtc) |
{ |
struct drm_device *dev = plane->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
/* FIXME: kill this fastboot hack */ |
intel_update_pipe_size(intel_crtc); |
dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
} |
|
intel_crtc->primary_enabled = true; |
static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
struct drm_crtc_state *old_crtc_state) |
{ |
struct drm_device *dev = crtc->dev; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_crtc_state *old_intel_state = |
to_intel_crtc_state(old_crtc_state); |
bool modeset = needs_modeset(crtc->state); |
|
dev_priv->display.update_primary_plane(crtc, plane->fb, |
crtc->x, crtc->y); |
if (intel_crtc->atomic.update_wm_pre) |
intel_update_watermarks(crtc); |
|
/* |
* BDW signals flip done immediately if the plane |
* is disabled, even if the plane enable is already |
* armed to occur at the next vblank :( |
*/ |
if (IS_BROADWELL(dev) && !was_enabled) |
intel_wait_for_vblank(dev, intel_crtc->pipe); |
} else { |
/* |
* If clipping results in a non-visible primary plane, |
* we'll disable the primary plane. Note that this is |
* a bit different than what happens if userspace |
* explicitly disables the plane by passing fb=0 |
* because plane->fb still gets set and pinned. |
*/ |
intel_disable_primary_hw_plane(plane, crtc); |
} |
/* Perform vblank evasion around commit operation */ |
if (crtc->state->active) |
intel_pipe_update_start(intel_crtc); |
|
intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
if (modeset) |
return; |
|
mutex_lock(&dev->struct_mutex); |
intel_update_fbc(dev); |
mutex_unlock(&dev->struct_mutex); |
if (to_intel_crtc_state(crtc->state)->update_pipe) |
intel_update_pipe_config(intel_crtc, old_intel_state); |
else if (INTEL_INFO(dev)->gen >= 9) |
skl_detach_scalers(intel_crtc); |
} |
|
if (old_fb && old_fb != fb) { |
if (intel_crtc->active) |
intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
mutex_lock(&dev->struct_mutex); |
intel_unpin_fb_obj(old_obj); |
mutex_unlock(&dev->struct_mutex); |
} |
} |
|
static int |
intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, |
struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
unsigned int crtc_w, unsigned int crtc_h, |
uint32_t src_x, uint32_t src_y, |
uint32_t src_w, uint32_t src_h) |
static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
struct drm_crtc_state *old_crtc_state) |
{ |
struct intel_plane_state state; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int ret; |
|
state.crtc = crtc; |
state.fb = fb; |
|
/* sample coordinates in 16.16 fixed point */ |
state.src.x1 = src_x; |
state.src.x2 = src_x + src_w; |
state.src.y1 = src_y; |
state.src.y2 = src_y + src_h; |
|
/* integer pixels */ |
state.dst.x1 = crtc_x; |
state.dst.x2 = crtc_x + crtc_w; |
state.dst.y1 = crtc_y; |
state.dst.y2 = crtc_y + crtc_h; |
|
state.clip.x1 = 0; |
state.clip.y1 = 0; |
state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; |
state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; |
|
state.orig_src = state.src; |
state.orig_dst = state.dst; |
|
ret = intel_check_primary_plane(plane, &state); |
if (ret) |
return ret; |
|
ret = intel_prepare_primary_plane(plane, &state); |
if (ret) |
return ret; |
|
intel_commit_primary_plane(plane, &state); |
|
return 0; |
if (crtc->state->active) |
intel_pipe_update_end(intel_crtc); |
} |
|
/* Common destruction function for both primary and cursor planes */ |
static void intel_plane_destroy(struct drm_plane *plane) |
/** |
* intel_plane_destroy - destroy a plane |
* @plane: plane to destroy |
* |
* Common destruction function for all types of planes (primary, cursor, |
* sprite). |
*/ |
void intel_plane_destroy(struct drm_plane *plane) |
{ |
struct intel_plane *intel_plane = to_intel_plane(plane); |
drm_plane_cleanup(plane); |
11760,11 → 13622,16 |
kfree(intel_plane); |
} |
|
static const struct drm_plane_funcs intel_primary_plane_funcs = { |
.update_plane = intel_primary_plane_setplane, |
.disable_plane = intel_primary_plane_disable, |
const struct drm_plane_funcs intel_plane_funcs = { |
.update_plane = drm_atomic_helper_update_plane, |
.disable_plane = drm_atomic_helper_disable_plane, |
.destroy = intel_plane_destroy, |
.set_property = intel_plane_set_property |
.set_property = drm_atomic_helper_plane_set_property, |
.atomic_get_property = intel_plane_atomic_get_property, |
.atomic_set_property = intel_plane_atomic_set_property, |
.atomic_duplicate_state = intel_plane_duplicate_state, |
.atomic_destroy_state = intel_plane_destroy_state, |
|
}; |
|
static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, |
11771,77 → 13638,92 |
int pipe) |
{ |
struct intel_plane *primary; |
struct intel_plane_state *state; |
const uint32_t *intel_primary_formats; |
int num_formats; |
unsigned int num_formats; |
|
primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
if (primary == NULL) |
return NULL; |
|
state = intel_create_plane_state(&primary->base); |
if (!state) { |
kfree(primary); |
return NULL; |
} |
primary->base.state = &state->base; |
|
primary->can_scale = false; |
primary->max_downscale = 1; |
if (INTEL_INFO(dev)->gen >= 9) { |
primary->can_scale = true; |
state->scaler_id = -1; |
} |
primary->pipe = pipe; |
primary->plane = pipe; |
primary->rotation = BIT(DRM_ROTATE_0); |
primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
primary->check_plane = intel_check_primary_plane; |
primary->commit_plane = intel_commit_primary_plane; |
primary->disable_plane = intel_disable_primary_plane; |
if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
primary->plane = !pipe; |
|
if (INTEL_INFO(dev)->gen <= 3) { |
intel_primary_formats = intel_primary_formats_gen2; |
num_formats = ARRAY_SIZE(intel_primary_formats_gen2); |
if (INTEL_INFO(dev)->gen >= 9) { |
intel_primary_formats = skl_primary_formats; |
num_formats = ARRAY_SIZE(skl_primary_formats); |
} else if (INTEL_INFO(dev)->gen >= 4) { |
intel_primary_formats = i965_primary_formats; |
num_formats = ARRAY_SIZE(i965_primary_formats); |
} else { |
intel_primary_formats = intel_primary_formats_gen4; |
num_formats = ARRAY_SIZE(intel_primary_formats_gen4); |
intel_primary_formats = i8xx_primary_formats; |
num_formats = ARRAY_SIZE(i8xx_primary_formats); |
} |
|
drm_universal_plane_init(dev, &primary->base, 0, |
&intel_primary_plane_funcs, |
&intel_plane_funcs, |
intel_primary_formats, num_formats, |
DRM_PLANE_TYPE_PRIMARY); |
|
if (INTEL_INFO(dev)->gen >= 4) { |
if (!dev->mode_config.rotation_property) |
dev->mode_config.rotation_property = |
drm_mode_create_rotation_property(dev, |
BIT(DRM_ROTATE_0) | |
BIT(DRM_ROTATE_180)); |
if (dev->mode_config.rotation_property) |
drm_object_attach_property(&primary->base.base, |
dev->mode_config.rotation_property, |
primary->rotation); |
} |
if (INTEL_INFO(dev)->gen >= 4) |
intel_create_rotation_property(dev, primary); |
|
drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
|
return &primary->base; |
} |
|
static int |
intel_cursor_plane_disable(struct drm_plane *plane) |
void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
{ |
if (!plane->fb) |
return 0; |
if (!dev->mode_config.rotation_property) { |
unsigned long flags = BIT(DRM_ROTATE_0) | |
BIT(DRM_ROTATE_180); |
|
BUG_ON(!plane->crtc); |
if (INTEL_INFO(dev)->gen >= 9) |
flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); |
|
return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); |
dev->mode_config.rotation_property = |
drm_mode_create_rotation_property(dev, flags); |
} |
if (dev->mode_config.rotation_property) |
drm_object_attach_property(&plane->base.base, |
dev->mode_config.rotation_property, |
plane->base.state->rotation); |
} |
|
static int |
intel_check_cursor_plane(struct drm_plane *plane, |
struct intel_crtc_state *crtc_state, |
struct intel_plane_state *state) |
{ |
struct drm_crtc *crtc = state->crtc; |
struct drm_device *dev = crtc->dev; |
struct drm_framebuffer *fb = state->fb; |
struct drm_rect *dest = &state->dst; |
struct drm_rect *src = &state->src; |
const struct drm_rect *clip = &state->clip; |
struct drm_crtc *crtc = crtc_state->base.crtc; |
struct drm_framebuffer *fb = state->base.fb; |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
int crtc_w, crtc_h; |
enum pipe pipe = to_intel_plane(plane)->pipe; |
unsigned stride; |
int ret; |
|
ret = drm_plane_helper_check_update(plane, crtc, fb, |
src, dest, clip, |
ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
&state->dst, &state->clip, |
DRM_PLANE_HELPER_NO_SCALING, |
DRM_PLANE_HELPER_NO_SCALING, |
true, true, &state->visible); |
11848,141 → 13730,108 |
if (ret) |
return ret; |
|
|
/* if we want to turn off the cursor ignore width and height */ |
if (!obj) |
return 0; |
|
/* Check for which cursor types we support */ |
crtc_w = drm_rect_width(&state->orig_dst); |
crtc_h = drm_rect_height(&state->orig_dst); |
if (!cursor_size_ok(dev, crtc_w, crtc_h)) { |
DRM_DEBUG("Cursor dimension not supported\n"); |
if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
state->base.crtc_w, state->base.crtc_h); |
return -EINVAL; |
} |
|
stride = roundup_pow_of_two(crtc_w) * 4; |
if (obj->base.size < stride * crtc_h) { |
stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
if (obj->base.size < stride * state->base.crtc_h) { |
DRM_DEBUG_KMS("buffer is too small\n"); |
return -ENOMEM; |
} |
|
if (fb == crtc->cursor->fb) |
return 0; |
|
/* we only need to pin inside GTT if cursor is non-phy */ |
mutex_lock(&dev->struct_mutex); |
if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { |
if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
ret = -EINVAL; |
return -EINVAL; |
} |
mutex_unlock(&dev->struct_mutex); |
|
return ret; |
/* |
* There's something wrong with the cursor on CHV pipe C. |
* If it straddles the left edge of the screen then |
* moving it away from the edge or disabling it often |
* results in a pipe underrun, and often that can lead to |
* dead pipe (constant underrun reported, and it scans |
* out just a solid color). To recover from that, the |
* display power well must be turned off and on again. |
* Refuse the put the cursor into that compromised position. |
*/ |
if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && |
state->visible && state->base.crtc_x < 0) { |
DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
return -EINVAL; |
} |
|
static int |
intel_commit_cursor_plane(struct drm_plane *plane, |
struct intel_plane_state *state) |
{ |
struct drm_crtc *crtc = state->crtc; |
struct drm_framebuffer *fb = state->fb; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_plane *intel_plane = to_intel_plane(plane); |
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
struct drm_i915_gem_object *obj = intel_fb->obj; |
int crtc_w, crtc_h; |
|
crtc->cursor_x = state->orig_dst.x1; |
crtc->cursor_y = state->orig_dst.y1; |
|
intel_plane->crtc_x = state->orig_dst.x1; |
intel_plane->crtc_y = state->orig_dst.y1; |
intel_plane->crtc_w = drm_rect_width(&state->orig_dst); |
intel_plane->crtc_h = drm_rect_height(&state->orig_dst); |
intel_plane->src_x = state->orig_src.x1; |
intel_plane->src_y = state->orig_src.y1; |
intel_plane->src_w = drm_rect_width(&state->orig_src); |
intel_plane->src_h = drm_rect_height(&state->orig_src); |
intel_plane->obj = obj; |
|
if (fb != crtc->cursor->fb) { |
crtc_w = drm_rect_width(&state->orig_dst); |
crtc_h = drm_rect_height(&state->orig_dst); |
return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
} else { |
intel_crtc_update_cursor(crtc, state->visible); |
|
|
return 0; |
} |
|
static void |
intel_disable_cursor_plane(struct drm_plane *plane, |
struct drm_crtc *crtc) |
{ |
intel_crtc_update_cursor(crtc, false); |
} |
|
static int |
intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, |
struct drm_framebuffer *fb, int crtc_x, int crtc_y, |
unsigned int crtc_w, unsigned int crtc_h, |
uint32_t src_x, uint32_t src_y, |
uint32_t src_w, uint32_t src_h) |
static void |
intel_commit_cursor_plane(struct drm_plane *plane, |
struct intel_plane_state *state) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_plane_state state; |
int ret; |
struct drm_crtc *crtc = state->base.crtc; |
struct drm_device *dev = plane->dev; |
struct intel_crtc *intel_crtc; |
struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
uint32_t addr; |
|
state.crtc = crtc; |
state.fb = fb; |
crtc = crtc ? crtc : plane->crtc; |
intel_crtc = to_intel_crtc(crtc); |
|
/* sample coordinates in 16.16 fixed point */ |
state.src.x1 = src_x; |
state.src.x2 = src_x + src_w; |
state.src.y1 = src_y; |
state.src.y2 = src_y + src_h; |
if (!obj) |
addr = 0; |
else if (!INTEL_INFO(dev)->cursor_needs_physical) |
addr = i915_gem_obj_ggtt_offset(obj); |
else |
addr = obj->phys_handle->busaddr; |
|
/* integer pixels */ |
state.dst.x1 = crtc_x; |
state.dst.x2 = crtc_x + crtc_w; |
state.dst.y1 = crtc_y; |
state.dst.y2 = crtc_y + crtc_h; |
intel_crtc->cursor_addr = addr; |
|
state.clip.x1 = 0; |
state.clip.y1 = 0; |
state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; |
state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; |
|
state.orig_src = state.src; |
state.orig_dst = state.dst; |
|
ret = intel_check_cursor_plane(plane, &state); |
if (ret) |
return ret; |
|
return intel_commit_cursor_plane(plane, &state); |
if (crtc->state->active) |
intel_crtc_update_cursor(crtc, state->visible); |
} |
|
static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
.update_plane = intel_cursor_plane_update, |
.disable_plane = intel_cursor_plane_disable, |
.destroy = intel_plane_destroy, |
.set_property = intel_plane_set_property, |
}; |
|
static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
int pipe) |
{ |
struct intel_plane *cursor; |
struct intel_plane_state *state; |
|
cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); |
if (cursor == NULL) |
return NULL; |
|
state = intel_create_plane_state(&cursor->base); |
if (!state) { |
kfree(cursor); |
return NULL; |
} |
cursor->base.state = &state->base; |
|
cursor->can_scale = false; |
cursor->max_downscale = 1; |
cursor->pipe = pipe; |
cursor->plane = pipe; |
cursor->rotation = BIT(DRM_ROTATE_0); |
cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
cursor->check_plane = intel_check_cursor_plane; |
cursor->commit_plane = intel_commit_cursor_plane; |
cursor->disable_plane = intel_disable_cursor_plane; |
|
drm_universal_plane_init(dev, &cursor->base, 0, |
&intel_cursor_plane_funcs, |
&intel_plane_funcs, |
intel_cursor_formats, |
ARRAY_SIZE(intel_cursor_formats), |
DRM_PLANE_TYPE_CURSOR); |
11996,16 → 13845,38 |
if (dev->mode_config.rotation_property) |
drm_object_attach_property(&cursor->base.base, |
dev->mode_config.rotation_property, |
cursor->rotation); |
state->base.rotation); |
} |
|
if (INTEL_INFO(dev)->gen >=9) |
state->scaler_id = -1; |
|
drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
|
return &cursor->base; |
} |
|
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
struct intel_crtc_state *crtc_state) |
{ |
int i; |
struct intel_scaler *intel_scaler; |
struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; |
|
for (i = 0; i < intel_crtc->num_scalers; i++) { |
intel_scaler = &scaler_state->scalers[i]; |
intel_scaler->in_use = 0; |
intel_scaler->mode = PS_SCALER_MODE_DYN; |
} |
|
scaler_state->scaler_id = -1; |
} |
|
static void intel_crtc_init(struct drm_device *dev, int pipe) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc; |
struct intel_crtc_state *crtc_state = NULL; |
struct drm_plane *primary = NULL; |
struct drm_plane *cursor = NULL; |
int i, ret; |
12014,6 → 13885,23 |
if (intel_crtc == NULL) |
return; |
|
crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
if (!crtc_state) |
goto fail; |
intel_crtc->config = crtc_state; |
intel_crtc->base.state = &crtc_state->base; |
crtc_state->base.crtc = &intel_crtc->base; |
|
/* initialize shared scalers */ |
if (INTEL_INFO(dev)->gen >= 9) { |
if (pipe == PIPE_C) |
intel_crtc->num_scalers = 1; |
else |
intel_crtc->num_scalers = SKL_NUM_SCALERS; |
|
skl_init_scalers(dev, intel_crtc, crtc_state); |
} |
|
primary = intel_primary_plane_create(dev, pipe); |
if (!primary) |
goto fail; |
12049,6 → 13937,8 |
intel_crtc->cursor_cntl = ~0; |
intel_crtc->cursor_size = ~0; |
|
intel_crtc->wm.cxsr_allowed = true; |
|
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
12064,6 → 13954,7 |
drm_plane_cleanup(primary); |
if (cursor) |
drm_plane_cleanup(cursor); |
kfree(crtc_state); |
kfree(intel_crtc); |
} |
|
12087,9 → 13978,6 |
struct drm_crtc *drmmode_crtc; |
struct intel_crtc *crtc; |
|
if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
return -ENODEV; |
|
drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
|
if (!drmmode_crtc) { |
12136,28 → 14024,6 |
return true; |
} |
|
const char *intel_output_name(int output) |
{ |
static const char *names[] = { |
[INTEL_OUTPUT_UNUSED] = "Unused", |
[INTEL_OUTPUT_ANALOG] = "Analog", |
[INTEL_OUTPUT_DVO] = "DVO", |
[INTEL_OUTPUT_SDVO] = "SDVO", |
[INTEL_OUTPUT_LVDS] = "LVDS", |
[INTEL_OUTPUT_TVOUT] = "TV", |
[INTEL_OUTPUT_HDMI] = "HDMI", |
[INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
[INTEL_OUTPUT_EDP] = "eDP", |
[INTEL_OUTPUT_DSI] = "DSI", |
[INTEL_OUTPUT_UNKNOWN] = "Unknown", |
}; |
|
if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
return "Invalid"; |
|
return names[output]; |
} |
|
static bool intel_crt_present(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
12188,13 → 14054,26 |
if (intel_crt_present(dev)) |
intel_crt_init(dev); |
|
if (HAS_DDI(dev)) { |
if (IS_BROXTON(dev)) { |
/* |
* FIXME: Broxton doesn't support port detection via the |
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to |
* detect the ports. |
*/ |
intel_ddi_init(dev, PORT_A); |
intel_ddi_init(dev, PORT_B); |
intel_ddi_init(dev, PORT_C); |
} else if (HAS_DDI(dev)) { |
int found; |
|
/* Haswell uses DDI functions to detect digital outputs */ |
found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
/* DDI A only supports eDP */ |
if (found) |
/* |
* Haswell uses DDI functions to detect digital outputs. |
* On SKL pre-D0 the strap isn't connected, so we assume |
* it's there. |
*/ |
found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
/* WaIgnoreDDIAStrap: skl */ |
if (found || IS_SKYLAKE(dev)) |
intel_ddi_init(dev, PORT_A); |
|
/* DDI B, C and D detection is indicated by the SFUSE_STRAP |
12207,6 → 14086,15 |
intel_ddi_init(dev, PORT_C); |
if (found & SFUSE_STRAP_DDID_DETECTED) |
intel_ddi_init(dev, PORT_D); |
/* |
* On SKL we don't have a way to detect DDI-E so we rely on VBT. |
*/ |
if (IS_SKYLAKE(dev) && |
(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || |
dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) |
intel_ddi_init(dev, PORT_E); |
|
} else if (HAS_PCH_SPLIT(dev)) { |
int found; |
dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
12244,42 → 14132,41 |
* eDP ports. Consult the VBT as well as DP_DETECTED to |
* detect eDP ports. |
*/ |
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) |
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
PORT_B); |
if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
!intel_dp_is_edp(dev, PORT_B)) |
intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
if (I915_READ(VLV_DP_B) & DP_DETECTED || |
intel_dp_is_edp(dev, PORT_B)) |
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
intel_dp_init(dev, VLV_DP_B, PORT_B); |
|
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) |
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
PORT_C); |
if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
!intel_dp_is_edp(dev, PORT_C)) |
intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
if (I915_READ(VLV_DP_C) & DP_DETECTED || |
intel_dp_is_edp(dev, PORT_C)) |
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
intel_dp_init(dev, VLV_DP_C, PORT_C); |
|
if (IS_CHERRYVIEW(dev)) { |
if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
PORT_D); |
/* eDP not supported on port D, so don't check VBT */ |
if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) |
intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); |
if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
intel_hdmi_init(dev, CHV_HDMID, PORT_D); |
if (I915_READ(CHV_DP_D) & DP_DETECTED) |
intel_dp_init(dev, CHV_DP_D, PORT_D); |
} |
|
intel_dsi_init(dev); |
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
bool found = false; |
|
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
DRM_DEBUG_KMS("probing SDVOB\n"); |
found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
if (!found && IS_G4X(dev)) { |
DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
} |
|
if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
if (!found && IS_G4X(dev)) |
intel_dp_init(dev, DP_B, PORT_B); |
} |
|
12292,21 → 14179,20 |
|
if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
|
if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
if (IS_G4X(dev)) { |
DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
} |
if (SUPPORTS_INTEGRATED_DP(dev)) |
if (IS_G4X(dev)) |
intel_dp_init(dev, DP_C, PORT_C); |
} |
|
if (SUPPORTS_INTEGRATED_DP(dev) && |
if (IS_G4X(dev) && |
(I915_READ(DP_D) & DP_DETECTED)) |
intel_dp_init(dev, DP_D, PORT_D); |
} else if (IS_GEN2(dev)) |
intel_dvo_init(dev); |
|
|
intel_psr_init(dev); |
|
for_each_intel_encoder(dev, encoder) { |
12320,59 → 14206,151 |
drm_helper_move_panel_connectors_to_head(dev); |
} |
|
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
{ |
struct drm_device *dev = fb->dev; |
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
|
drm_framebuffer_cleanup(fb); |
mutex_lock(&dev->struct_mutex); |
WARN_ON(!intel_fb->obj->framebuffer_references--); |
drm_gem_object_unreference(&intel_fb->obj->base); |
mutex_unlock(&dev->struct_mutex); |
kfree(intel_fb); |
} |
|
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
struct drm_file *file, |
unsigned int *handle) |
{ |
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
struct drm_i915_gem_object *obj = intel_fb->obj; |
|
if (obj->userptr.mm) { |
DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); |
return -EINVAL; |
} |
|
return drm_gem_handle_create(file, &obj->base, handle); |
} |
|
static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
struct drm_file *file, |
unsigned flags, unsigned color, |
struct drm_clip_rect *clips, |
unsigned num_clips) |
{ |
struct drm_device *dev = fb->dev; |
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
struct drm_i915_gem_object *obj = intel_fb->obj; |
|
mutex_lock(&dev->struct_mutex); |
intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
mutex_unlock(&dev->struct_mutex); |
|
return 0; |
} |
|
static const struct drm_framebuffer_funcs intel_fb_funcs = { |
// .destroy = intel_user_framebuffer_destroy, |
// .create_handle = intel_user_framebuffer_create_handle, |
.destroy = intel_user_framebuffer_destroy, |
.create_handle = intel_user_framebuffer_create_handle, |
.dirty = intel_user_framebuffer_dirty, |
}; |
|
static |
u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, |
uint32_t pixel_format) |
{ |
u32 gen = INTEL_INFO(dev)->gen; |
|
if (gen >= 9) { |
/* "The stride in bytes must not exceed the of the size of 8K |
* pixels and 32K bytes." |
*/ |
return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { |
return 32*1024; |
} else if (gen >= 4) { |
if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
return 16*1024; |
else |
return 32*1024; |
} else if (gen >= 3) { |
if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
return 8*1024; |
else |
return 16*1024; |
} else { |
/* XXX DSPC is limited to 4k tiled */ |
return 8*1024; |
} |
} |
|
static int intel_framebuffer_init(struct drm_device *dev, |
struct intel_framebuffer *intel_fb, |
struct drm_mode_fb_cmd2 *mode_cmd, |
struct drm_i915_gem_object *obj) |
{ |
int aligned_height; |
int pitch_limit; |
unsigned int aligned_height; |
int ret; |
u32 pitch_limit, stride_alignment; |
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
|
if (obj->tiling_mode == I915_TILING_Y) { |
DRM_DEBUG("hardware does not support tiling Y\n"); |
if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
/* Enforce that fb modifier and tiling mode match, but only for |
* X-tiled. This is needed for FBC. */ |
if (!!(obj->tiling_mode == I915_TILING_X) != |
!!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
return -EINVAL; |
} |
} else { |
if (obj->tiling_mode == I915_TILING_X) |
mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
else if (obj->tiling_mode == I915_TILING_Y) { |
DRM_DEBUG("No Y tiling for legacy addfb\n"); |
return -EINVAL; |
} |
} |
|
if (mode_cmd->pitches[0] & 63) { |
DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
mode_cmd->pitches[0]); |
/* Passed in modifier sanity checking. */ |
switch (mode_cmd->modifier[0]) { |
case I915_FORMAT_MOD_Y_TILED: |
case I915_FORMAT_MOD_Yf_TILED: |
if (INTEL_INFO(dev)->gen < 9) { |
DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
mode_cmd->modifier[0]); |
return -EINVAL; |
} |
case DRM_FORMAT_MOD_NONE: |
case I915_FORMAT_MOD_X_TILED: |
break; |
default: |
DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
mode_cmd->modifier[0]); |
return -EINVAL; |
} |
|
if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
pitch_limit = 32*1024; |
} else if (INTEL_INFO(dev)->gen >= 4) { |
if (obj->tiling_mode) |
pitch_limit = 16*1024; |
else |
pitch_limit = 32*1024; |
} else if (INTEL_INFO(dev)->gen >= 3) { |
if (obj->tiling_mode) |
pitch_limit = 8*1024; |
else |
pitch_limit = 16*1024; |
} else |
/* XXX DSPC is limited to 4k tiled */ |
pitch_limit = 8*1024; |
stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
mode_cmd->pixel_format); |
if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
mode_cmd->pitches[0], stride_alignment); |
return -EINVAL; |
} |
|
pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
mode_cmd->pixel_format); |
if (mode_cmd->pitches[0] > pitch_limit) { |
DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
obj->tiling_mode ? "tiled" : "linear", |
DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? |
"tiled" : "linear", |
mode_cmd->pitches[0], pitch_limit); |
return -EINVAL; |
} |
|
if (obj->tiling_mode != I915_TILING_NONE && |
if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
mode_cmd->pitches[0] != obj->stride) { |
DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
mode_cmd->pitches[0], obj->stride); |
12387,7 → 14365,6 |
case DRM_FORMAT_ARGB8888: |
break; |
case DRM_FORMAT_XRGB1555: |
case DRM_FORMAT_ARGB1555: |
if (INTEL_INFO(dev)->gen > 3) { |
DRM_DEBUG("unsupported pixel format: %s\n", |
drm_get_format_name(mode_cmd->pixel_format)); |
12394,12 → 14371,16 |
return -EINVAL; |
} |
break; |
case DRM_FORMAT_ABGR8888: |
if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
DRM_DEBUG("unsupported pixel format: %s\n", |
drm_get_format_name(mode_cmd->pixel_format)); |
return -EINVAL; |
} |
break; |
case DRM_FORMAT_XBGR8888: |
case DRM_FORMAT_ABGR8888: |
case DRM_FORMAT_XRGB2101010: |
case DRM_FORMAT_ARGB2101010: |
case DRM_FORMAT_XBGR2101010: |
case DRM_FORMAT_ABGR2101010: |
if (INTEL_INFO(dev)->gen < 4) { |
DRM_DEBUG("unsupported pixel format: %s\n", |
drm_get_format_name(mode_cmd->pixel_format)); |
12406,6 → 14387,13 |
return -EINVAL; |
} |
break; |
case DRM_FORMAT_ABGR2101010: |
if (!IS_VALLEYVIEW(dev)) { |
DRM_DEBUG("unsupported pixel format: %s\n", |
drm_get_format_name(mode_cmd->pixel_format)); |
return -EINVAL; |
} |
break; |
case DRM_FORMAT_YUYV: |
case DRM_FORMAT_UYVY: |
case DRM_FORMAT_YVYU: |
12426,8 → 14414,9 |
if (mode_cmd->offsets[0] != 0) |
return -EINVAL; |
|
aligned_height = intel_align_height(dev, mode_cmd->height, |
obj->tiling_mode); |
aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
mode_cmd->pixel_format, |
mode_cmd->modifier[0]); |
/* FIXME drm helper for size checks (especially planar formats)? */ |
if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
return -EINVAL; |
12445,7 → 14434,23 |
return 0; |
} |
|
#ifndef CONFIG_DRM_I915_FBDEV |
static struct drm_framebuffer * |
intel_user_framebuffer_create(struct drm_device *dev, |
struct drm_file *filp, |
struct drm_mode_fb_cmd2 *user_mode_cmd) |
{ |
struct drm_i915_gem_object *obj; |
struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
|
obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
mode_cmd.handles[0])); |
if (&obj->base == NULL) |
return ERR_PTR(-ENOENT); |
|
return intel_framebuffer_create(dev, &mode_cmd, obj); |
} |
|
#ifndef CONFIG_DRM_FBDEV_EMULATION |
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
{ |
} |
12452,8 → 14457,12 |
#endif |
|
static const struct drm_mode_config_funcs intel_mode_funcs = { |
.fb_create = NULL, |
.fb_create = intel_user_framebuffer_create, |
.output_poll_changed = intel_fbdev_output_poll_changed, |
.atomic_check = intel_atomic_check, |
.atomic_commit = intel_atomic_commit, |
.atomic_state_alloc = intel_atomic_state_alloc, |
.atomic_state_clear = intel_atomic_state_clear, |
}; |
|
/* Set up chip specific display functions */ |
12472,57 → 14481,91 |
else |
dev_priv->display.find_dpll = i9xx_find_best_dpll; |
|
if (HAS_DDI(dev)) { |
if (INTEL_INFO(dev)->gen >= 9) { |
dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
dev_priv->display.get_plane_config = ironlake_get_plane_config; |
dev_priv->display.get_initial_plane_config = |
skylake_get_initial_plane_config; |
dev_priv->display.crtc_compute_clock = |
haswell_crtc_compute_clock; |
dev_priv->display.crtc_enable = haswell_crtc_enable; |
dev_priv->display.crtc_disable = haswell_crtc_disable; |
dev_priv->display.off = ironlake_crtc_off; |
if (INTEL_INFO(dev)->gen >= 9) |
dev_priv->display.update_primary_plane = |
skylake_update_primary_plane; |
else |
} else if (HAS_DDI(dev)) { |
dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
dev_priv->display.get_initial_plane_config = |
ironlake_get_initial_plane_config; |
dev_priv->display.crtc_compute_clock = |
haswell_crtc_compute_clock; |
dev_priv->display.crtc_enable = haswell_crtc_enable; |
dev_priv->display.crtc_disable = haswell_crtc_disable; |
dev_priv->display.update_primary_plane = |
ironlake_update_primary_plane; |
} else if (HAS_PCH_SPLIT(dev)) { |
dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
dev_priv->display.get_plane_config = ironlake_get_plane_config; |
dev_priv->display.get_initial_plane_config = |
ironlake_get_initial_plane_config; |
dev_priv->display.crtc_compute_clock = |
ironlake_crtc_compute_clock; |
dev_priv->display.crtc_enable = ironlake_crtc_enable; |
dev_priv->display.crtc_disable = ironlake_crtc_disable; |
dev_priv->display.off = ironlake_crtc_off; |
dev_priv->display.update_primary_plane = |
ironlake_update_primary_plane; |
} else if (IS_VALLEYVIEW(dev)) { |
dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
dev_priv->display.get_plane_config = i9xx_get_plane_config; |
dev_priv->display.get_initial_plane_config = |
i9xx_get_initial_plane_config; |
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
dev_priv->display.crtc_enable = valleyview_crtc_enable; |
dev_priv->display.crtc_disable = i9xx_crtc_disable; |
dev_priv->display.off = i9xx_crtc_off; |
dev_priv->display.update_primary_plane = |
i9xx_update_primary_plane; |
} else { |
dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
dev_priv->display.get_plane_config = i9xx_get_plane_config; |
dev_priv->display.get_initial_plane_config = |
i9xx_get_initial_plane_config; |
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
dev_priv->display.crtc_enable = i9xx_crtc_enable; |
dev_priv->display.crtc_disable = i9xx_crtc_disable; |
dev_priv->display.off = i9xx_crtc_off; |
dev_priv->display.update_primary_plane = |
i9xx_update_primary_plane; |
} |
|
/* Returns the core display clock speed */ |
if (IS_VALLEYVIEW(dev)) |
if (IS_SKYLAKE(dev)) |
dev_priv->display.get_display_clock_speed = |
skylake_get_display_clock_speed; |
else if (IS_BROXTON(dev)) |
dev_priv->display.get_display_clock_speed = |
broxton_get_display_clock_speed; |
else if (IS_BROADWELL(dev)) |
dev_priv->display.get_display_clock_speed = |
broadwell_get_display_clock_speed; |
else if (IS_HASWELL(dev)) |
dev_priv->display.get_display_clock_speed = |
haswell_get_display_clock_speed; |
else if (IS_VALLEYVIEW(dev)) |
dev_priv->display.get_display_clock_speed = |
valleyview_get_display_clock_speed; |
else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
else if (IS_GEN5(dev)) |
dev_priv->display.get_display_clock_speed = |
ilk_get_display_clock_speed; |
else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
dev_priv->display.get_display_clock_speed = |
i945_get_display_clock_speed; |
else if (IS_GM45(dev)) |
dev_priv->display.get_display_clock_speed = |
gm45_get_display_clock_speed; |
else if (IS_CRESTLINE(dev)) |
dev_priv->display.get_display_clock_speed = |
i965gm_get_display_clock_speed; |
else if (IS_PINEVIEW(dev)) |
dev_priv->display.get_display_clock_speed = |
pnv_get_display_clock_speed; |
else if (IS_G33(dev) || IS_G4X(dev)) |
dev_priv->display.get_display_clock_speed = |
g33_get_display_clock_speed; |
else if (IS_I915G(dev)) |
dev_priv->display.get_display_clock_speed = |
i915_get_display_clock_speed; |
12540,10 → 14583,12 |
i865_get_display_clock_speed; |
else if (IS_I85X(dev)) |
dev_priv->display.get_display_clock_speed = |
i855_get_display_clock_speed; |
else /* 852, 830 */ |
i85x_get_display_clock_speed; |
else { /* 830 */ |
WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
dev_priv->display.get_display_clock_speed = |
i830_get_display_clock_speed; |
} |
|
if (IS_GEN5(dev)) { |
dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
12552,22 → 14597,30 |
} else if (IS_IVYBRIDGE(dev)) { |
/* FIXME: detect B0+ stepping and use auto training */ |
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
dev_priv->display.modeset_global_resources = |
ivb_modeset_global_resources; |
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
if (IS_BROADWELL(dev)) { |
dev_priv->display.modeset_commit_cdclk = |
broadwell_modeset_commit_cdclk; |
dev_priv->display.modeset_calc_cdclk = |
broadwell_modeset_calc_cdclk; |
} |
} else if (IS_VALLEYVIEW(dev)) { |
dev_priv->display.modeset_global_resources = |
valleyview_modeset_global_resources; |
dev_priv->display.modeset_commit_cdclk = |
valleyview_modeset_commit_cdclk; |
dev_priv->display.modeset_calc_cdclk = |
valleyview_modeset_calc_cdclk; |
} else if (IS_BROXTON(dev)) { |
dev_priv->display.modeset_commit_cdclk = |
broxton_modeset_commit_cdclk; |
dev_priv->display.modeset_calc_cdclk = |
broxton_modeset_calc_cdclk; |
} |
|
/* Default just returns -ENODEV to indicate unsupported */ |
// dev_priv->display.queue_flip = intel_default_queue_flip; |
|
|
|
|
intel_panel_init_backlight_funcs(dev); |
|
mutex_init(&dev_priv->pps_mutex); |
} |
12658,9 → 14711,6 |
}; |
|
static struct intel_quirk intel_quirks[] = { |
/* HP Mini needs pipe A force quirk (LP: #322104) */ |
{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
|
/* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
{ 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
|
12706,11 → 14756,20 |
/* Apple Macbook 2,1 (Core 2 T7400) */ |
{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, |
|
/* Apple Macbook 4,1 */ |
{ 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, |
|
/* Toshiba CB35 Chromebook (Celeron 2955U) */ |
{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
|
/* HP Chromebook 14 (Celeron 2955U) */ |
{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, |
|
/* Dell Chromebook 11 */ |
{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, |
|
/* Dell Chromebook 11 (2015 version) */ |
{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, |
}; |
|
static void intel_init_quirks(struct drm_device *dev) |
12741,6 → 14800,7 |
u8 sr1; |
u32 vga_reg = i915_vgacntrl_reg(dev); |
|
/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
// vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
outb(SR01, VGA_SR_INDEX); |
sr1 = inb(VGA_SR_DATA); |
12748,23 → 14808,15 |
// vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
udelay(300); |
|
/* |
* Fujitsu-Siemens Lifebook S6010 (830) has problems resuming |
* from S3 without preserving (some of?) the other bits. |
*/ |
I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); |
I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
POSTING_READ(vga_reg); |
} |
|
void intel_modeset_init_hw(struct drm_device *dev) |
{ |
intel_update_cdclk(dev); |
intel_prepare_ddi(dev); |
|
if (IS_VALLEYVIEW(dev)) |
vlv_update_cdclk(dev); |
|
intel_init_clock_gating(dev); |
|
intel_enable_gt_powersave(dev); |
} |
|
12774,7 → 14826,7 |
int sprite, ret; |
enum pipe pipe; |
struct intel_crtc *crtc; |
|
ENTER(); |
drm_mode_config_init(dev); |
|
dev->mode_config.min_width = 0; |
12783,6 → 14835,8 |
dev->mode_config.preferred_depth = 24; |
dev->mode_config.prefer_shadow = 1; |
|
dev->mode_config.allow_fb_modifiers = true; |
|
dev->mode_config.funcs = &intel_mode_funcs; |
|
intel_init_quirks(dev); |
12792,6 → 14846,24 |
if (INTEL_INFO(dev)->num_pipes == 0) |
return; |
|
/* |
* There may be no VBT; and if the BIOS enabled SSC we can |
* just keep using it to avoid unnecessary flicker. Whereas if the |
* BIOS isn't using it, don't assume it will work even if the VBT |
* indicates as much. |
*/ |
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
DREF_SSC1_ENABLE); |
|
if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { |
DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", |
bios_lvds_use_ssc ? "en" : "dis", |
dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); |
dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
} |
} |
|
intel_init_display(dev); |
|
if (IS_GEN2(dev)) { |
12821,7 → 14893,7 |
|
for_each_pipe(dev_priv, pipe) { |
intel_crtc_init(dev, pipe); |
for_each_sprite(pipe, sprite) { |
for_each_sprite(dev_priv, pipe, sprite) { |
ret = intel_plane_init(dev, pipe, sprite); |
if (ret) |
DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
12829,24 → 14901,25 |
} |
} |
|
intel_init_dpio(dev); |
intel_update_czclk(dev_priv); |
intel_update_cdclk(dev); |
|
intel_shared_dpll_init(dev); |
|
/* save the BIOS value before clobbering it */ |
dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev)); |
/* Just disable it once at startup */ |
i915_disable_vga(dev); |
intel_setup_outputs(dev); |
|
/* Just in case the BIOS is doing something questionable. */ |
intel_disable_fbc(dev); |
intel_fbc_disable(dev_priv); |
|
drm_modeset_lock_all(dev); |
intel_modeset_setup_hw_state(dev, false); |
intel_modeset_setup_hw_state(dev); |
drm_modeset_unlock_all(dev); |
|
for_each_intel_crtc(dev, crtc) { |
struct intel_initial_plane_config plane_config = {}; |
|
if (!crtc->active) |
continue; |
|
12857,17 → 14930,28 |
* can even allow for smooth boot transitions if the BIOS |
* fb is large enough for the active pipe configuration. |
*/ |
if (dev_priv->display.get_plane_config) { |
dev_priv->display.get_plane_config(crtc, |
&crtc->plane_config); |
dev_priv->display.get_initial_plane_config(crtc, |
&plane_config); |
|
/* |
* If the fb is shared between multiple heads, we'll |
* just get the first one. |
*/ |
crtc->plane_config.size = 16*1024*1024; |
intel_find_plane_obj(crtc, &crtc->plane_config); |
intel_find_initial_plane_obj(crtc, &plane_config); |
if(!main_fb_obj) |
{ |
struct drm_framebuffer *fb; |
|
fb = crtc->base.primary->fb; |
main_fb_obj = intel_fb_obj(fb); |
main_fb_obj->map_and_fenceable=true; |
DRM_DEBUG_KMS("main_fb_obj %p gtt_offset 0x%08lx\n", main_fb_obj, i915_gem_obj_ggtt_offset(main_fb_obj)); |
} |
|
} |
|
|
LEAVE(); |
} |
|
static void intel_enable_pipe_a(struct drm_device *dev) |
12880,9 → 14964,7 |
/* We can't just switch on the pipe A, we need to set things up with a |
* proper mode and output configuration. As a gross hack, enable pipe A |
* by enabling the load detect pipe once. */ |
list_for_each_entry(connector, |
&dev->mode_config.connector_list, |
base.head) { |
for_each_intel_connector(dev, connector) { |
if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
crt = &connector->base; |
break; |
12893,7 → 14975,7 |
return; |
|
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
intel_release_load_detect_pipe(crt, &load_detect_temp); |
intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
} |
|
static bool |
12901,13 → 14983,12 |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 reg, val; |
u32 val; |
|
if (INTEL_INFO(dev)->num_pipes == 1) |
return true; |
|
reg = DSPCNTR(!crtc->plane); |
val = I915_READ(reg); |
val = I915_READ(DSPCNTR(!crtc->plane)); |
|
if ((val & DISPLAY_PLANE_ENABLE) && |
(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
12916,6 → 14997,17 |
return true; |
} |
|
static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct intel_encoder *encoder; |
|
for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
return true; |
|
return false; |
} |
|
static void intel_sanitize_crtc(struct intel_crtc *crtc) |
{ |
struct drm_device *dev = crtc->base.dev; |
12923,21 → 15015,29 |
u32 reg; |
|
/* Clear any frame start delays used for debugging left by the BIOS */ |
reg = PIPECONF(crtc->config.cpu_transcoder); |
reg = PIPECONF(crtc->config->cpu_transcoder); |
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
|
/* restore vblank interrupts to correct state */ |
drm_crtc_vblank_reset(&crtc->base); |
if (crtc->active) { |
update_scanline_offset(crtc); |
drm_vblank_on(dev, crtc->pipe); |
} else |
drm_vblank_off(dev, crtc->pipe); |
struct intel_plane *plane; |
|
drm_crtc_vblank_on(&crtc->base); |
|
/* Disable everything but the primary plane */ |
for_each_intel_plane_on_crtc(dev, crtc, plane) { |
if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) |
continue; |
|
plane->disable_plane(&plane->base, &crtc->base); |
} |
} |
|
/* We need to sanitize the plane -> pipe mapping first because this will |
* disable the crtc (and hence change the state) if it is wrong. Note |
* that gen4+ has a fixed plane -> pipe mapping. */ |
if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
struct intel_connector *connector; |
bool plane; |
|
DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12947,33 → 15047,12 |
* Temporarily change the plane mapping and disable everything |
* ... */ |
plane = crtc->plane; |
to_intel_plane_state(crtc->base.primary->state)->visible = true; |
crtc->plane = !plane; |
crtc->primary_enabled = true; |
dev_priv->display.crtc_disable(&crtc->base); |
intel_crtc_disable_noatomic(&crtc->base); |
crtc->plane = plane; |
|
/* ... and break all links. */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
if (connector->encoder->base.crtc != &crtc->base) |
continue; |
|
connector->base.dpms = DRM_MODE_DPMS_OFF; |
connector->base.encoder = NULL; |
} |
/* multiple connectors may have the same encoder: |
* handle them and break crtc link separately */ |
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) |
if (connector->encoder->base.crtc == &crtc->base) { |
connector->encoder->base.crtc = NULL; |
connector->encoder->connectors_active = false; |
} |
|
WARN_ON(crtc->active); |
crtc->base.enabled = false; |
} |
|
if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
crtc->pipe == PIPE_A && !crtc->active) { |
/* BIOS forgot to enable pipe A, this mostly happens after |
12985,19 → 15064,23 |
|
/* Adjust the state of the output pipe according to whether we |
* have active connectors/encoders. */ |
intel_crtc_update_dpms(&crtc->base); |
if (!intel_crtc_has_encoders(crtc)) |
intel_crtc_disable_noatomic(&crtc->base); |
|
if (crtc->active != crtc->base.enabled) { |
if (crtc->active != crtc->base.state->active) { |
struct intel_encoder *encoder; |
|
/* This can happen either due to bugs in the get_hw_state |
* functions or because the pipe is force-enabled due to the |
* functions or because of calls to intel_crtc_disable_noatomic, |
* or because the pipe is force-enabled due to the |
* pipe A quirk. */ |
DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
crtc->base.base.id, |
crtc->base.enabled ? "enabled" : "disabled", |
crtc->base.state->enable ? "enabled" : "disabled", |
crtc->active ? "enabled" : "disabled"); |
|
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
crtc->base.state->active = crtc->active; |
crtc->base.enabled = crtc->active; |
|
/* Because we only establish the connector -> encoder -> |
13007,11 → 15090,9 |
* actually up, hence no need to break them. */ |
WARN_ON(crtc->active); |
|
for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
WARN_ON(encoder->connectors_active); |
for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
encoder->base.crtc = NULL; |
} |
} |
|
if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
/* |
13036,6 → 15117,7 |
{ |
struct intel_connector *connector; |
struct drm_device *dev = encoder->base.dev; |
bool active = false; |
|
/* We need to check both for a crtc link (meaning that the |
* encoder is active and trying to read from a pipe) and the |
13043,7 → 15125,15 |
bool has_active_crtc = encoder->base.crtc && |
to_intel_crtc(encoder->base.crtc)->active; |
|
if (encoder->connectors_active && !has_active_crtc) { |
for_each_intel_connector(dev, connector) { |
if (connector->base.encoder != &encoder->base) |
continue; |
|
active = true; |
break; |
} |
|
if (active && !has_active_crtc) { |
DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
encoder->base.base.id, |
encoder->base.name); |
13060,15 → 15150,12 |
encoder->post_disable(encoder); |
} |
encoder->base.crtc = NULL; |
encoder->connectors_active = false; |
|
/* Inconsistent output/port/pipe state happens presumably due to |
* a bug in one of the get_hw_state functions. Or someplace else |
* in our code, like the register restore mess on resume. Clamp |
* things to off as a safer default. */ |
list_for_each_entry(connector, |
&dev->mode_config.connector_list, |
base.head) { |
for_each_intel_connector(dev, connector) { |
if (connector->encoder != encoder) |
continue; |
connector->base.dpms = DRM_MODE_DPMS_OFF; |
13107,14 → 15194,25 |
i915_redisable_vga_power_on(dev); |
} |
|
static bool primary_get_hw_state(struct intel_crtc *crtc) |
static bool primary_get_hw_state(struct intel_plane *plane) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
|
if (!crtc->active) |
return false; |
return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
} |
|
return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; |
/* FIXME read out full plane state for all planes */ |
static void readout_plane_state(struct intel_crtc *crtc) |
{ |
struct drm_plane *primary = crtc->base.primary; |
struct intel_plane_state *plane_state = |
to_intel_plane_state(primary->state); |
|
plane_state->visible = |
primary_get_hw_state(to_intel_plane(primary)); |
|
if (plane_state->visible) |
crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
} |
|
static void intel_modeset_readout_hw_state(struct drm_device *dev) |
13127,16 → 15225,18 |
int i; |
|
for_each_intel_crtc(dev, crtc) { |
memset(&crtc->config, 0, sizeof(crtc->config)); |
__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
memset(crtc->config, 0, sizeof(*crtc->config)); |
crtc->config->base.crtc = &crtc->base; |
|
crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
|
crtc->active = dev_priv->display.get_pipe_config(crtc, |
&crtc->config); |
crtc->config); |
|
crtc->base.state->active = crtc->active; |
crtc->base.enabled = crtc->active; |
crtc->primary_enabled = primary_get_hw_state(crtc); |
|
readout_plane_state(crtc); |
|
DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
crtc->base.base.id, |
crtc->active ? "enabled" : "disabled"); |
13169,12 → 15269,11 |
if (encoder->get_hw_state(encoder, &pipe)) { |
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
encoder->base.crtc = &crtc->base; |
encoder->get_config(encoder, &crtc->config); |
encoder->get_config(encoder, crtc->config); |
} else { |
encoder->base.crtc = NULL; |
} |
|
encoder->connectors_active = false; |
DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
encoder->base.base.id, |
encoder->base.name, |
13182,11 → 15281,9 |
pipe_name(pipe)); |
} |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, |
base.head) { |
for_each_intel_connector(dev, connector) { |
if (connector->get_hw_state(connector)) { |
connector->base.dpms = DRM_MODE_DPMS_ON; |
connector->encoder->connectors_active = true; |
connector->base.encoder = &connector->encoder->base; |
} else { |
connector->base.dpms = DRM_MODE_DPMS_OFF; |
13197,12 → 15294,46 |
connector->base.name, |
connector->base.encoder ? "enabled" : "disabled"); |
} |
|
for_each_intel_crtc(dev, crtc) { |
crtc->base.hwmode = crtc->config->base.adjusted_mode; |
|
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
if (crtc->base.state->active) { |
intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); |
intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); |
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
|
/* |
* The initial mode needs to be set in order to keep |
* the atomic core happy. It wants a valid mode if the |
* crtc's enabled, so we do the above call. |
* |
* At this point some state updated by the connectors |
* in their ->detect() callback has not run yet, so |
* no recalculation can be done yet. |
* |
* Even if we could do a recalculation and modeset |
* right now it would cause a double modeset if |
* fbdev or userspace chooses a different initial mode. |
* |
* If that happens, someone indicated they wanted a |
* mode change, which means it's safe to do a full |
* recalculation. |
*/ |
crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; |
|
drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
update_scanline_offset(crtc); |
} |
} |
} |
|
/* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
* and i915 state tracking structures. */ |
void intel_modeset_setup_hw_state(struct drm_device *dev, |
bool force_restore) |
/* Scan out the current hw modeset state, |
* and sanitizes it to the current state |
*/ |
static void |
intel_modeset_setup_hw_state(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
enum pipe pipe; |
13212,20 → 15343,6 |
|
intel_modeset_readout_hw_state(dev); |
|
/* |
* Now that we have the config, copy it to each CRTC struct |
* Note that this could go away if we move to using crtc_config |
* checking everywhere. |
*/ |
for_each_intel_crtc(dev, crtc) { |
if (crtc->active && i915.fastboot) { |
intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
crtc->base.base.id); |
drm_mode_debug_printmodeline(&crtc->base.mode); |
} |
} |
|
/* HW state is read out, now we need to sanitize this mess. */ |
for_each_intel_encoder(dev, encoder) { |
intel_sanitize_encoder(encoder); |
13234,9 → 15351,12 |
for_each_pipe(dev_priv, pipe) { |
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
intel_sanitize_crtc(crtc); |
intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
intel_dump_pipe_config(crtc, crtc->config, |
"[setup_hw_state]"); |
} |
|
intel_modeset_update_connector_atomic_state(dev); |
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
|
13249,52 → 15369,85 |
pll->on = false; |
} |
|
if (IS_GEN9(dev)) |
if (IS_VALLEYVIEW(dev)) |
vlv_wm_get_hw_state(dev); |
else if (IS_GEN9(dev)) |
skl_wm_get_hw_state(dev); |
else if (HAS_PCH_SPLIT(dev)) |
ilk_wm_get_hw_state(dev); |
|
if (force_restore) { |
i915_redisable_vga(dev); |
for_each_intel_crtc(dev, crtc) { |
unsigned long put_domains; |
|
/* |
* We need to use raw interfaces for restoring state to avoid |
* checking (bogus) intermediate states. |
*/ |
for_each_pipe(dev_priv, pipe) { |
struct drm_crtc *crtc = |
dev_priv->pipe_to_crtc_mapping[pipe]; |
put_domains = modeset_get_crtc_power_domains(&crtc->base); |
if (WARN_ON(put_domains)) |
modeset_put_power_domains(dev_priv, put_domains); |
} |
intel_display_set_init_power(dev_priv, false); |
} |
|
intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
crtc->primary->fb); |
void intel_display_resume(struct drm_device *dev) |
{ |
struct drm_atomic_state *state = drm_atomic_state_alloc(dev); |
struct intel_connector *conn; |
struct intel_plane *plane; |
struct drm_crtc *crtc; |
int ret; |
|
if (!state) |
return; |
|
state->acquire_ctx = dev->mode_config.acquire_ctx; |
|
/* preserve complete old state, including dpll */ |
intel_atomic_get_shared_dpll_state(state); |
|
for_each_crtc(dev, crtc) { |
struct drm_crtc_state *crtc_state = |
drm_atomic_get_crtc_state(state, crtc); |
|
ret = PTR_ERR_OR_ZERO(crtc_state); |
if (ret) |
goto err; |
|
/* force a restore */ |
crtc_state->mode_changed = true; |
} |
} else { |
intel_modeset_update_staged_output_state(dev); |
|
for_each_intel_plane(dev, plane) { |
ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); |
if (ret) |
goto err; |
} |
|
intel_modeset_check_state(dev); |
for_each_intel_connector(dev, conn) { |
ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); |
if (ret) |
goto err; |
} |
|
intel_modeset_setup_hw_state(dev); |
|
i915_redisable_vga(dev); |
ret = drm_atomic_commit(state); |
if (!ret) |
return; |
|
err: |
DRM_ERROR("Restoring old state failed with %i\n", ret); |
drm_atomic_state_free(state); |
} |
|
void intel_modeset_gem_init(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_crtc *c; |
struct drm_i915_gem_object *obj; |
int ret; |
|
mutex_lock(&dev->struct_mutex); |
intel_init_gt_powersave(dev); |
mutex_unlock(&dev->struct_mutex); |
|
/* |
* There may be no VBT; and if the BIOS enabled SSC we can |
* just keep using it to avoid unnecessary flicker. Whereas if the |
* BIOS isn't using it, don't assume it will work even if the VBT |
* indicates as much. |
*/ |
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
DREF_SSC1_ENABLE); |
|
intel_modeset_init_hw(dev); |
|
// intel_setup_overlay(dev); |
13304,22 → 15457,29 |
* pinned & fenced. When we do the allocation it's too early |
* for this. |
*/ |
mutex_lock(&dev->struct_mutex); |
for_each_crtc(dev, c) { |
obj = intel_fb_obj(c->primary->fb); |
if (obj == NULL) |
continue; |
|
if (intel_pin_and_fence_fb_obj(c->primary, |
mutex_lock(&dev->struct_mutex); |
ret = intel_pin_and_fence_fb_obj(c->primary, |
c->primary->fb, |
NULL)) { |
c->primary->state, |
NULL, NULL); |
mutex_unlock(&dev->struct_mutex); |
if (ret) { |
DRM_ERROR("failed to pin boot fb on pipe %d\n", |
to_intel_crtc(c)->pipe); |
drm_framebuffer_unreference(c->primary->fb); |
c->primary->fb = NULL; |
c->primary->crtc = c->primary->state->crtc = NULL; |
update_state_fb(c->primary); |
c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
} |
} |
mutex_unlock(&dev->struct_mutex); |
|
intel_backlight_register(dev); |
} |
|
void intel_connector_unregister(struct intel_connector *intel_connector) |
13353,16 → 15513,10 |
*/ |
drm_kms_helper_poll_fini(dev); |
|
mutex_lock(&dev->struct_mutex); |
|
intel_unregister_dsm_handler(); |
|
intel_disable_fbc(dev); |
intel_fbc_disable(dev_priv); |
|
ironlake_teardown_rc6(dev); |
|
mutex_unlock(&dev->struct_mutex); |
|
/* flush any delayed tasks or pending work */ |
flush_scheduled_work(); |
|