4560,9 → 4560,9 |
/* Enable DPIO clock input */ |
dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
if (pipe) |
/* We should never disable this, set it here for state tracking */ |
if (pipe == PIPE_B) |
dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
|
dpll |= DPLL_VCO_ENABLE; |
crtc->config.dpll_hw_state.dpll = dpll; |
|
5022,6 → 5022,32 |
I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
} |
|
static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = pipe_config->cpu_transcoder; |
intel_clock_t clock; |
u32 mdiv; |
int refclk = 100000; |
|
mutex_lock(&dev_priv->dpio_lock); |
mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
mutex_unlock(&dev_priv->dpio_lock); |
|
clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
clock.m2 = mdiv & DPIO_M2DIV_MASK; |
clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
|
clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
|
pipe_config->adjusted_mode.clock = clock.dot / 10; |
} |
|
static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
{ |
5553,7 → 5579,7 |
uint16_t postoff = 0; |
|
if (intel_crtc->config.limited_color_range) |
postoff = (16 * (1 << 13) / 255) & 0x1fff; |
postoff = (16 * (1 << 12) / 255) & 0x1fff; |
|
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
6069,7 → 6095,7 |
|
/* Make sure we're not on PC8 state before disabling PC8, otherwise |
* we'll hang the machine! */ |
dev_priv->uncore.funcs.force_wake_get(dev_priv); |
gen6_gt_force_wake_get(dev_priv); |
|
if (val & LCPLL_POWER_DOWN_ALLOW) { |
val &= ~LCPLL_POWER_DOWN_ALLOW; |
6100,7 → 6126,7 |
DRM_ERROR("Switching back to LCPLL failed\n"); |
} |
|
dev_priv->uncore.funcs.force_wake_put(dev_priv); |
gen6_gt_force_wake_put(dev_priv); |
} |
|
void hsw_enable_pc8_work(struct work_struct *__work) |
9794,7 → 9820,7 |
dev_priv->display.update_plane = ironlake_update_plane; |
} else if (IS_VALLEYVIEW(dev)) { |
dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
dev_priv->display.get_clock = i9xx_crtc_clock_get; |
dev_priv->display.get_clock = vlv_crtc_clock_get; |
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
dev_priv->display.crtc_enable = valleyview_crtc_enable; |
dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10028,6 → 10054,8 |
|
void intel_modeset_init_hw(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
|
intel_init_power_well(dev); |
|
intel_prepare_ddi(dev); |
10034,11 → 10062,21 |
|
intel_init_clock_gating(dev); |
|
/* Enable the CRI clock source so we can get at the display */ |
if (IS_VALLEYVIEW(dev)) |
I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
DPLL_INTEGRATED_CRI_CLK_VLV); |
|
mutex_lock(&dev->struct_mutex); |
intel_enable_gt_powersave(dev); |
mutex_unlock(&dev->struct_mutex); |
} |
|
void intel_modeset_suspend_hw(struct drm_device *dev) |
{ |
intel_suspend_hw(dev); |
} |
|
void intel_modeset_init(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |