98,6 → 98,19 |
}; |
#define port_name(p) ((p) + 'A') |
|
enum hpd_pin { |
HPD_NONE = 0, |
HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
HPD_CRT, |
HPD_SDVO_B, |
HPD_SDVO_C, |
HPD_PORT_B, |
HPD_PORT_C, |
HPD_PORT_D, |
HPD_NUM_PINS |
}; |
|
#define I915_GEM_GPU_DOMAINS \ |
(I915_GEM_DOMAIN_RENDER | \ |
I915_GEM_DOMAIN_SAMPLER | \ |
105,7 → 118,7 |
I915_GEM_DOMAIN_INSTRUCTION | \ |
I915_GEM_DOMAIN_VERTEX) |
|
#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
|
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
194,9 → 207,9 |
struct _drm_i915_sarea *sarea_priv; |
}; |
#define I915_FENCE_REG_NONE -1 |
#define I915_MAX_NUM_FENCES 16 |
/* 16 fences + sign bit for FENCE_REG_NONE */ |
#define I915_MAX_NUM_FENCE_BITS 5 |
#define I915_MAX_NUM_FENCES 32 |
/* 32 fences + sign bit for FENCE_REG_NONE */ |
#define I915_MAX_NUM_FENCE_BITS 6 |
|
struct drm_i915_fence_reg { |
struct list_head lru_list; |
255,7 → 268,7 |
int page_count; |
u32 gtt_offset; |
u32 *pages[0]; |
} *ringbuffer, *batchbuffer; |
} *ringbuffer, *batchbuffer, *ctx; |
struct drm_i915_error_request { |
long jiffies; |
u32 seqno; |
283,6 → 296,9 |
struct intel_display_error_state *display; |
}; |
|
struct intel_crtc_config; |
struct intel_crtc; |
|
struct drm_i915_display_funcs { |
bool (*fbc_enabled)(struct drm_device *dev); |
void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
295,9 → 311,11 |
void (*update_linetime_wm)(struct drm_device *dev, int pipe, |
struct drm_display_mode *mode); |
void (*modeset_global_resources)(struct drm_device *dev); |
/* Returns the active state of the crtc, and if the crtc is active, |
* fills out the pipe-config with the hw state. */ |
bool (*get_pipe_config)(struct intel_crtc *, |
struct intel_crtc_config *); |
int (*crtc_mode_set)(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode, |
int x, int y, |
struct drm_framebuffer *old_fb); |
void (*crtc_enable)(struct drm_crtc *crtc); |
353,6 → 371,7 |
|
struct intel_device_info { |
u32 display_mmio_offset; |
u8 num_pipes:3; |
u8 gen; |
u8 is_mobile:1; |
u8 is_i85x:1; |
442,6 → 461,7 |
struct sg_table *st, |
unsigned int pg_start, |
enum i915_cache_level cache_level); |
int (*enable)(struct drm_device *dev); |
void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
}; |
|
472,6 → 492,7 |
PCH_IBX, /* Ibexpeak PCH */ |
PCH_CPT, /* Cougarpoint PCH */ |
PCH_LPT, /* Lynxpoint PCH */ |
PCH_NOP, |
}; |
|
enum intel_sbi_destination { |
659,6 → 680,7 |
u8 cur_delay; |
u8 min_delay; |
u8 max_delay; |
u8 hw_max; |
|
struct delayed_work delayed_resume_work; |
|
915,16 → 937,23 |
struct mutex dpio_lock; |
|
/** Cached value of IMR to avoid reads in updating the bitfield */ |
u32 pipestat[2]; |
u32 irq_mask; |
u32 gt_irq_mask; |
|
u32 hotplug_supported_mask; |
struct work_struct hotplug_work; |
bool enable_hotplug_processing; |
struct { |
unsigned long hpd_last_jiffies; |
int hpd_cnt; |
enum { |
HPD_ENABLED = 0, |
HPD_DISABLED = 1, |
HPD_MARK_DISABLED = 2 |
} hpd_mark; |
} hpd_stats[HPD_NUM_PINS]; |
|
int num_pipe; |
int num_pch_pll; |
int num_plane; |
|
unsigned long cfb_size; |
unsigned int cfb_fb; |
938,9 → 967,14 |
struct intel_overlay *overlay; |
unsigned int sprite_scaling_enabled; |
|
/* backlight */ |
struct { |
int level; |
bool enabled; |
struct backlight_device *device; |
} backlight; |
|
/* LVDS info */ |
int backlight_level; /* restore backlight to this value */ |
bool backlight_enabled; |
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
|
951,6 → 985,7 |
unsigned int int_crt_support:1; |
unsigned int lvds_use_ssc:1; |
unsigned int display_clock_mode:1; |
unsigned int fdi_rx_polarity_inverted:1; |
int lvds_ssc_freq; |
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
struct { |
1042,8 → 1077,6 |
*/ |
struct work_struct console_resume_work; |
|
// struct backlight_device *backlight; |
|
struct drm_property *broadcast_rgb_property; |
struct drm_property *force_audio_property; |
|
1350,6 → 1383,7 |
#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
|
#define HAS_DDI(dev) (IS_HASWELL(dev)) |
#define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
|
#define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
1362,6 → 1396,7 |
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
|
#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1534,18 → 1569,13 |
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
{ |
struct scatterlist *sg = obj->pages->sgl; |
int nents = obj->pages->nents; |
while (nents > SG_MAX_SINGLE_ALLOC) { |
if (n < SG_MAX_SINGLE_ALLOC - 1) |
break; |
struct sg_page_iter sg_iter; |
|
sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1); |
n -= SG_MAX_SINGLE_ALLOC - 1; |
nents -= SG_MAX_SINGLE_ALLOC - 1; |
for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
return sg_page_iter_page(&sg_iter); |
|
return NULL; |
} |
return sg_page(sg+n); |
} |
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
{ |
BUG_ON(obj->pages == NULL); |
1629,7 → 1659,6 |
int __must_check i915_gem_init_hw(struct drm_device *dev); |
void i915_gem_l3_remap(struct drm_device *dev); |
void i915_gem_init_swizzling(struct drm_device *dev); |
void i915_gem_init_ppgtt(struct drm_device *dev); |
void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
int __must_check i915_gpu_idle(struct drm_device *dev); |
int __must_check i915_gem_idle(struct drm_device *dev); |
1670,6 → 1699,8 |
struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
struct drm_gem_object *gem_obj, int flags); |
|
void i915_gem_restore_fences(struct drm_device *dev); |
|
/* i915_gem_context.c */ |
void i915_gem_context_init(struct drm_device *dev); |
void i915_gem_context_fini(struct drm_device *dev); |
1721,6 → 1752,11 |
void i915_gem_cleanup_stolen(struct drm_device *dev); |
struct drm_i915_gem_object * |
i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
struct drm_i915_gem_object * |
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
u32 stolen_offset, |
u32 gtt_offset, |
u32 size); |
void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
|
/* i915_gem_tiling.c */ |
1851,6 → 1887,8 |
|
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val); |
int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
|
#define __i915_read(x, y) \ |
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
1904,6 → 1942,27 |
return VGACNTRL; |
} |
|
static inline void __user *to_user_ptr(u64 address) |
{ |
return (void __user *)(uintptr_t)address; |
} |
|
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
{ |
unsigned long j = msecs_to_jiffies(m); |
|
return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
} |
|
static inline unsigned long |
timespec_to_jiffies_timeout(const struct timespec *value) |
{ |
unsigned long j = timespec_to_jiffies(value); |
|
return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
} |
|
|
typedef struct |
{ |
int width; |