WebSVN – Kolibri OS – Path Comparison – / – /drivers/video/drm/i915/i915_drv.h Rev 3242 and /drivers/video/drm/i915/i915

Regard whitespace Rev 3242 → Rev 3243

 /drivers/video/drm/i915/i915_drv.h
 ,6 → 33,7
 #include "i915_reg.h"
 #include "intel_bios.h"
 #include "intel_ringbuffer.h"
+#include <linux/scatterlist.h>
 //#include <linux/io-mapping.h>
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 ,6 → 41,7
 //#include <linux/backlight.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 /* General customization:
 ,6 → 71,14
 };
 #define pipe_name(p) ((p) + 'A')
+enum transcoder {
+        TRANSCODER_A = 0,
+        TRANSCODER_B,
+        TRANSCODER_C,
+        TRANSCODER_EDP = 0xF,
+};
+#define transcoder_name(t) ((t) + 'A')
 enum plane {
         PLANE_A = 0,
         PLANE_B,
 ,6 → 114,12
 };
 #define I915_NUM_PLLS 2
+struct intel_ddi_plls {
+        int spll_refcount;
+        int wrpll1_refcount;
+        int wrpll2_refcount;
+};
 /* Interface history:
  *
  * 1.1: Original.
 ,14 → 143,8
 #define I915_GEM_PHYS_OVERLAY_REGS 3
 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
-struct mem_block {
-        struct mem_block *next;
-        struct mem_block *prev;
-        int start;
-        int size;
-        struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
-};
 struct opregion_header;
 struct opregion_acpi;
 struct opregion_swsci;
 ,19 → 191,24
 struct intel_display_error_state;
 struct drm_i915_error_state {
+        struct kref ref;
         u32 eir;
         u32 pgtbl_er;
         u32 ier;
         u32 ccid;
+        u32 derrmr;
+        u32 forcewake;
         bool waiting[I915_NUM_RINGS];
         u32 pipestat[I915_MAX_PIPES];
         u32 tail[I915_NUM_RINGS];
         u32 head[I915_NUM_RINGS];
+        u32 ctl[I915_NUM_RINGS];
         u32 ipeir[I915_NUM_RINGS];
         u32 ipehr[I915_NUM_RINGS];
         u32 instdone[I915_NUM_RINGS];
         u32 acthd[I915_NUM_RINGS];
         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
+        u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
         /* our own tracking of ring head and tail */
         u32 cpu_ring_head[I915_NUM_RINGS];
 ,6 → 269,7
                                  uint32_t sprite_width, int pixel_size);
         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
                                  struct drm_display_mode *mode);
+        void (*modeset_global_resources)(struct drm_device *dev);
         int (*crtc_mode_set)(struct drm_crtc *crtc,
                              struct drm_display_mode *mode,
                              struct drm_display_mode *adjusted_mode,
 ,7 → 282,6
                           struct drm_crtc *crtc);
         void (*fdi_link_train)(struct drm_crtc *crtc);
         void (*init_clock_gating)(struct drm_device *dev);
-        void (*init_pch_clock_gating)(struct drm_device *dev);
         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
                           struct drm_framebuffer *fb,
                           struct drm_i915_gem_object *obj);
 ,8 → 356,9
 #define I915_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES 1024
 struct i915_hw_ppgtt {
+        struct drm_device *dev;
         unsigned num_pd_entries;
-    dma_addr_t *pt_pages;
+        struct page **pt_pages;
         uint32_t pd_offset;
         dma_addr_t *pt_dma_addr;
         dma_addr_t scratch_page_dma_addr;
 ,6 → 393,11
         PCH_LPT,        /* Lynxpoint PCH */
 };
+enum intel_sbi_destination {
+        SBI_ICLK,
+        SBI_MPHY,
+};
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 ,7 → 407,7
 struct intel_gmbus {
         struct i2c_adapter adapter;
-        bool force_bit;
+        u32 force_bit;
         u32 reg0;
         u32 gpio_reg;
         struct i2c_algo_bit_data bit_algo;
 ,147 → 414,11
         struct drm_i915_private *dev_priv;
 };
-typedef struct drm_i915_private {
-        struct drm_device *dev;
-        const struct intel_device_info *info;
-        int relative_constants_mode;
-        void __iomem *regs;
-        struct drm_i915_gt_funcs gt;
-        /** gt_fifo_count and the subsequent register write are synchronized
-         * with dev->struct_mutex. */
-        unsigned gt_fifo_count;
-        /** forcewake_count is protected by gt_lock */
-        unsigned forcewake_count;
-        /** gt_lock is also taken in irq contexts. */
-    spinlock_t gt_lock;
-        struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
-        /** gmbus_mutex protects against concurrent usage of the single hw gmbus
-         * controller on different i2c buses. */
-        struct mutex gmbus_mutex;
-        /**
-         * Base address of the gmbus and gpio block.
-         */
-        uint32_t gpio_mmio_base;
-        struct pci_dev *bridge_dev;
-    struct intel_ring_buffer ring[I915_NUM_RINGS];
-        uint32_t next_seqno;
-    drm_dma_handle_t *status_page_dmah;
-        uint32_t counter;
-    struct drm_i915_gem_object *pwrctx;
-    struct drm_i915_gem_object *renderctx;
-//   struct resource mch_res;
-        atomic_t irq_received;
-        /* protects the irq masks */
-        spinlock_t irq_lock;
-        /* DPIO indirect register protection */
-        spinlock_t dpio_lock;
-        /** Cached value of IMR to avoid reads in updating the bitfield */
-        u32 pipestat[2];
-        u32 irq_mask;
-        u32 gt_irq_mask;
-        u32 pch_irq_mask;
-        u32 hotplug_supported_mask;
-        struct work_struct hotplug_work;
-        int num_pipe;
-        int num_pch_pll;
-        /* For hangcheck timer */
-#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
-    struct timer_list hangcheck_timer;
-        int hangcheck_count;
-        uint32_t last_acthd[I915_NUM_RINGS];
-        uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
-        unsigned int stop_rings;
-        unsigned long cfb_size;
-        unsigned int cfb_fb;
-        enum plane cfb_plane;
-        int cfb_y;
-//   struct intel_fbc_work *fbc_work;
-    struct intel_opregion opregion;
-        /* overlay */
-//   struct intel_overlay *overlay;
-        bool sprite_scaling_enabled;
-        /* LVDS info */
-        int backlight_level;  /* restore backlight to this value */
-        bool backlight_enabled;
-        struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
-        struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
-        /* Feature bits from the VBIOS */
-        unsigned int int_tv_support:1;
-        unsigned int lvds_dither:1;
-        unsigned int lvds_vbt:1;
-        unsigned int int_crt_support:1;
-        unsigned int lvds_use_ssc:1;
-        unsigned int display_clock_mode:1;
-        int lvds_ssc_freq;
-        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
-        unsigned int lvds_val; /* used for checking LVDS channel mode */
-        struct {
-                int rate;
-                int lanes;
-                int preemphasis;
-                int vswing;
-                bool initialized;
-                bool support;
-                int bpp;
-        struct edp_power_seq pps;
-        } edp;
-        bool no_aux_handshake;
-//   struct notifier_block lid_notifier;
-        int crt_ddc_pin;
-        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
-        int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
-        int num_fence_regs; /* 8 on pre-965, 16 otherwise */
-        unsigned int fsb_freq, mem_freq, is_ddr3;
-        spinlock_t error_lock;
-        /* Protected by dev->error_lock. */
-        struct drm_i915_error_state *first_error;
-        struct work_struct error_work;
-        struct completion error_completion;
-    struct workqueue_struct *wq;
-        /* Display functions */
-    struct drm_i915_display_funcs display;
-        /* PCH chipset type */
-        enum intel_pch pch_type;
-        unsigned long quirks;
-        /* Register state */
-        bool modeset_on_lid;
+struct i915_suspend_saved_registers {
         u8 saveLBB;
         u32 saveDSPACNTR;
         u32 saveDSPBCNTR;
         u32 saveDSPARB;
-        u32 saveHWS;
         u32 savePIPEACONF;
         u32 savePIPEBCONF;
         u32 savePIPEASRC;
 ,10 → 564,206
         u32 savePIPEB_LINK_N1;
         u32 saveMCHBAR_RENDER_STANDBY;
         u32 savePCH_PORT_HOTPLUG;
+};
+struct intel_gen6_power_mgmt {
+        struct work_struct work;
+        u32 pm_iir;
+        /* lock - irqsave spinlock that protectects the work_struct and
+         * pm_iir. */
+        spinlock_t lock;
+        /* The below variables an all the rps hw state are protected by
+         * dev->struct mutext. */
+        u8 cur_delay;
+        u8 min_delay;
+        u8 max_delay;
+        struct delayed_work delayed_resume_work;
+        /*
+         * Protects RPS/RC6 register access and PCU communication.
+         * Must be taken after struct_mutex if nested.
+         */
+        struct mutex hw_lock;
+};
+struct intel_ilk_power_mgmt {
+        u8 cur_delay;
+        u8 min_delay;
+        u8 max_delay;
+        u8 fmax;
+        u8 fstart;
+        u64 last_count1;
+        unsigned long last_time1;
+        unsigned long chipset_power;
+        u64 last_count2;
+        struct timespec last_time2;
+        unsigned long gfx_power;
+        u8 corr;
+        int c_m;
+        int r_t;
+        struct drm_i915_gem_object *pwrctx;
+        struct drm_i915_gem_object *renderctx;
+};
+struct i915_dri1_state {
+        unsigned allow_batchbuffer : 1;
+        u32 __iomem *gfx_hws_cpu_addr;
+        unsigned int cpp;
+        int back_offset;
+        int front_offset;
+        int current_page;
+        int page_flipping;
+        uint32_t counter;
+};
+struct intel_l3_parity {
+        u32 *remap_info;
+        struct work_struct error_work;
+};
+typedef struct drm_i915_private {
+        struct drm_device *dev;
+        const struct intel_device_info *info;
+        int relative_constants_mode;
+        void __iomem *regs;
+        struct drm_i915_gt_funcs gt;
+        /** gt_fifo_count and the subsequent register write are synchronized
+         * with dev->struct_mutex. */
+        unsigned gt_fifo_count;
+        /** forcewake_count is protected by gt_lock */
+        unsigned forcewake_count;
+        /** gt_lock is also taken in irq contexts. */
+        struct spinlock gt_lock;
+        struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
+        /** gmbus_mutex protects against concurrent usage of the single hw gmbus
+         * controller on different i2c buses. */
+        struct mutex gmbus_mutex;
+        /**
+         * Base address of the gmbus and gpio block.
+         */
+        uint32_t gpio_mmio_base;
+        struct pci_dev *bridge_dev;
+        struct intel_ring_buffer ring[I915_NUM_RINGS];
+        uint32_t next_seqno;
+        drm_dma_handle_t *status_page_dmah;
+        struct resource mch_res;
+        atomic_t irq_received;
+        /* protects the irq masks */
+        spinlock_t irq_lock;
+        /* DPIO indirect register protection */
+        spinlock_t dpio_lock;
+        /** Cached value of IMR to avoid reads in updating the bitfield */
+        u32 pipestat[2];
+        u32 irq_mask;
+        u32 gt_irq_mask;
+        u32 pch_irq_mask;
+        u32 hotplug_supported_mask;
+        struct work_struct hotplug_work;
+        int num_pipe;
+        int num_pch_pll;
+        /* For hangcheck timer */
+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
+        struct timer_list hangcheck_timer;
+        int hangcheck_count;
+        uint32_t last_acthd[I915_NUM_RINGS];
+        uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
+        unsigned int stop_rings;
+        unsigned long cfb_size;
+        unsigned int cfb_fb;
+        enum plane cfb_plane;
+        int cfb_y;
+        struct intel_fbc_work *fbc_work;
+        struct intel_opregion opregion;
+        /* overlay */
+        struct intel_overlay *overlay;
+        bool sprite_scaling_enabled;
+        /* LVDS info */
+        int backlight_level;  /* restore backlight to this value */
+        bool backlight_enabled;
+        struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
+        struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
+        /* Feature bits from the VBIOS */
+        unsigned int int_tv_support:1;
+        unsigned int lvds_dither:1;
+        unsigned int lvds_vbt:1;
+        unsigned int int_crt_support:1;
+        unsigned int lvds_use_ssc:1;
+        unsigned int display_clock_mode:1;
+        int lvds_ssc_freq;
+        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+        unsigned int lvds_val; /* used for checking LVDS channel mode */
         struct {
+                int rate;
+                int lanes;
+                int preemphasis;
+                int vswing;
+                bool initialized;
+                bool support;
+                int bpp;
+                struct edp_power_seq pps;
+        } edp;
+        bool no_aux_handshake;
+        int crt_ddc_pin;
+        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
+        int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
+        int num_fence_regs; /* 8 on pre-965, 16 otherwise */
+        unsigned int fsb_freq, mem_freq, is_ddr3;
+        spinlock_t error_lock;
+        /* Protected by dev->error_lock. */
+        struct drm_i915_error_state *first_error;
+        struct work_struct error_work;
+        struct completion error_completion;
+        struct workqueue_struct *wq;
+        /* Display functions */
+        struct drm_i915_display_funcs display;
+        /* PCH chipset type */
+        enum intel_pch pch_type;
+        unsigned short pch_id;
+        unsigned long quirks;
+        /* Register state */
+        bool modeset_on_lid;
+        struct {
                 /** Bridge to intel-gtt-ko */
-                const struct intel_gtt *gtt;
+                struct intel_gtt *gtt;
                 /** Memory allocator for GTT stolen memory */
         struct drm_mm stolen;
                 /** Memory allocator for GTT */
 ,9 → 790,8
                 /** PPGTT used for aliasing the PPGTT with the GTT */
                 struct i915_hw_ppgtt *aliasing_ppgtt;
-                u32 *l3_remap_info;
 //       struct shrinker inactive_shrinker;
+                bool shrinker_no_lock_stealing;
                 /**
                  * List of objects currently involved in rendering.
 ,19 → 868,6
                 u32 object_count;
         } mm;
-        /* Old dri1 support infrastructure, beware the dragons ya fools entering
-         * here! */
-        struct {
-                unsigned allow_batchbuffer : 1;
-                u32 __iomem *gfx_hws_cpu_addr;
-                unsigned int cpp;
-                int back_offset;
-                int front_offset;
-                int current_page;
-                int page_flipping;
-        } dri1;
         /* Kernel Modesetting */
     struct sdvo_device_mapping sdvo_mappings[2];
 ,6 → 881,7
         wait_queue_head_t pending_flip_queue;
         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
+        struct intel_ddi_plls ddi_plls;
         /* Reclocking support */
         bool render_reclock_avail;
 ,47 → 891,18
         u16 orig_clock;
         int child_dev_num;
     struct child_device_config *child_dev;
-    struct drm_connector *int_lvds_connector;
-    struct drm_connector *int_edp_connector;
         bool mchbar_need_disable;
+        struct intel_l3_parity l3_parity;
         /* gen6+ rps state */
-        struct {
-                struct work_struct work;
-        u32 pm_iir;
-                /* lock - irqsave spinlock that protectects the work_struct and
-                 * pm_iir. */
-                spinlock_t lock;
+        struct intel_gen6_power_mgmt rps;
-                /* The below variables an all the rps hw state are protected by
-                 * dev->struct mutext. */
-                u8 cur_delay;
-                u8 min_delay;
-                u8 max_delay;
-        } rps;
         /* ilk-only ips/rps state. Everything in here is protected by the global
          * mchdev_lock in intel_pm.c */
-        struct {
-        u8 cur_delay;
-        u8 min_delay;
-        u8 max_delay;
-        u8 fmax;
-        u8 fstart;
+        struct intel_ilk_power_mgmt ips;
-        u64 last_count1;
-        unsigned long last_time1;
-        unsigned long chipset_power;
-        u64 last_count2;
-    struct timespec last_time2;
-        unsigned long gfx_power;
-                u8 corr;
-        int c_m;
-        int r_t;
-        } ips;
         enum no_fbc_reason no_fbc_reason;
         struct drm_mm_node *compressed_fb;
 ,6 → 913,12
         /* list of fbdev register on this device */
     struct intel_fbdev *fbdev;
+        /*
+         * The console may be contended at resume, but we don't
+         * want it to block on it.
+         */
+        struct work_struct console_resume_work;
 //   struct backlight_device *backlight;
         struct drm_property *broadcast_rgb_property;
 ,6 → 926,14
         bool hw_contexts_disabled;
         uint32_t hw_context_size;
+        bool fdi_rx_polarity_reversed;
+        struct i915_suspend_saved_registers regfile;
+        /* Old dri1 support infrastructure, beware the dragons ya fools entering
+         * here! */
+        struct i915_dri1_state dri1;
 } drm_i915_private_t;
 /* Iterate over initialised rings */
 ,7 → 977,7
         const struct drm_i915_gem_object_ops *ops;
-    void  *mapped;
+//    void  *mapped;
     /** Current space allocated to this object in the GTT, if any. */
     struct drm_mm_node *gtt_space;
 ,8 → 1065,8
         unsigned int has_global_gtt_mapping:1;
         unsigned int has_dma_mapping:1;
-    dma_addr_t *allocated_pages;
-    struct pagelist pages;
+//    dma_addr_t *allocated_pages;
+        struct sg_table *pages;
         int pages_pin_count;
         /* prime dma-buf support */
 ,6 → 1115,7
      */
     atomic_t pending_flip;
 };
+#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 ,7 → 1152,7
 struct drm_i915_file_private {
         struct {
-        spinlock_t lock;
+                struct spinlock lock;
                 struct list_head request_list;
         } mm;
         struct idr context_idr;
 ,9 → 1179,17
 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
+                                 (dev)->pci_device == 0x0152 || \
+                                 (dev)->pci_device == 0x015a)
+#define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
+                                 (dev)->pci_device == 0x0106 || \
+                                 (dev)->pci_device == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
+#define IS_ULT(dev)             (IS_HASWELL(dev) && \
+                                 ((dev)->pci_device & 0xFF00) == 0x0A00)
 /*
  * The genX designation typically refers to the render engine, so render
 ,6 → 1215,9
 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
+/* Early gen2 have a totally busted CS tlb and require pinned batches. */
+#define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
 ,6 → 1238,13
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
+#define INTEL_PCH_DEVICE_ID_MASK                0xff00
+#define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
+#define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
+#define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
+#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 ,6 → 1330,7
 extern void intel_irq_init(struct drm_device *dev);
 extern void intel_gt_init(struct drm_device *dev);
+extern void intel_gt_reset(struct drm_device *dev);
 void i915_error_state_free(struct kref *error_ref);
 ,15 → 1413,23
 void i915_gem_lastclose(struct drm_device *dev);
 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
-static inline dma_addr_t i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
+static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
 {
-    return obj->pages.page[n];
-};
+        struct scatterlist *sg = obj->pages->sgl;
+        int nents = obj->pages->nents;
+        while (nents > SG_MAX_SINGLE_ALLOC) {
+                if (n < SG_MAX_SINGLE_ALLOC - 1)
+                        break;
+                sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
+                n -= SG_MAX_SINGLE_ALLOC - 1;
+                nents -= SG_MAX_SINGLE_ALLOC - 1;
+        }
+        return sg_page(sg+n);
+}
 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
 {
-    BUG_ON(obj->pages.page == NULL);
+        BUG_ON(obj->pages == NULL);
         obj->pages_pin_count++;
 }
 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
 ,8 → 1442,7
 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
                          struct intel_ring_buffer *to);
 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
-                                    struct intel_ring_buffer *ring,
-                                    u32 seqno);
+                                    struct intel_ring_buffer *ring);
 int i915_gem_dumb_create(struct drm_file *file_priv,
                          struct drm_device *dev,
 ,7 → 1460,7
         return (int32_t)(seq1 - seq2) >= 0;
 }
-u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
+extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
 ,7 → 1570,15
                               unsigned long start,
                               unsigned long mappable_end,
                               unsigned long end);
+int i915_gem_gtt_init(struct drm_device *dev);
+void i915_gem_gtt_fini(struct drm_device *dev);
+static inline void i915_gem_chipset_flush(struct drm_device *dev)
+{
+        if (INTEL_INFO(dev)->gen < 6)
+                intel_gtt_chipset_flush();
+}
 /* i915_gem_evict.c */
 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
                                           unsigned alignment,
 ,11 → 1674,12
 extern void intel_modeset_gem_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
-extern void intel_modeset_setup_hw_state(struct drm_device *dev);
+extern void intel_modeset_setup_hw_state(struct drm_device *dev,
+                                         bool force_restore);
 extern bool intel_fbc_enabled(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
-extern void ironlake_init_pch_refclk(struct drm_device *dev);
+extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
 extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 ,6 → 1708,9
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
+int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
+int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
 #define __i915_read(x, y) \
         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);

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