WebSVN – Kolibri OS – Path Comparison – / – /drivers/video/drm/i915/i915_drv.c Rev 3745 and /drivers/video/drm/i915/i915

Regard whitespace Rev 3745 → Rev 3746

 /drivers/video/drm/i915/i915_drv.c
 ,6 → 57,8
                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
                 "1=on, -1=force vga console preference [default])");
+unsigned int i915_fbpercrtc __always_unused = 0;
+module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 int i915_panel_ignore_lid __read_mostly         =  1;
 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
 ,7 → 126,7
                 "WARNING: Disabling this can cause system wide hangs. "
                 "(default: true)");
-int i915_enable_ppgtt __read_mostly = false;
+int i915_enable_ppgtt __read_mostly = 0;
 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 MODULE_PARM_DESC(i915_enable_ppgtt,
                 "Enable PPGTT (default: true)");
 ,9 → 134,7
 unsigned int i915_preliminary_hw_support __read_mostly = true;
 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 MODULE_PARM_DESC(preliminary_hw_support,
-                "Enable preliminary hardware support. "
-                "Enable Haswell and ValleyView Support. "
-                "(default: false)");
+                "Enable preliminary hardware support. (default: false)");
 int i915_disable_power_well __read_mostly = 0;
 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 ,23 → 152,31
     .subdevice = PCI_ANY_ID,                \
     .driver_data = (unsigned long) info }
+#define INTEL_QUANTA_VGA_DEVICE(info) {         \
+        .class = PCI_BASE_CLASS_DISPLAY << 16,  \
+        .class_mask = 0xff0000,                 \
+        .vendor = 0x8086,                       \
+        .device = 0x16a,                        \
+        .subvendor = 0x152d,                    \
+        .subdevice = 0x8990,                    \
+        .driver_data = (unsigned long) info }
 static const struct intel_device_info intel_i915g_info = {
-        .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
+        .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
         .has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
-        .gen = 3, .is_mobile = 1,
+        .gen = 3, .is_mobile = 1, .num_pipes = 2,
         .cursor_needs_physical = 1,
         .has_overlay = 1, .overlay_needs_physical = 1,
         .supports_tv = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
-        .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
+        .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
         .has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
-        .gen = 3, .is_i945gm = 1, .is_mobile = 1,
+        .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
         .has_hotplug = 1, .cursor_needs_physical = 1,
         .has_overlay = 1, .overlay_needs_physical = 1,
         .supports_tv = 1,
 ,13 → 183,13
 };
 static const struct intel_device_info intel_i965g_info = {
-        .gen = 4, .is_broadwater = 1,
+        .gen = 4, .is_broadwater = 1, .num_pipes = 2,
         .has_hotplug = 1,
         .has_overlay = 1,
 };
 static const struct intel_device_info intel_i965gm_info = {
-        .gen = 4, .is_crestline = 1,
+        .gen = 4, .is_crestline = 1, .num_pipes = 2,
         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
         .has_overlay = 1,
         .supports_tv = 1,
 ,19 → 196,19
 };
 static const struct intel_device_info intel_g33_info = {
-        .gen = 3, .is_g33 = 1,
+        .gen = 3, .is_g33 = 1, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
         .has_overlay = 1,
 };
 static const struct intel_device_info intel_g45_info = {
-        .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
+        .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
         .has_pipe_cxsr = 1, .has_hotplug = 1,
         .has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_gm45_info = {
-        .gen = 4, .is_g4x = 1,
+        .gen = 4, .is_g4x = 1, .num_pipes = 2,
         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
         .has_pipe_cxsr = 1, .has_hotplug = 1,
         .supports_tv = 1,
 ,19 → 216,19
 };
 static const struct intel_device_info intel_pineview_info = {
-        .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
+        .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
         .has_overlay = 1,
 };
 static const struct intel_device_info intel_ironlake_d_info = {
-        .gen = 5,
+        .gen = 5, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
         .has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_ironlake_m_info = {
-        .gen = 5, .is_mobile = 1,
+        .gen = 5, .is_mobile = 1, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
         .has_fbc = 1,
         .has_bsd_ring = 1,
 ,7 → 235,7
 };
 static const struct intel_device_info intel_sandybridge_d_info = {
-    .gen = 6,
+        .gen = 6, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
     .has_bsd_ring = 1,
     .has_blt_ring = 1,
 ,7 → 244,7
 };
 static const struct intel_device_info intel_sandybridge_m_info = {
-        .gen = 6, .is_mobile = 1,
+        .gen = 6, .is_mobile = 1, .num_pipes = 2,
         .need_gfx_hws = 1, .has_hotplug = 1,
     .has_fbc      = 1,
     .has_bsd_ring = 1,
 ,61 → 253,57
         .has_force_wake = 1,
 };
+#define GEN7_FEATURES  \
+        .gen = 7, .num_pipes = 3, \
+        .need_gfx_hws = 1, .has_hotplug = 1, \
+        .has_bsd_ring = 1, \
+        .has_blt_ring = 1, \
+        .has_llc = 1, \
+        .has_force_wake = 1
 static const struct intel_device_info intel_ivybridge_d_info = {
-        .is_ivybridge = 1, .gen = 7,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
-        .has_llc = 1,
-        .has_force_wake = 1,
+        GEN7_FEATURES,
+        .is_ivybridge = 1,
 };
 static const struct intel_device_info intel_ivybridge_m_info = {
-        .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
-        .has_llc = 1,
-        .has_force_wake = 1,
+        GEN7_FEATURES,
+        .is_ivybridge = 1,
+        .is_mobile = 1,
 };
+static const struct intel_device_info intel_ivybridge_q_info = {
+        GEN7_FEATURES,
+        .is_ivybridge = 1,
+        .num_pipes = 0, /* legal, last one wins */
+};
 static const struct intel_device_info intel_valleyview_m_info = {
-        .gen = 7, .is_mobile = 1,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_fbc = 0,
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
+        GEN7_FEATURES,
+        .is_mobile = 1,
+        .num_pipes = 2,
         .is_valleyview = 1,
         .display_mmio_offset = VLV_DISPLAY_BASE,
+        .has_llc = 0, /* legal, last one wins */
 };
 static const struct intel_device_info intel_valleyview_d_info = {
-        .gen = 7,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_fbc = 0,
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
+        GEN7_FEATURES,
+        .num_pipes = 2,
         .is_valleyview = 1,
         .display_mmio_offset = VLV_DISPLAY_BASE,
+        .has_llc = 0, /* legal, last one wins */
 };
 static const struct intel_device_info intel_haswell_d_info = {
-        .is_haswell = 1, .gen = 7,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
-        .has_llc = 1,
-        .has_force_wake = 1,
+        GEN7_FEATURES,
+        .is_haswell = 1,
 };
 static const struct intel_device_info intel_haswell_m_info = {
-        .is_haswell = 1, .gen = 7, .is_mobile = 1,
-        .need_gfx_hws = 1, .has_hotplug = 1,
-        .has_bsd_ring = 1,
-        .has_blt_ring = 1,
-        .has_llc = 1,
-        .has_force_wake = 1,
+        GEN7_FEATURES,
+        .is_haswell = 1,
+        .is_mobile = 1,
 };
 static const struct pci_device_id pciidlist[] = {       /* aka */
 ,44 → 345,72
         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+        INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
-        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
+        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
-        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
+        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
+        INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
+        INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
-        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
-        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
-        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
+        INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
+        INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
-        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
-        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
-        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
+        INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
+        INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
-        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
-        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
-        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
+        INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
+        INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+        INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
+        INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
+        INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
     {0, 0, 0}
 ,6 → 427,15
     struct drm_i915_private *dev_priv = dev->dev_private;
     struct pci_dev *pch;
+        /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
+         * (which really amounts to a PCH but no South Display).
+         */
+        if (INTEL_INFO(dev)->num_pipes == 0) {
+                dev_priv->pch_type = PCH_NOP;
+                dev_priv->num_pch_pll = 0;
+                return;
+        }
     /*
      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
      * make graphics device passthrough work easy for VMM, that only
 ,11 → 470,13
                                 dev_priv->num_pch_pll = 0;
                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
                                 WARN_ON(!IS_HASWELL(dev));
+                                WARN_ON(IS_ULT(dev));
                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_LPT;
                                 dev_priv->num_pch_pll = 0;
                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
                                 WARN_ON(!IS_HASWELL(dev));
+                                WARN_ON(!IS_ULT(dev));
             }
                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
         }
 ,6 → 769,11
         return true;
 }
+/* We give fast paths for the really cool registers */
+#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+        ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
+         ((reg) < 0x40000) &&            \
+         ((reg) != FORCEWAKE))
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)
 {
 ,6 → 783,27
         I915_WRITE_NOTRACE(MI_MODE, 0);
 }
+static void
+hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
+{
+        if (IS_HASWELL(dev_priv->dev) &&
+            (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
+                DRM_ERROR("Unknown unclaimed register before writing to %x\n",
+                          reg);
+                I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+        }
+}
+static void
+hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
+{
+        if (IS_HASWELL(dev_priv->dev) &&
+            (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
+                DRM_ERROR("Unclaimed write to %x\n", reg);
+                I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+        }
+}
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
         u##x val = 0; \
 ,18 → 839,12
         } \
         if (IS_GEN5(dev_priv->dev)) \
                 ilk_dummy_write(dev_priv); \
-        if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
-                DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
-                I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
-        } \
+        hsw_unclaimed_reg_clear(dev_priv, reg); \
         write##y(val, dev_priv->regs + reg); \
         if (unlikely(__fifo_ret)) { \
                 gen6_gt_check_fifodbg(dev_priv); \
         } \
-        if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
-                DRM_ERROR("Unclaimed write to %x\n", reg); \
-                writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
-        } \
+        hsw_unclaimed_reg_check(dev_priv, reg); \
 }
 __i915_write(8, b)
 __i915_write(16, w)

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Regard whitespace Rev 3745 → Rev 3746