| 45,7 → 45,6 |
|---|
| |
| void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen); |
| |
| |
| #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
| |
| #define BEGIN_LP_RING(n) \ |
| 1004,8 → 1003,7 |
|---|
| value = 1; |
| break; |
| default: |
| DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
| param->param); |
| DRM_DEBUG("Unknown parameter %d\n", param->param); |
| return -EINVAL; |
| } |
| |
| 1150,8 → 1148,8 |
|---|
| if (ret) |
| DRM_INFO("failed to find VBIOS tables\n"); |
| |
| // intel_register_dsm_handler(); |
| |
| |
| /* Initialise stolen first so that we may reserve preallocated |
| * objects for the BIOS to KMS transition. |
| */ |
| 1177,10 → 1175,8 |
|---|
| /* Always safe in the mode setting case. */ |
| /* FIXME: do pre/post-mode set stuff in core KMS code */ |
| dev->vblank_disable_allowed = 1; |
| if (INTEL_INFO(dev)->num_pipes == 0) { |
| dev_priv->mm.suspended = 0; |
| if (INTEL_INFO(dev)->num_pipes == 0) |
| return 0; |
| } |
| |
| ret = intel_fbdev_init(dev); |
| if (ret) |
| 1206,9 → 1202,6 |
|---|
| |
| drm_kms_helper_poll_init(dev); |
| |
| /* We're off and running w/KMS */ |
| dev_priv->mm.suspended = 0; |
| |
| return 0; |
| |
| cleanup_gem: |
| 1235,34 → 1228,22 |
|---|
| { |
| const struct intel_device_info *info = dev_priv->info; |
| |
| #define DEV_INFO_FLAG(name) info->name ? #name "," : "" |
| #define DEV_INFO_SEP , |
| #define PRINT_S(name) "%s" |
| #define SEP_EMPTY |
| #define PRINT_FLAG(name) info->name ? #name "," : "" |
| #define SEP_COMMA , |
| DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" |
| "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
| info->gen, |
| dev_priv->dev->pdev->device, |
| DEV_INFO_FLAGS); |
| #undef DEV_INFO_FLAG |
| #undef DEV_INFO_SEP |
| DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
| #undef PRINT_S |
| #undef SEP_EMPTY |
| #undef PRINT_FLAG |
| #undef SEP_COMMA |
| } |
| |
| /** |
| * intel_early_sanitize_regs - clean up BIOS state |
| * @dev: DRM device |
| * |
| * This function must be called before we do any I915_READ or I915_WRITE. Its |
| * purpose is to clean up any state left by the BIOS that may affect us when |
| * reading and/or writing registers. |
| */ |
| static void intel_early_sanitize_regs(struct drm_device *dev) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| |
| if (IS_HASWELL(dev)) |
| I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| } |
| |
| /** |
| * i915_driver_load - setup chip and create an initial config |
| * @dev: DRM device |
| * @flags: startup flags |
| 1291,8 → 1272,33 |
|---|
| dev_priv->dev = dev; |
| dev_priv->info = info; |
| |
| spin_lock_init(&dev_priv->irq_lock); |
| spin_lock_init(&dev_priv->gpu_error.lock); |
| spin_lock_init(&dev_priv->backlight.lock); |
| spin_lock_init(&dev_priv->uncore.lock); |
| spin_lock_init(&dev_priv->mm.object_stat_lock); |
| mutex_init(&dev_priv->dpio_lock); |
| mutex_init(&dev_priv->rps.hw_lock); |
| mutex_init(&dev_priv->modeset_restore_lock); |
| |
| mutex_init(&dev_priv->pc8.lock); |
| dev_priv->pc8.requirements_met = false; |
| dev_priv->pc8.gpu_idle = false; |
| dev_priv->pc8.irqs_disabled = false; |
| dev_priv->pc8.enabled = false; |
| dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */ |
| INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work); |
| |
| i915_dump_device_info(dev_priv); |
| |
| /* Not all pre-production machines fall into this category, only the |
| * very first ones. Almost everything should work, except for maybe |
| * suspend/resume. And we don't implement workarounds that affect only |
| * pre-production machines. */ |
| if (IS_HSW_EARLY_SDV(dev)) |
| DRM_INFO("This is an early pre-production Haswell machine. " |
| "It may not be fully functional.\n"); |
| |
| if (i915_get_bridge_dev(dev)) { |
| ret = -EIO; |
| goto free_priv; |
| 1318,8 → 1324,18 |
|---|
| goto put_bridge; |
| } |
| |
| intel_early_sanitize_regs(dev); |
| intel_uncore_early_sanitize(dev); |
| |
| if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) { |
| /* The docs do not explain exactly how the calculation can be |
| * made. It is somewhat guessable, but for now, it's always |
| * 128MB. |
| * NB: We can't write IDICR yet because we do not have gt funcs |
| * set up */ |
| dev_priv->ellc_size = 128; |
| DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| } |
| |
| ret = i915_gem_gtt_init(dev); |
| if (ret) |
| goto put_bridge; |
| 1366,7 → 1382,9 |
|---|
| intel_detect_pch(dev); |
| |
| intel_irq_init(dev); |
| intel_gt_init(dev); |
| intel_pm_init(dev); |
| intel_uncore_sanitize(dev); |
| intel_uncore_init(dev); |
| |
| /* Try to make sure MCHBAR is enabled before poking at it */ |
| intel_setup_mchbar(dev); |
| 1389,25 → 1407,10 |
|---|
| * stuck interrupts on some machines. |
| */ |
| |
| spin_lock_init(&dev_priv->irq_lock); |
| spin_lock_init(&dev_priv->gpu_error.lock); |
| spin_lock_init(&dev_priv->rps.lock); |
| mutex_init(&dev_priv->dpio_lock); |
| |
| mutex_init(&dev_priv->rps.hw_lock); |
| mutex_init(&dev_priv->modeset_restore_lock); |
| |
| dev_priv->num_plane = 1; |
| if (IS_VALLEYVIEW(dev)) |
| dev_priv->num_plane = 2; |
| |
| // ret = drm_vblank_init(dev, dev_priv->num_pipe); |
| // if (ret) |
| // goto out_gem_unload; |
| |
| /* Start out suspended */ |
| dev_priv->mm.suspended = 1; |
| |
| ret = i915_load_modeset_init(dev); |
| if (ret < 0) { |
| DRM_ERROR("failed to init modeset\n"); |
| 1420,6 → 1423,8 |
|---|
| if (IS_GEN5(dev)) |
| intel_gpu_ips_init(dev_priv); |
| |
| main_device = dev; |
| |
| return 0; |
| |
| out_gem_unload: |
| 1433,17 → 1438,11 |
|---|
| // intel_teardown_mchbar(dev); |
| // destroy_workqueue(dev_priv->wq); |
| out_mtrrfree: |
| // if (dev_priv->mm.gtt_mtrr >= 0) { |
| // mtrr_del(dev_priv->mm.gtt_mtrr, |
| // dev_priv->mm.gtt_base_addr, |
| // aperture_size); |
| // dev_priv->mm.gtt_mtrr = -1; |
| // } |
| // io_mapping_free(dev_priv->mm.gtt_mapping); |
| // arch_phys_wc_del(dev_priv->mm.gtt_mtrr); |
| // io_mapping_free(dev_priv->gtt.mappable); |
| // dev_priv->gtt.gtt_remove(dev); |
| out_rmmap: |
| pci_iounmap(dev->pdev, dev_priv->regs); |
| put_gmch: |
| // dev_priv->gtt.gtt_remove(dev); |
| put_bridge: |
| // pci_dev_put(dev_priv->bridge_dev); |
| free_priv: |
| 1460,9 → 1459,17 |
|---|
| |
| intel_gpu_ips_teardown(); |
| |
| if (HAS_POWER_WELL(dev)) { |
| /* The i915.ko module is still not prepared to be loaded when |
| * the power well is not enabled, so just enable it in case |
| * we're going to unload/reload. */ |
| intel_set_power_well(dev, true); |
| i915_remove_power_well(dev); |
| } |
| |
| i915_teardown_sysfs(dev); |
| |
| if (dev_priv->mm.inactive_shrinker.shrink) |
| if (dev_priv->mm.inactive_shrinker.scan_objects) |
| unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| |
| mutex_lock(&dev->struct_mutex); |
| 1476,12 → 1483,7 |
|---|
| cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| |
| io_mapping_free(dev_priv->gtt.mappable); |
| if (dev_priv->mm.gtt_mtrr >= 0) { |
| mtrr_del(dev_priv->mm.gtt_mtrr, |
| dev_priv->gtt.mappable_base, |
| dev_priv->gtt.mappable_end); |
| dev_priv->mm.gtt_mtrr = -1; |
| } |
| arch_phys_wc_del(dev_priv->gtt.mtrr); |
| |
| acpi_video_unregister(); |
| |
| 1494,10 → 1496,10 |
|---|
| * free the memory space allocated for the child device |
| * config parsed from VBT |
| */ |
| if (dev_priv->child_dev && dev_priv->child_dev_num) { |
| kfree(dev_priv->child_dev); |
| dev_priv->child_dev = NULL; |
| dev_priv->child_dev_num = 0; |
| if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
| kfree(dev_priv->vbt.child_dev); |
| dev_priv->vbt.child_dev = NULL; |
| dev_priv->vbt.child_dev_num = 0; |
| } |
| |
| vga_switcheroo_unregister_client(dev->pdev); |
| 1530,6 → 1532,9 |
|---|
| i915_free_hws(dev); |
| } |
| |
| list_del(&dev_priv->gtt.base.global_link); |
| WARN_ON(!list_empty(&dev_priv->vm_list)); |
| drm_mm_takedown(&dev_priv->gtt.base.mm); |
| if (dev_priv->regs != NULL) |
| pci_iounmap(dev->pdev, dev_priv->regs); |
| |
| 1539,6 → 1544,8 |
|---|
| destroy_workqueue(dev_priv->wq); |
| pm_qos_remove_request(&dev_priv->pm_qos); |
| |
| dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
| |
| if (dev_priv->slab) |
| kmem_cache_destroy(dev_priv->slab); |
| |
| 1615,7 → 1622,7 |
|---|
| kfree(file_priv); |
| } |
| |
| struct drm_ioctl_desc i915_ioctls[] = { |
| const struct drm_ioctl_desc i915_ioctls[] = { |
| DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), |
| 1622,7 → 1629,7 |
|---|
| DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
| DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), |
| 1635,35 → 1642,35 |
|---|
| DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED), |
| DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| }; |
| |
| int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |