/drivers/video/drm/radeon/kgd_kfd_interface.h |
---|
0,0 → 1,227 |
/* |
* Copyright 2014 Advanced Micro Devices, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
*/ |
/* |
* This file defines the private interface between the |
* AMD kernel graphics drivers and the AMD KFD. |
*/ |
#ifndef KGD_KFD_INTERFACE_H_INCLUDED |
#define KGD_KFD_INTERFACE_H_INCLUDED |
#include <linux/types.h> |
struct pci_dev; |
#define KFD_INTERFACE_VERSION 1 |
struct kfd_dev; |
struct kgd_dev; |
struct kgd_mem; |
enum kgd_memory_pool { |
KGD_POOL_SYSTEM_CACHEABLE = 1, |
KGD_POOL_SYSTEM_WRITECOMBINE = 2, |
KGD_POOL_FRAMEBUFFER = 3, |
}; |
enum kgd_engine_type { |
KGD_ENGINE_PFP = 1, |
KGD_ENGINE_ME, |
KGD_ENGINE_CE, |
KGD_ENGINE_MEC1, |
KGD_ENGINE_MEC2, |
KGD_ENGINE_RLC, |
KGD_ENGINE_SDMA1, |
KGD_ENGINE_SDMA2, |
KGD_ENGINE_MAX |
}; |
struct kgd2kfd_shared_resources { |
/* Bit n == 1 means VMID n is available for KFD. */ |
unsigned int compute_vmid_bitmap; |
/* Compute pipes are counted starting from MEC0/pipe0 as 0. */ |
unsigned int first_compute_pipe; |
/* Number of MEC pipes available for KFD. */ |
unsigned int compute_pipe_count; |
/* Base address of doorbell aperture. */ |
phys_addr_t doorbell_physical_address; |
/* Size in bytes of doorbell aperture. */ |
size_t doorbell_aperture_size; |
/* Number of bytes at start of aperture reserved for KGD. */ |
size_t doorbell_start_offset; |
}; |
/** |
* struct kfd2kgd_calls |
* |
* @init_gtt_mem_allocation: Allocate a buffer on the gart aperture. |
* The buffer can be used for mqds, hpds, kernel queue, fence and runlists |
* |
* @free_gtt_mem: Frees a buffer that was allocated on the gart aperture |
* |
* @get_vmem_size: Retrieves (physical) size of VRAM |
* |
* @get_gpu_clock_counter: Retrieves GPU clock counter |
* |
* @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz |
* |
* @program_sh_mem_settings: A function that should initiate the memory |
* properties such as main aperture memory type (cache / non cached) and |
* secondary aperture base address, size and memory type. |
* This function is used only for no cp scheduling mode. |
* |
* @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp |
* scheduling mode. Only used for no cp scheduling mode. |
* |
* @init_pipeline: Initialized the compute pipelines. |
* |
* @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp |
* sceduling mode. |
* |
* @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot. |
* used only for no HWS mode. |
* |
* @hqd_is_occupies: Checks if a hqd slot is occupied. |
* |
* @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot. |
* |
* @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied. |
* |
* @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that |
* SDMA hqd slot. |
* |
* @get_fw_version: Returns FW versions from the header |
* |
* This structure contains function pointers to services that the kgd driver |
* provides to amdkfd driver. |
* |
*/ |
struct kfd2kgd_calls { |
int (*init_gtt_mem_allocation)(struct kgd_dev *kgd, size_t size, |
void **mem_obj, uint64_t *gpu_addr, |
void **cpu_ptr); |
void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj); |
uint64_t (*get_vmem_size)(struct kgd_dev *kgd); |
uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd); |
uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd); |
/* Register access functions */ |
void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid, |
uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, |
uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); |
int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid, |
unsigned int vmid); |
int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id, |
uint32_t hpd_size, uint64_t hpd_gpu_addr); |
int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); |
int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, |
uint32_t queue_id, uint32_t __user *wptr); |
int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd); |
bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, |
uint32_t pipe_id, uint32_t queue_id); |
int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type, |
unsigned int timeout, uint32_t pipe_id, |
uint32_t queue_id); |
bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd); |
int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd, |
unsigned int timeout); |
int (*address_watch_disable)(struct kgd_dev *kgd); |
int (*address_watch_execute)(struct kgd_dev *kgd, |
unsigned int watch_point_id, |
uint32_t cntl_val, |
uint32_t addr_hi, |
uint32_t addr_lo); |
int (*wave_control_execute)(struct kgd_dev *kgd, |
uint32_t gfx_index_val, |
uint32_t sq_cmd); |
uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, |
unsigned int watch_point_id, |
unsigned int reg_offset); |
bool (*get_atc_vmid_pasid_mapping_valid)( |
struct kgd_dev *kgd, |
uint8_t vmid); |
uint16_t (*get_atc_vmid_pasid_mapping_pasid)( |
struct kgd_dev *kgd, |
uint8_t vmid); |
void (*write_vmid_invalidate_request)(struct kgd_dev *kgd, |
uint8_t vmid); |
uint16_t (*get_fw_version)(struct kgd_dev *kgd, |
enum kgd_engine_type type); |
}; |
/** |
* struct kgd2kfd_calls |
* |
* @exit: Notifies amdkfd that kgd module is unloaded |
* |
* @probe: Notifies amdkfd about a probe done on a device in the kgd driver. |
* |
* @device_init: Initialize the newly probed device (if it is a device that |
* amdkfd supports) |
* |
* @device_exit: Notifies amdkfd about a removal of a kgd device |
* |
* @suspend: Notifies amdkfd about a suspend action done to a kgd device |
* |
* @resume: Notifies amdkfd about a resume action done to a kgd device |
* |
* This structure contains function callback pointers so the kgd driver |
* will notify to the amdkfd about certain status changes. |
* |
*/ |
struct kgd2kfd_calls { |
void (*exit)(void); |
struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev, |
const struct kfd2kgd_calls *f2g); |
bool (*device_init)(struct kfd_dev *kfd, |
const struct kgd2kfd_shared_resources *gpu_resources); |
void (*device_exit)(struct kfd_dev *kfd); |
void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry); |
void (*suspend)(struct kfd_dev *kfd); |
int (*resume)(struct kfd_dev *kfd); |
}; |
bool kgd2kfd_init(unsigned interface_version, |
const struct kgd2kfd_calls **g2f); |
#endif /* KGD_KFD_INTERFACE_H_INCLUDED */ |
/drivers/video/drm/radeon/radeon_audio.c |
---|
0,0 → 1,783 |
/* |
* Copyright 2014 Advanced Micro Devices, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Slava Grigorev <slava.grigorev@amd.com> |
*/ |
//#include <linux/gcd.h> |
#include <drm/drmP.h> |
#include <drm/drm_crtc.h> |
#include "radeon.h" |
#include "atom.h" |
#include "radeon_audio.h" |
void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
u8 enable_mask); |
void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
u8 enable_mask); |
void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, |
u8 enable_mask); |
u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg); |
void dce6_endpoint_wreg(struct radeon_device *rdev, |
u32 offset, u32 reg, u32 v); |
void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder, |
struct cea_sad *sads, int sad_count); |
void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
struct cea_sad *sads, int sad_count); |
void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, |
struct cea_sad *sads, int sad_count); |
void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
struct drm_connector *connector, struct drm_display_mode *mode); |
void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
struct drm_connector *connector, struct drm_display_mode *mode); |
struct r600_audio_pin* r600_audio_get_pin(struct radeon_device *rdev); |
struct r600_audio_pin* dce6_audio_get_pin(struct radeon_device *rdev); |
void dce6_afmt_select_pin(struct drm_encoder *encoder); |
void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void dce3_2_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void dce6_dp_audio_set_dto(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, |
unsigned char *buffer, size_t size); |
void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
unsigned char *buffer, size_t size); |
void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
const struct radeon_hdmi_acr *acr); |
void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
const struct radeon_hdmi_acr *acr); |
void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
const struct radeon_hdmi_acr *acr); |
void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset); |
void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset); |
void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, |
u32 offset, int bpc); |
void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset); |
void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset); |
void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset); |
void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute); |
void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute); |
void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute); |
static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); |
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); |
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable); |
static const u32 pin_offsets[7] = |
{ |
(0x5e00 - 0x5e00), |
(0x5e18 - 0x5e00), |
(0x5e30 - 0x5e00), |
(0x5e48 - 0x5e00), |
(0x5e60 - 0x5e00), |
(0x5e78 - 0x5e00), |
(0x5e90 - 0x5e00), |
}; |
static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg) |
{ |
return RREG32(reg); |
} |
static void radeon_audio_wreg(struct radeon_device *rdev, u32 offset, |
u32 reg, u32 v) |
{ |
WREG32(reg, v); |
} |
static struct radeon_audio_basic_funcs r600_funcs = { |
.endpoint_rreg = radeon_audio_rreg, |
.endpoint_wreg = radeon_audio_wreg, |
.enable = r600_audio_enable, |
}; |
static struct radeon_audio_basic_funcs dce32_funcs = { |
.endpoint_rreg = radeon_audio_rreg, |
.endpoint_wreg = radeon_audio_wreg, |
.enable = r600_audio_enable, |
}; |
static struct radeon_audio_basic_funcs dce4_funcs = { |
.endpoint_rreg = radeon_audio_rreg, |
.endpoint_wreg = radeon_audio_wreg, |
.enable = dce4_audio_enable, |
}; |
static struct radeon_audio_basic_funcs dce6_funcs = { |
.endpoint_rreg = dce6_endpoint_rreg, |
.endpoint_wreg = dce6_endpoint_wreg, |
.enable = dce6_audio_enable, |
}; |
static struct radeon_audio_funcs r600_hdmi_funcs = { |
.get_pin = r600_audio_get_pin, |
.set_dto = r600_hdmi_audio_set_dto, |
.update_acr = r600_hdmi_update_acr, |
.set_vbi_packet = r600_set_vbi_packet, |
.set_avi_packet = r600_set_avi_packet, |
.set_audio_packet = r600_set_audio_packet, |
.set_mute = r600_set_mute, |
.mode_set = radeon_audio_hdmi_mode_set, |
.dpms = r600_hdmi_enable, |
}; |
static struct radeon_audio_funcs dce32_hdmi_funcs = { |
.get_pin = r600_audio_get_pin, |
.write_sad_regs = dce3_2_afmt_write_sad_regs, |
.write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation, |
.set_dto = dce3_2_audio_set_dto, |
.update_acr = dce3_2_hdmi_update_acr, |
.set_vbi_packet = r600_set_vbi_packet, |
.set_avi_packet = r600_set_avi_packet, |
.set_audio_packet = dce3_2_set_audio_packet, |
.set_mute = dce3_2_set_mute, |
.mode_set = radeon_audio_hdmi_mode_set, |
.dpms = r600_hdmi_enable, |
}; |
static struct radeon_audio_funcs dce32_dp_funcs = { |
.get_pin = r600_audio_get_pin, |
.write_sad_regs = dce3_2_afmt_write_sad_regs, |
.write_speaker_allocation = dce3_2_afmt_dp_write_speaker_allocation, |
.set_dto = dce3_2_audio_set_dto, |
.set_avi_packet = r600_set_avi_packet, |
.set_audio_packet = dce3_2_set_audio_packet, |
}; |
static struct radeon_audio_funcs dce4_hdmi_funcs = { |
.get_pin = r600_audio_get_pin, |
.write_sad_regs = evergreen_hdmi_write_sad_regs, |
.write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation, |
.write_latency_fields = dce4_afmt_write_latency_fields, |
.set_dto = dce4_hdmi_audio_set_dto, |
.update_acr = evergreen_hdmi_update_acr, |
.set_vbi_packet = dce4_set_vbi_packet, |
.set_color_depth = dce4_hdmi_set_color_depth, |
.set_avi_packet = evergreen_set_avi_packet, |
.set_audio_packet = dce4_set_audio_packet, |
.set_mute = dce4_set_mute, |
.mode_set = radeon_audio_hdmi_mode_set, |
.dpms = evergreen_hdmi_enable, |
}; |
static struct radeon_audio_funcs dce4_dp_funcs = { |
.get_pin = r600_audio_get_pin, |
.write_sad_regs = evergreen_hdmi_write_sad_regs, |
.write_speaker_allocation = dce4_afmt_dp_write_speaker_allocation, |
.write_latency_fields = dce4_afmt_write_latency_fields, |
.set_dto = dce4_dp_audio_set_dto, |
.set_avi_packet = evergreen_set_avi_packet, |
.set_audio_packet = dce4_set_audio_packet, |
.mode_set = radeon_audio_dp_mode_set, |
.dpms = evergreen_dp_enable, |
}; |
static struct radeon_audio_funcs dce6_hdmi_funcs = { |
.select_pin = dce6_afmt_select_pin, |
.get_pin = dce6_audio_get_pin, |
.write_sad_regs = dce6_afmt_write_sad_regs, |
.write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation, |
.write_latency_fields = dce6_afmt_write_latency_fields, |
.set_dto = dce6_hdmi_audio_set_dto, |
.update_acr = evergreen_hdmi_update_acr, |
.set_vbi_packet = dce4_set_vbi_packet, |
.set_color_depth = dce4_hdmi_set_color_depth, |
.set_avi_packet = evergreen_set_avi_packet, |
.set_audio_packet = dce4_set_audio_packet, |
.set_mute = dce4_set_mute, |
.mode_set = radeon_audio_hdmi_mode_set, |
.dpms = evergreen_hdmi_enable, |
}; |
static struct radeon_audio_funcs dce6_dp_funcs = { |
.select_pin = dce6_afmt_select_pin, |
.get_pin = dce6_audio_get_pin, |
.write_sad_regs = dce6_afmt_write_sad_regs, |
.write_speaker_allocation = dce6_afmt_dp_write_speaker_allocation, |
.write_latency_fields = dce6_afmt_write_latency_fields, |
.set_dto = dce6_dp_audio_set_dto, |
.set_avi_packet = evergreen_set_avi_packet, |
.set_audio_packet = dce4_set_audio_packet, |
.mode_set = radeon_audio_dp_mode_set, |
.dpms = evergreen_dp_enable, |
}; |
static void radeon_audio_enable(struct radeon_device *rdev, |
struct r600_audio_pin *pin, u8 enable_mask) |
{ |
struct drm_encoder *encoder; |
struct radeon_encoder *radeon_encoder; |
struct radeon_encoder_atom_dig *dig; |
int pin_count = 0; |
if (!pin) |
return; |
if (rdev->mode_info.mode_config_initialized) { |
list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) { |
if (radeon_encoder_is_digital(encoder)) { |
radeon_encoder = to_radeon_encoder(encoder); |
dig = radeon_encoder->enc_priv; |
if (dig->pin == pin) |
pin_count++; |
} |
} |
if ((pin_count > 1) && (enable_mask == 0)) |
return; |
} |
if (rdev->audio.funcs->enable) |
rdev->audio.funcs->enable(rdev, pin, enable_mask); |
} |
static void radeon_audio_interface_init(struct radeon_device *rdev) |
{ |
if (ASIC_IS_DCE6(rdev)) { |
rdev->audio.funcs = &dce6_funcs; |
rdev->audio.hdmi_funcs = &dce6_hdmi_funcs; |
rdev->audio.dp_funcs = &dce6_dp_funcs; |
} else if (ASIC_IS_DCE4(rdev)) { |
rdev->audio.funcs = &dce4_funcs; |
rdev->audio.hdmi_funcs = &dce4_hdmi_funcs; |
rdev->audio.dp_funcs = &dce4_dp_funcs; |
} else if (ASIC_IS_DCE32(rdev)) { |
rdev->audio.funcs = &dce32_funcs; |
rdev->audio.hdmi_funcs = &dce32_hdmi_funcs; |
rdev->audio.dp_funcs = &dce32_dp_funcs; |
} else { |
rdev->audio.funcs = &r600_funcs; |
rdev->audio.hdmi_funcs = &r600_hdmi_funcs; |
rdev->audio.dp_funcs = 0; |
} |
} |
static int radeon_audio_chipset_supported(struct radeon_device *rdev) |
{ |
return ASIC_IS_DCE2(rdev) && !ASIC_IS_NODCE(rdev); |
} |
int radeon_audio_init(struct radeon_device *rdev) |
{ |
int i; |
if (!radeon_audio || !radeon_audio_chipset_supported(rdev)) |
return 0; |
rdev->audio.enabled = true; |
if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */ |
rdev->audio.num_pins = 3; |
else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */ |
rdev->audio.num_pins = 7; |
else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */ |
rdev->audio.num_pins = 7; |
else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */ |
rdev->audio.num_pins = 2; |
else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */ |
rdev->audio.num_pins = 6; |
else if (ASIC_IS_DCE6(rdev)) /* SI: 6 streams, 6 endpoints */ |
rdev->audio.num_pins = 6; |
else |
rdev->audio.num_pins = 1; |
for (i = 0; i < rdev->audio.num_pins; i++) { |
rdev->audio.pin[i].channels = -1; |
rdev->audio.pin[i].rate = -1; |
rdev->audio.pin[i].bits_per_sample = -1; |
rdev->audio.pin[i].status_bits = 0; |
rdev->audio.pin[i].category_code = 0; |
rdev->audio.pin[i].connected = false; |
rdev->audio.pin[i].offset = pin_offsets[i]; |
rdev->audio.pin[i].id = i; |
} |
radeon_audio_interface_init(rdev); |
/* disable audio. it will be set up later */ |
for (i = 0; i < rdev->audio.num_pins; i++) |
radeon_audio_enable(rdev, &rdev->audio.pin[i], 0); |
return 0; |
} |
u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg) |
{ |
if (rdev->audio.funcs->endpoint_rreg) |
return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg); |
return 0; |
} |
void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset, |
u32 reg, u32 v) |
{ |
if (rdev->audio.funcs->endpoint_wreg) |
rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v); |
} |
static void radeon_audio_write_sad_regs(struct drm_encoder *encoder) |
{ |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct cea_sad *sads; |
int sad_count; |
if (!connector) |
return; |
sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
if (sad_count <= 0) { |
DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
return; |
} |
BUG_ON(!sads); |
if (radeon_encoder->audio && radeon_encoder->audio->write_sad_regs) |
radeon_encoder->audio->write_sad_regs(encoder, sads, sad_count); |
kfree(sads); |
} |
static void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder) |
{ |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
u8 *sadb = NULL; |
int sad_count; |
if (!connector) |
return; |
sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), |
&sadb); |
if (sad_count < 0) { |
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", |
sad_count); |
sad_count = 0; |
} |
if (radeon_encoder->audio && radeon_encoder->audio->write_speaker_allocation) |
radeon_encoder->audio->write_speaker_allocation(encoder, sadb, sad_count); |
kfree(sadb); |
} |
static void radeon_audio_write_latency_fields(struct drm_encoder *encoder, |
struct drm_display_mode *mode) |
{ |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
if (!connector) |
return; |
if (radeon_encoder->audio && radeon_encoder->audio->write_latency_fields) |
radeon_encoder->audio->write_latency_fields(encoder, connector, mode); |
} |
struct r600_audio_pin* radeon_audio_get_pin(struct drm_encoder *encoder) |
{ |
struct radeon_device *rdev = encoder->dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
if (radeon_encoder->audio && radeon_encoder->audio->get_pin) |
return radeon_encoder->audio->get_pin(rdev); |
return NULL; |
} |
static void radeon_audio_select_pin(struct drm_encoder *encoder) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
if (radeon_encoder->audio && radeon_encoder->audio->select_pin) |
radeon_encoder->audio->select_pin(encoder); |
} |
void radeon_audio_detect(struct drm_connector *connector, |
struct drm_encoder *encoder, |
enum drm_connector_status status) |
{ |
struct drm_device *dev = connector->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig; |
if (!radeon_audio_chipset_supported(rdev)) |
return; |
if (!radeon_encoder_is_digital(encoder)) |
return; |
dig = radeon_encoder->enc_priv; |
if (status == connector_status_connected) { |
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
if (radeon_dp_getsinktype(radeon_connector) == |
CONNECTOR_OBJECT_ID_DISPLAYPORT) |
radeon_encoder->audio = rdev->audio.dp_funcs; |
else |
radeon_encoder->audio = rdev->audio.hdmi_funcs; |
} else { |
radeon_encoder->audio = rdev->audio.hdmi_funcs; |
} |
if (drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
if (!dig->pin) |
dig->pin = radeon_audio_get_pin(encoder); |
radeon_audio_enable(rdev, dig->pin, 0xf); |
} else { |
radeon_audio_enable(rdev, dig->pin, 0); |
dig->pin = NULL; |
} |
} else { |
radeon_audio_enable(rdev, dig->pin, 0); |
dig->pin = NULL; |
} |
} |
void radeon_audio_fini(struct radeon_device *rdev) |
{ |
int i; |
if (!rdev->audio.enabled) |
return; |
for (i = 0; i < rdev->audio.num_pins; i++) |
radeon_audio_enable(rdev, &rdev->audio.pin[i], 0); |
rdev->audio.enabled = false; |
} |
static void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock) |
{ |
struct radeon_device *rdev = encoder->dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc); |
if (radeon_encoder->audio && radeon_encoder->audio->set_dto) |
radeon_encoder->audio->set_dto(rdev, crtc, clock); |
} |
static int radeon_audio_set_avi_packet(struct drm_encoder *encoder, |
struct drm_display_mode *mode) |
{ |
struct radeon_device *rdev = encoder->dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
struct hdmi_avi_infoframe frame; |
int err; |
if (!connector) |
return -EINVAL; |
err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
if (err < 0) { |
DRM_ERROR("failed to setup AVI infoframe: %d\n", err); |
return err; |
} |
if (radeon_encoder->output_csc != RADEON_OUTPUT_CSC_BYPASS) { |
if (drm_rgb_quant_range_selectable(radeon_connector_edid(connector))) { |
if (radeon_encoder->output_csc == RADEON_OUTPUT_CSC_TVRGB) |
frame.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; |
else |
frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; |
} else { |
frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; |
} |
} |
err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
if (err < 0) { |
DRM_ERROR("failed to pack AVI infoframe: %d\n", err); |
return err; |
} |
if (dig && dig->afmt && radeon_encoder->audio && |
radeon_encoder->audio->set_avi_packet) |
radeon_encoder->audio->set_avi_packet(rdev, dig->afmt->offset, |
buffer, sizeof(buffer)); |
return 0; |
} |
/* |
* calculate CTS and N values if they are not found in the table |
*/ |
static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq) |
{ |
int n, cts; |
unsigned long div, mul; |
/* Safe, but overly large values */ |
n = 128 * freq; |
cts = clock * 1000; |
/* Smallest valid fraction */ |
div = gcd(n, cts); |
n /= div; |
cts /= div; |
/* |
* The optimal N is 128*freq/1000. Calculate the closest larger |
* value that doesn't truncate any bits. |
*/ |
mul = ((128*freq/1000) + (n-1))/n; |
n *= mul; |
cts *= mul; |
/* Check that we are in spec (not always possible) */ |
if (n < (128*freq/1500)) |
printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); |
if (n > (128*freq/300)) |
printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); |
*N = n; |
*CTS = cts; |
DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", |
*N, *CTS, freq); |
} |
static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock) |
{ |
static struct radeon_hdmi_acr res; |
u8 i; |
static const struct radeon_hdmi_acr hdmi_predefined_acr[] = { |
/* 32kHz 44.1kHz 48kHz */ |
/* Clock N CTS N CTS N CTS */ |
{ 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ |
{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
{ 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ |
{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
{ 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ |
{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
}; |
/* Precalculated values for common clocks */ |
for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++) |
if (hdmi_predefined_acr[i].clock == clock) |
return &hdmi_predefined_acr[i]; |
/* And odd clocks get manually calculated */ |
radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); |
radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); |
radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); |
return &res; |
} |
/* |
* update the N and CTS parameters for a given pixel clock rate |
*/ |
static void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock) |
{ |
const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
if (!dig || !dig->afmt) |
return; |
if (radeon_encoder->audio && radeon_encoder->audio->update_acr) |
radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); |
} |
static void radeon_audio_set_vbi_packet(struct drm_encoder *encoder) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
if (!dig || !dig->afmt) |
return; |
if (radeon_encoder->audio && radeon_encoder->audio->set_vbi_packet) |
radeon_encoder->audio->set_vbi_packet(encoder, dig->afmt->offset); |
} |
static void radeon_hdmi_set_color_depth(struct drm_encoder *encoder) |
{ |
int bpc = 8; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
if (!dig || !dig->afmt) |
return; |
if (encoder->crtc) { |
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
bpc = radeon_crtc->bpc; |
} |
if (radeon_encoder->audio && radeon_encoder->audio->set_color_depth) |
radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc); |
} |
static void radeon_audio_set_audio_packet(struct drm_encoder *encoder) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
if (!dig || !dig->afmt) |
return; |
if (radeon_encoder->audio && radeon_encoder->audio->set_audio_packet) |
radeon_encoder->audio->set_audio_packet(encoder, dig->afmt->offset); |
} |
static void radeon_audio_set_mute(struct drm_encoder *encoder, bool mute) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
if (!dig || !dig->afmt) |
return; |
if (radeon_encoder->audio && radeon_encoder->audio->set_mute) |
radeon_encoder->audio->set_mute(encoder, dig->afmt->offset, mute); |
} |
/* |
* update the info frames with the data from the current display mode |
*/ |
static void radeon_audio_hdmi_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
if (!dig || !dig->afmt) |
return; |
if (!connector) |
return; |
if (drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
radeon_audio_set_mute(encoder, true); |
radeon_audio_write_speaker_allocation(encoder); |
radeon_audio_write_sad_regs(encoder); |
radeon_audio_write_latency_fields(encoder, mode); |
radeon_audio_set_dto(encoder, mode->clock); |
radeon_audio_set_vbi_packet(encoder); |
radeon_hdmi_set_color_depth(encoder); |
radeon_audio_update_acr(encoder, mode->clock); |
radeon_audio_set_audio_packet(encoder); |
radeon_audio_select_pin(encoder); |
if (radeon_audio_set_avi_packet(encoder, mode) < 0) |
return; |
radeon_audio_set_mute(encoder, false); |
} else { |
radeon_hdmi_set_color_depth(encoder); |
if (radeon_audio_set_avi_packet(encoder, mode) < 0) |
return; |
} |
} |
static void radeon_audio_dp_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode) |
{ |
struct drm_device *dev = encoder->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
struct radeon_connector_atom_dig *dig_connector = |
radeon_connector->con_priv; |
if (!dig || !dig->afmt) |
return; |
if (!connector) |
return; |
if (drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
radeon_audio_write_speaker_allocation(encoder); |
radeon_audio_write_sad_regs(encoder); |
radeon_audio_write_latency_fields(encoder, mode); |
if (rdev->clock.dp_extclk || ASIC_IS_DCE5(rdev)) |
radeon_audio_set_dto(encoder, rdev->clock.default_dispclk * 10); |
else |
radeon_audio_set_dto(encoder, dig_connector->dp_clock); |
radeon_audio_set_audio_packet(encoder); |
radeon_audio_select_pin(encoder); |
if (radeon_audio_set_avi_packet(encoder, mode) < 0) |
return; |
} |
} |
void radeon_audio_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
if (radeon_encoder->audio && radeon_encoder->audio->mode_set) |
radeon_encoder->audio->mode_set(encoder, mode); |
} |
void radeon_audio_dpms(struct drm_encoder *encoder, int mode) |
{ |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
if (radeon_encoder->audio && radeon_encoder->audio->dpms) |
radeon_encoder->audio->dpms(encoder, mode == DRM_MODE_DPMS_ON); |
} |
/drivers/video/drm/radeon/radeon_audio.h |
---|
0,0 → 1,83 |
/* |
* Copyright 2014 Advanced Micro Devices, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Slava Grigorev <slava.grigorev@amd.com> |
*/ |
#ifndef __RADEON_AUDIO_H__ |
#define __RADEON_AUDIO_H__ |
#include <linux/types.h> |
#define RREG32_ENDPOINT(block, reg) \ |
radeon_audio_endpoint_rreg(rdev, (block), (reg)) |
#define WREG32_ENDPOINT(block, reg, v) \ |
radeon_audio_endpoint_wreg(rdev, (block), (reg), (v)) |
struct radeon_audio_basic_funcs |
{ |
u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg); |
void (*endpoint_wreg)(struct radeon_device *rdev, |
u32 offset, u32 reg, u32 v); |
void (*enable)(struct radeon_device *rdev, |
struct r600_audio_pin *pin, u8 enable_mask); |
}; |
struct radeon_audio_funcs |
{ |
void (*select_pin)(struct drm_encoder *encoder); |
struct r600_audio_pin* (*get_pin)(struct radeon_device *rdev); |
void (*write_latency_fields)(struct drm_encoder *encoder, |
struct drm_connector *connector, struct drm_display_mode *mode); |
void (*write_sad_regs)(struct drm_encoder *encoder, |
struct cea_sad *sads, int sad_count); |
void (*write_speaker_allocation)(struct drm_encoder *encoder, |
u8 *sadb, int sad_count); |
void (*set_dto)(struct radeon_device *rdev, |
struct radeon_crtc *crtc, unsigned int clock); |
void (*update_acr)(struct drm_encoder *encoder, long offset, |
const struct radeon_hdmi_acr *acr); |
void (*set_vbi_packet)(struct drm_encoder *encoder, u32 offset); |
void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc); |
void (*set_avi_packet)(struct radeon_device *rdev, u32 offset, |
unsigned char *buffer, size_t size); |
void (*set_audio_packet)(struct drm_encoder *encoder, u32 offset); |
void (*set_mute)(struct drm_encoder *encoder, u32 offset, bool mute); |
void (*mode_set)(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
void (*dpms)(struct drm_encoder *encoder, bool mode); |
}; |
int radeon_audio_init(struct radeon_device *rdev); |
void radeon_audio_detect(struct drm_connector *connector, |
struct drm_encoder *encoder, |
enum drm_connector_status status); |
u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, |
u32 offset, u32 reg); |
void radeon_audio_endpoint_wreg(struct radeon_device *rdev, |
u32 offset, u32 reg, u32 v); |
struct r600_audio_pin *radeon_audio_get_pin(struct drm_encoder *encoder); |
void radeon_audio_fini(struct radeon_device *rdev); |
void radeon_audio_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
void radeon_audio_dpms(struct drm_encoder *encoder, int mode); |
#endif |
/drivers/video/drm/radeon/radeon_dp_auxch.c |
---|
0,0 → 1,204 |
/* |
* Copyright 2015 Red Hat Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
*/ |
#include <drm/drmP.h> |
#include <drm/radeon_drm.h> |
#include "radeon.h" |
#include "nid.h" |
#define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ |
AUX_SW_RX_HPD_DISCON | \ |
AUX_SW_RX_PARTIAL_BYTE | \ |
AUX_SW_NON_AUX_MODE | \ |
AUX_SW_RX_SYNC_INVALID_L | \ |
AUX_SW_RX_SYNC_INVALID_H | \ |
AUX_SW_RX_INVALID_START | \ |
AUX_SW_RX_RECV_NO_DET | \ |
AUX_SW_RX_RECV_INVALID_H | \ |
AUX_SW_RX_RECV_INVALID_V) |
#define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) |
#define BARE_ADDRESS_SIZE 3 |
static const u32 aux_offset[] = |
{ |
0x6200 - 0x6200, |
0x6250 - 0x6200, |
0x62a0 - 0x6200, |
0x6300 - 0x6200, |
0x6350 - 0x6200, |
0x63a0 - 0x6200, |
}; |
ssize_t |
radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
{ |
struct radeon_i2c_chan *chan = |
container_of(aux, struct radeon_i2c_chan, aux); |
struct drm_device *dev = chan->dev; |
struct radeon_device *rdev = dev->dev_private; |
int ret = 0, i; |
uint32_t tmp, ack = 0; |
int instance = chan->rec.i2c_id & 0xf; |
u8 byte; |
u8 *buf = msg->buffer; |
int retry_count = 0; |
int bytes; |
int msize; |
bool is_write = false; |
if (WARN_ON(msg->size > 16)) |
return -E2BIG; |
switch (msg->request & ~DP_AUX_I2C_MOT) { |
case DP_AUX_NATIVE_WRITE: |
case DP_AUX_I2C_WRITE: |
is_write = true; |
break; |
case DP_AUX_NATIVE_READ: |
case DP_AUX_I2C_READ: |
break; |
default: |
return -EINVAL; |
} |
/* work out two sizes required */ |
msize = 0; |
bytes = BARE_ADDRESS_SIZE; |
if (msg->size) { |
msize = msg->size - 1; |
bytes++; |
if (is_write) |
bytes += msg->size; |
} |
mutex_lock(&chan->mutex); |
/* switch the pad to aux mode */ |
tmp = RREG32(chan->rec.mask_clk_reg); |
tmp |= (1 << 16); |
WREG32(chan->rec.mask_clk_reg, tmp); |
/* setup AUX control register with correct HPD pin */ |
tmp = RREG32(AUX_CONTROL + aux_offset[instance]); |
tmp &= AUX_HPD_SEL(0x7); |
tmp |= AUX_HPD_SEL(chan->rec.hpd); |
tmp |= AUX_EN | AUX_LS_READ_EN; |
WREG32(AUX_CONTROL + aux_offset[instance], tmp); |
/* atombios appears to write this twice lets copy it */ |
WREG32(AUX_SW_CONTROL + aux_offset[instance], |
AUX_SW_WR_BYTES(bytes)); |
WREG32(AUX_SW_CONTROL + aux_offset[instance], |
AUX_SW_WR_BYTES(bytes)); |
/* write the data header into the registers */ |
/* request, address, msg size */ |
byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); |
byte = (msg->address >> 8) & 0xff; |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_MASK(byte)); |
byte = msg->address & 0xff; |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_MASK(byte)); |
byte = msize; |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_MASK(byte)); |
/* if we are writing - write the msg buffer */ |
if (is_write) { |
for (i = 0; i < msg->size; i++) { |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_MASK(buf[i])); |
} |
} |
/* clear the ACK */ |
WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
/* write the size and GO bits */ |
WREG32(AUX_SW_CONTROL + aux_offset[instance], |
AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); |
/* poll the status registers - TODO irq support */ |
do { |
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); |
if (tmp & AUX_SW_DONE) { |
break; |
} |
usleep_range(100, 200); |
} while (retry_count++ < 1000); |
if (retry_count >= 1000) { |
DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); |
ret = -EIO; |
goto done; |
} |
if (tmp & AUX_SW_RX_TIMEOUT) { |
DRM_DEBUG_KMS("dp_aux_ch timed out\n"); |
ret = -ETIMEDOUT; |
goto done; |
} |
if (tmp & AUX_RX_ERROR_FLAGS) { |
DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); |
ret = -EIO; |
goto done; |
} |
bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); |
if (bytes) { |
WREG32(AUX_SW_DATA + aux_offset[instance], |
AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); |
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
ack = (tmp >> 8) & 0xff; |
for (i = 0; i < bytes - 1; i++) { |
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
if (buf) |
buf[i] = (tmp >> 8) & 0xff; |
} |
if (buf) |
ret = bytes - 1; |
} |
WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
if (is_write) |
ret = msg->size; |
done: |
mutex_unlock(&chan->mutex); |
if (ret >= 0) |
msg->reply = ack >> 4; |
return ret; |
} |
/drivers/video/drm/radeon/radeon_dp_mst.c |
---|
0,0 → 1,796 |
#include <drm/drmP.h> |
#include <drm/drm_dp_mst_helper.h> |
#include <drm/drm_fb_helper.h> |
#include "radeon.h" |
#include "atom.h" |
#include "ni_reg.h" |
static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector); |
static int radeon_atom_set_enc_offset(int id) |
{ |
static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, |
EVERGREEN_CRTC1_REGISTER_OFFSET, |
EVERGREEN_CRTC2_REGISTER_OFFSET, |
EVERGREEN_CRTC3_REGISTER_OFFSET, |
EVERGREEN_CRTC4_REGISTER_OFFSET, |
EVERGREEN_CRTC5_REGISTER_OFFSET, |
0x13830 - 0x7030 }; |
return offsets[id]; |
} |
static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary, |
struct radeon_encoder_mst *mst_enc, |
enum radeon_hpd_id hpd, bool enable) |
{ |
struct drm_device *dev = primary->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
uint32_t reg; |
int retries = 0; |
uint32_t temp; |
reg = RREG32(NI_DIG_BE_CNTL + primary->offset); |
/* set MST mode */ |
reg &= ~NI_DIG_FE_DIG_MODE(7); |
reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); |
if (enable) |
reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
else |
reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
reg |= NI_DIG_HPD_SELECT(hpd); |
DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); |
WREG32(NI_DIG_BE_CNTL + primary->offset, reg); |
if (enable) { |
uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
do { |
temp = RREG32(NI_DIG_FE_CNTL + offset); |
} while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); |
if (retries == 10000) |
DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); |
} |
return 0; |
} |
static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, |
int stream_number, |
int fe, |
int slots) |
{ |
struct drm_device *dev = primary->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
u32 temp, val; |
int retries = 0; |
int satreg, satidx; |
satreg = stream_number >> 1; |
satidx = stream_number & 1; |
temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); |
val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe); |
val <<= (16 * satidx); |
temp &= ~(0xffff << (16 * satidx)); |
temp |= val; |
DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp); |
WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); |
WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); |
do { |
temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); |
} while ((temp & 0x1) && retries++ < 10000); |
if (retries == 10000) |
DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); |
/* MTP 16 ? */ |
return 0; |
} |
static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn, |
struct radeon_encoder *primary) |
{ |
struct drm_device *dev = mst_conn->base.dev; |
struct stream_attribs new_attribs[6]; |
int i; |
int idx = 0; |
struct radeon_connector *radeon_connector; |
struct drm_connector *connector; |
memset(new_attribs, 0, sizeof(new_attribs)); |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
struct radeon_encoder *subenc; |
struct radeon_encoder_mst *mst_enc; |
radeon_connector = to_radeon_connector(connector); |
if (!radeon_connector->is_mst_connector) |
continue; |
if (radeon_connector->mst_port != mst_conn) |
continue; |
subenc = radeon_connector->mst_encoder; |
mst_enc = subenc->enc_priv; |
if (!mst_enc->enc_active) |
continue; |
new_attribs[idx].fe = mst_enc->fe; |
new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); |
idx++; |
} |
for (i = 0; i < idx; i++) { |
if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || |
new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { |
radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); |
mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; |
mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; |
} |
} |
for (i = idx; i < mst_conn->enabled_attribs; i++) { |
radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); |
mst_conn->cur_stream_attribs[i].fe = 0; |
mst_conn->cur_stream_attribs[i].slots = 0; |
} |
mst_conn->enabled_attribs = idx; |
return 0; |
} |
static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y) |
{ |
struct drm_device *dev = mst->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder_mst *mst_enc = mst->enc_priv; |
uint32_t val, temp; |
uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
int retries = 0; |
val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y); |
WREG32(NI_DP_MSE_RATE_CNTL + offset, val); |
do { |
temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); |
} while ((temp & 0x1) && (retries++ < 10000)); |
if (retries >= 10000) |
DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); |
return 0; |
} |
static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector) |
{ |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
struct radeon_connector *master = radeon_connector->mst_port; |
struct edid *edid; |
int ret = 0; |
edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port); |
radeon_connector->edid = edid; |
DRM_DEBUG_KMS("edid retrieved %p\n", edid); |
if (radeon_connector->edid) { |
drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); |
return ret; |
} |
drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
return ret; |
} |
static int radeon_dp_mst_get_modes(struct drm_connector *connector) |
{ |
return radeon_dp_mst_get_ddc_modes(connector); |
} |
static enum drm_mode_status |
radeon_dp_mst_mode_valid(struct drm_connector *connector, |
struct drm_display_mode *mode) |
{ |
/* TODO - validate mode against available PBN for link */ |
if (mode->clock < 10000) |
return MODE_CLOCK_LOW; |
if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
return MODE_H_ILLEGAL; |
return MODE_OK; |
} |
struct drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector) |
{ |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
return &radeon_connector->mst_encoder->base; |
} |
static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = { |
.get_modes = radeon_dp_mst_get_modes, |
.mode_valid = radeon_dp_mst_mode_valid, |
.best_encoder = radeon_mst_best_encoder, |
}; |
static enum drm_connector_status |
radeon_dp_mst_detect(struct drm_connector *connector, bool force) |
{ |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
struct radeon_connector *master = radeon_connector->mst_port; |
return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port); |
} |
static void |
radeon_dp_mst_connector_destroy(struct drm_connector *connector) |
{ |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; |
drm_encoder_cleanup(&radeon_encoder->base); |
kfree(radeon_encoder); |
drm_connector_cleanup(connector); |
kfree(radeon_connector); |
} |
static int radeon_connector_dpms(struct drm_connector *connector, int mode) |
{ |
DRM_DEBUG_KMS("\n"); |
return 0; |
} |
static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = { |
.dpms = radeon_connector_dpms, |
.detect = radeon_dp_mst_detect, |
.fill_modes = drm_helper_probe_single_connector_modes, |
.destroy = radeon_dp_mst_connector_destroy, |
}; |
static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, |
struct drm_dp_mst_port *port, |
const char *pathprop) |
{ |
struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
struct drm_device *dev = master->base.dev; |
struct radeon_connector *radeon_connector; |
struct drm_connector *connector; |
radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL); |
if (!radeon_connector) |
return NULL; |
radeon_connector->is_mst_connector = true; |
connector = &radeon_connector->base; |
radeon_connector->port = port; |
radeon_connector->mst_port = master; |
DRM_DEBUG_KMS("\n"); |
drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); |
drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); |
radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); |
drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); |
drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
drm_mode_connector_set_path_property(connector, pathprop); |
return connector; |
} |
static void radeon_dp_register_mst_connector(struct drm_connector *connector) |
{ |
struct drm_device *dev = connector->dev; |
struct radeon_device *rdev = dev->dev_private; |
drm_modeset_lock_all(dev); |
radeon_fb_add_connector(rdev, connector); |
drm_modeset_unlock_all(dev); |
drm_connector_register(connector); |
} |
static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, |
struct drm_connector *connector) |
{ |
struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
struct drm_device *dev = master->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
drm_connector_unregister(connector); |
/* need to nuke the connector */ |
drm_modeset_lock_all(dev); |
/* dpms off */ |
radeon_fb_remove_connector(rdev, connector); |
drm_connector_cleanup(connector); |
drm_modeset_unlock_all(dev); |
kfree(connector); |
DRM_DEBUG_KMS("\n"); |
} |
static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) |
{ |
struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
struct drm_device *dev = master->base.dev; |
drm_kms_helper_hotplug_event(dev); |
} |
struct drm_dp_mst_topology_cbs mst_cbs = { |
.add_connector = radeon_dp_add_mst_connector, |
.register_connector = radeon_dp_register_mst_connector, |
.destroy_connector = radeon_dp_destroy_mst_connector, |
.hotplug = radeon_dp_mst_hotplug, |
}; |
struct radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder) |
{ |
struct drm_device *dev = encoder->dev; |
struct drm_connector *connector; |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
if (!connector->encoder) |
continue; |
if (!radeon_connector->is_mst_connector) |
continue; |
DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder); |
if (connector->encoder == encoder) |
return radeon_connector; |
} |
return NULL; |
} |
void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
{ |
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
struct drm_device *dev = crtc->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); |
struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); |
int dp_clock; |
struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
if (radeon_connector) { |
radeon_connector->pixelclock_for_modeset = mode->clock; |
if (radeon_connector->base.display_info.bpc) |
radeon_crtc->bpc = radeon_connector->base.display_info.bpc; |
else |
radeon_crtc->bpc = 8; |
} |
DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock); |
dp_clock = dig_connector->dp_clock; |
radeon_crtc->ss_enabled = |
radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
ASIC_INTERNAL_SS_ON_DP, |
dp_clock); |
} |
static void |
radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) |
{ |
struct drm_device *dev = encoder->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder, *primary; |
struct radeon_encoder_mst *mst_enc; |
struct radeon_encoder_atom_dig *dig_enc; |
struct radeon_connector *radeon_connector; |
struct drm_crtc *crtc; |
struct radeon_crtc *radeon_crtc; |
int ret, slots; |
if (!ASIC_IS_DCE5(rdev)) { |
DRM_ERROR("got mst dpms on non-DCE5\n"); |
return; |
} |
radeon_connector = radeon_mst_find_connector(encoder); |
if (!radeon_connector) |
return; |
radeon_encoder = to_radeon_encoder(encoder); |
mst_enc = radeon_encoder->enc_priv; |
primary = mst_enc->primary; |
dig_enc = primary->enc_priv; |
crtc = encoder->crtc; |
DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); |
switch (mode) { |
case DRM_MODE_DPMS_ON: |
dig_enc->active_mst_links++; |
radeon_crtc = to_radeon_crtc(crtc); |
if (dig_enc->active_mst_links == 1) { |
mst_enc->fe = dig_enc->dig_encoder; |
mst_enc->fe_from_be = true; |
atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); |
atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, |
0, 0, dig_enc->dig_encoder); |
if (radeon_dp_needs_link_train(mst_enc->connector) || |
dig_enc->active_mst_links == 1) { |
radeon_dp_link_train(&primary->base, &mst_enc->connector->base); |
} |
} else { |
mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); |
if (mst_enc->fe == -1) |
DRM_ERROR("failed to get frontend for dig encoder\n"); |
mst_enc->fe_from_be = false; |
atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
} |
DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder, |
dig_enc->linkb, radeon_crtc->crtc_id); |
ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr, |
radeon_connector->port, |
mst_enc->pbn, &slots); |
ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
radeon_dp_mst_set_be_cntl(primary, mst_enc, |
radeon_connector->mst_port->hpd.hpd, true); |
mst_enc->enc_active = true; |
radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0); |
atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, |
mst_enc->fe); |
ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); |
ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); |
break; |
case DRM_MODE_DPMS_STANDBY: |
case DRM_MODE_DPMS_SUSPEND: |
case DRM_MODE_DPMS_OFF: |
DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); |
if (!mst_enc->enc_active) |
return; |
drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port); |
ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); |
/* and this can also fail */ |
drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); |
drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port); |
mst_enc->enc_active = false; |
radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
radeon_dp_mst_set_be_cntl(primary, mst_enc, |
radeon_connector->mst_port->hpd.hpd, false); |
atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, |
mst_enc->fe); |
if (!mst_enc->fe_from_be) |
radeon_atom_release_dig_encoder(rdev, mst_enc->fe); |
mst_enc->fe_from_be = false; |
dig_enc->active_mst_links--; |
if (dig_enc->active_mst_links == 0) { |
/* drop link */ |
} |
break; |
} |
} |
static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, |
const struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode) |
{ |
struct radeon_encoder_mst *mst_enc; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
int bpp = 24; |
mst_enc = radeon_encoder->enc_priv; |
mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); |
mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; |
DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
mst_enc->primary->active_device, mst_enc->primary->devices, |
mst_enc->connector->devices, mst_enc->primary->base.encoder_type); |
drm_mode_set_crtcinfo(adjusted_mode, 0); |
{ |
struct radeon_connector_atom_dig *dig_connector; |
dig_connector = mst_enc->connector->con_priv; |
dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); |
dig_connector->dp_clock = radeon_dp_get_max_link_rate(&mst_enc->connector->base, |
dig_connector->dpcd); |
DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, |
dig_connector->dp_lane_count, dig_connector->dp_clock); |
} |
return true; |
} |
static void radeon_mst_encoder_prepare(struct drm_encoder *encoder) |
{ |
struct radeon_connector *radeon_connector; |
struct radeon_encoder *radeon_encoder, *primary; |
struct radeon_encoder_mst *mst_enc; |
struct radeon_encoder_atom_dig *dig_enc; |
radeon_connector = radeon_mst_find_connector(encoder); |
if (!radeon_connector) { |
DRM_DEBUG_KMS("failed to find connector %p\n", encoder); |
return; |
} |
radeon_encoder = to_radeon_encoder(encoder); |
radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
mst_enc = radeon_encoder->enc_priv; |
primary = mst_enc->primary; |
dig_enc = primary->enc_priv; |
mst_enc->port = radeon_connector->port; |
if (dig_enc->dig_encoder == -1) { |
dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); |
primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); |
atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); |
} |
DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); |
} |
static void |
radeon_mst_encoder_mode_set(struct drm_encoder *encoder, |
struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode) |
{ |
DRM_DEBUG_KMS("\n"); |
} |
static void radeon_mst_encoder_commit(struct drm_encoder *encoder) |
{ |
radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
DRM_DEBUG_KMS("\n"); |
} |
static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = { |
.dpms = radeon_mst_encoder_dpms, |
.mode_fixup = radeon_mst_mode_fixup, |
.prepare = radeon_mst_encoder_prepare, |
.mode_set = radeon_mst_encoder_mode_set, |
.commit = radeon_mst_encoder_commit, |
}; |
void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder) |
{ |
drm_encoder_cleanup(encoder); |
kfree(encoder); |
} |
static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = { |
.destroy = radeon_dp_mst_encoder_destroy, |
}; |
static struct radeon_encoder * |
radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) |
{ |
struct drm_device *dev = connector->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder; |
struct radeon_encoder_mst *mst_enc; |
struct drm_encoder *encoder; |
const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; |
struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); |
DRM_DEBUG_KMS("enc master is %p\n", enc_master); |
radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); |
if (!radeon_encoder) |
return NULL; |
radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL); |
if (!radeon_encoder->enc_priv) { |
kfree(radeon_encoder); |
return NULL; |
} |
encoder = &radeon_encoder->base; |
switch (rdev->num_crtc) { |
case 1: |
encoder->possible_crtcs = 0x1; |
break; |
case 2: |
default: |
encoder->possible_crtcs = 0x3; |
break; |
case 4: |
encoder->possible_crtcs = 0xf; |
break; |
case 6: |
encoder->possible_crtcs = 0x3f; |
break; |
} |
drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs, |
DRM_MODE_ENCODER_DPMST); |
drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); |
mst_enc = radeon_encoder->enc_priv; |
mst_enc->connector = connector; |
mst_enc->primary = to_radeon_encoder(enc_master); |
radeon_encoder->is_mst_encoder = true; |
return radeon_encoder; |
} |
int |
radeon_dp_mst_init(struct radeon_connector *radeon_connector) |
{ |
struct drm_device *dev = radeon_connector->base.dev; |
if (!radeon_connector->ddc_bus->has_aux) |
return 0; |
radeon_connector->mst_mgr.cbs = &mst_cbs; |
return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev, |
&radeon_connector->ddc_bus->aux, 16, 6, |
radeon_connector->base.base.id); |
} |
int |
radeon_dp_mst_probe(struct radeon_connector *radeon_connector) |
{ |
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
struct drm_device *dev = radeon_connector->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
int ret; |
u8 msg[1]; |
if (!radeon_mst) |
return 0; |
if (!ASIC_IS_DCE5(rdev)) |
return 0; |
if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) |
return 0; |
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg, |
1); |
if (ret) { |
if (msg[0] & DP_MST_CAP) { |
DRM_DEBUG_KMS("Sink is MST capable\n"); |
dig_connector->is_mst = true; |
} else { |
DRM_DEBUG_KMS("Sink is not MST capable\n"); |
dig_connector->is_mst = false; |
} |
} |
drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
dig_connector->is_mst); |
return dig_connector->is_mst; |
} |
int |
radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) |
{ |
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
int retry; |
if (dig_connector->is_mst) { |
u8 esi[16] = { 0 }; |
int dret; |
int ret = 0; |
bool handled; |
dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, |
DP_SINK_COUNT_ESI, esi, 8); |
go_again: |
if (dret == 8) { |
DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); |
if (handled) { |
for (retry = 0; retry < 3; retry++) { |
int wret; |
wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, |
DP_SINK_COUNT_ESI + 1, &esi[1], 3); |
if (wret == 3) |
break; |
} |
dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, |
DP_SINK_COUNT_ESI, esi, 8); |
if (dret == 8) { |
DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
goto go_again; |
} |
} else |
ret = 0; |
return ret; |
} else { |
DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); |
dig_connector->is_mst = false; |
drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
dig_connector->is_mst); |
/* send a hotplug event */ |
} |
} |
return -EINVAL; |
} |
#if defined(CONFIG_DEBUG_FS) |
static int radeon_debugfs_mst_info(struct seq_file *m, void *data) |
{ |
struct drm_info_node *node = (struct drm_info_node *)m->private; |
struct drm_device *dev = node->minor->dev; |
struct drm_connector *connector; |
struct radeon_connector *radeon_connector; |
struct radeon_connector_atom_dig *dig_connector; |
int i; |
drm_modeset_lock_all(dev); |
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
continue; |
radeon_connector = to_radeon_connector(connector); |
dig_connector = radeon_connector->con_priv; |
if (radeon_connector->is_mst_connector) |
continue; |
if (!dig_connector->is_mst) |
continue; |
drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); |
for (i = 0; i < radeon_connector->enabled_attribs; i++) |
seq_printf(m, "attrib %d: %d %d\n", i, |
radeon_connector->cur_stream_attribs[i].fe, |
radeon_connector->cur_stream_attribs[i].slots); |
} |
drm_modeset_unlock_all(dev); |
return 0; |
} |
static struct drm_info_list radeon_debugfs_mst_list[] = { |
{"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL}, |
}; |
#endif |
int radeon_mst_debugfs_init(struct radeon_device *rdev) |
{ |
#if defined(CONFIG_DEBUG_FS) |
return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1); |
#endif |
return 0; |
} |
/drivers/video/drm/radeon/radeon_kms.c |
---|
0,0 → 1,205 |
/* |
* Copyright 2008 Advanced Micro Devices, Inc. |
* Copyright 2008 Red Hat Inc. |
* Copyright 2009 Jerome Glisse. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
* Authors: Dave Airlie |
* Alex Deucher |
* Jerome Glisse |
*/ |
#include <drm/drmP.h> |
#include "radeon.h" |
#include <drm/radeon_drm.h> |
#include "radeon_asic.h" |
#include <linux/slab.h> |
#include <linux/pm_runtime.h> |
#include "radeon_kfd.h" |
#if defined(CONFIG_VGA_SWITCHEROO) |
bool radeon_has_atpx(void); |
#else |
static inline bool radeon_has_atpx(void) { return false; } |
#endif |
/* |
* VBlank related functions. |
*/ |
/** |
* radeon_get_vblank_counter_kms - get frame count |
* |
* @dev: drm dev pointer |
* @crtc: crtc to get the frame count from |
* |
* Gets the frame count on the requested crtc (all asics). |
* Returns frame count on success, -EINVAL on failure. |
*/ |
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) |
{ |
int vpos, hpos, stat; |
u32 count; |
struct radeon_device *rdev = dev->dev_private; |
if (crtc < 0 || crtc >= rdev->num_crtc) { |
DRM_ERROR("Invalid crtc %d\n", crtc); |
return -EINVAL; |
} |
/* The hw increments its frame counter at start of vsync, not at start |
* of vblank, as is required by DRM core vblank counter handling. |
* Cook the hw count here to make it appear to the caller as if it |
* incremented at start of vblank. We measure distance to start of |
* vblank in vpos. vpos therefore will be >= 0 between start of vblank |
* and start of vsync, so vpos >= 0 means to bump the hw frame counter |
* result by 1 to give the proper appearance to caller. |
*/ |
if (rdev->mode_info.crtcs[crtc]) { |
/* Repeat readout if needed to provide stable result if |
* we cross start of vsync during the queries. |
*/ |
do { |
count = radeon_get_vblank_counter(rdev, crtc); |
/* Ask radeon_get_crtc_scanoutpos to return vpos as |
* distance to start of vblank, instead of regular |
* vertical scanout pos. |
*/ |
stat = radeon_get_crtc_scanoutpos( |
dev, crtc, GET_DISTANCE_TO_VBLANKSTART, |
&vpos, &hpos, NULL, NULL, |
&rdev->mode_info.crtcs[crtc]->base.hwmode); |
} while (count != radeon_get_vblank_counter(rdev, crtc)); |
if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != |
(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { |
DRM_DEBUG_VBL("Query failed! stat %d\n", stat); |
} |
else { |
DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", |
crtc, vpos); |
/* Bump counter if we are at >= leading edge of vblank, |
* but before vsync where vpos would turn negative and |
* the hw counter really increments. |
*/ |
if (vpos >= 0) |
count++; |
} |
} |
else { |
/* Fallback to use value as is. */ |
count = radeon_get_vblank_counter(rdev, crtc); |
DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); |
} |
return count; |
} |
/** |
* radeon_enable_vblank_kms - enable vblank interrupt |
* |
* @dev: drm dev pointer |
* @crtc: crtc to enable vblank interrupt for |
* |
* Enable the interrupt on the requested crtc (all asics). |
* Returns 0 on success, -EINVAL on failure. |
*/ |
int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) |
{ |
struct radeon_device *rdev = dev->dev_private; |
unsigned long irqflags; |
int r; |
if (crtc < 0 || crtc >= rdev->num_crtc) { |
DRM_ERROR("Invalid crtc %d\n", crtc); |
return -EINVAL; |
} |
spin_lock_irqsave(&rdev->irq.lock, irqflags); |
rdev->irq.crtc_vblank_int[crtc] = true; |
r = radeon_irq_set(rdev); |
spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
return r; |
} |
/** |
* radeon_disable_vblank_kms - disable vblank interrupt |
* |
* @dev: drm dev pointer |
* @crtc: crtc to disable vblank interrupt for |
* |
* Disable the interrupt on the requested crtc (all asics). |
*/ |
void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) |
{ |
struct radeon_device *rdev = dev->dev_private; |
unsigned long irqflags; |
if (crtc < 0 || crtc >= rdev->num_crtc) { |
DRM_ERROR("Invalid crtc %d\n", crtc); |
return; |
} |
spin_lock_irqsave(&rdev->irq.lock, irqflags); |
rdev->irq.crtc_vblank_int[crtc] = false; |
radeon_irq_set(rdev); |
spin_unlock_irqrestore(&rdev->irq.lock, irqflags); |
} |
/** |
* radeon_get_vblank_timestamp_kms - get vblank timestamp |
* |
* @dev: drm dev pointer |
* @crtc: crtc to get the timestamp for |
* @max_error: max error |
* @vblank_time: time value |
* @flags: flags passed to the driver |
* |
* Gets the timestamp on the requested crtc based on the |
* scanout position. (all asics). |
* Returns postive status flags on success, negative error on failure. |
*/ |
int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, |
int *max_error, |
struct timeval *vblank_time, |
unsigned flags) |
{ |
struct drm_crtc *drmcrtc; |
struct radeon_device *rdev = dev->dev_private; |
if (crtc < 0 || crtc >= dev->num_crtcs) { |
DRM_ERROR("Invalid crtc %d\n", crtc); |
return -EINVAL; |
} |
/* Get associated drm_crtc: */ |
drmcrtc = &rdev->mode_info.crtcs[crtc]->base; |
if (!drmcrtc) |
return -EINVAL; |
/* Helper routine in DRM core does all the work: */ |
return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, |
vblank_time, flags, |
&drmcrtc->hwmode); |
} |