Subversion Repositories Kolibri OS

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Regard whitespace Rev 1412 → Rev 1413

/drivers/video/drm/radeon/firmware/R100_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/R200_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/R300_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/R420_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/R520_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/R600_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/R600_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/R600_rlc.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/R700_rlc.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RS600_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/RS690_cp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/drivers/video/drm/radeon/firmware/RS780_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RS780_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV610_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV610_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV620_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV620_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV630_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV630_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV635_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV635_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV670_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV670_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV710_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV710_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV730_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV730_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV770_me.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/firmware/RV770_pfp.bin
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Property changes:
Added: svn:mime-type
+application/octet-stream
\ No newline at end of property
/drivers/video/drm/radeon/fwblob.asm
16,71 → 16,291
 
___start_builtin_fw:
 
dd FIRMWARE_R100
dd FIRMWARE_R100_CP
dd R100CP_START
dd (R100CP_END - R100CP_START)
 
dd FIRMWARE_R200
dd FIRMWARE_R200_CP
dd R200CP_START
dd (R200CP_END - R200CP_START)
 
dd FIRMWARE_R300
dd FIRMWARE_R300_CP
dd R300CP_START
dd (R300CP_END - R300CP_START)
 
dd FIRMWARE_R420
dd FIRMWARE_R420_CP
dd R420CP_START
dd (R420CP_END - R420CP_START)
 
dd FIRMWARE_RS690
dd RS690CP_START
dd (RS690CP_END - RS690CP_START)
dd FIRMWARE_R520_CP
dd R520CP_START
dd (R520CP_END - R520CP_START)
 
dd FIRMWARE_RS600
dd FIRMWARE_RS600_CP
dd RS600CP_START
dd (RS600CP_END - RS600CP_START)
 
dd FIRMWARE_R520
dd R520CP_START
dd (R520CP_END - R520CP_START)
dd FIRMWARE_RS690_CP
dd RS690CP_START
dd (RS690CP_END - RS690CP_START)
 
dd FIRMWARE_RS780_ME
dd RS780ME_START
dd (RS780ME_END - RS780ME_START)
 
dd FIRMWARE_RS780_PFP
dd RS780PFP_START
dd (RS780PFP_END - RS780PFP_START)
 
dd FIRMWARE_RV610_ME
dd RV610ME_START
dd (RV610ME_END - RV610ME_START)
 
dd FIRMWARE_RV620_ME
dd RV620ME_START
dd (RV620ME_END - RV620ME_START)
 
dd FIRMWARE_RV630_ME
dd RV630ME_START
dd (RV630ME_END - RV630ME_START)
 
dd FIRMWARE_RV635_ME
dd RV635ME_START
dd (RV635ME_END - RV635ME_START)
 
dd FIRMWARE_RV670_ME
dd RV670ME_START
dd (RV670ME_END - RV670ME_START)
 
dd FIRMWARE_RV710_ME
dd RV710ME_START
dd (RV710ME_END - RV710ME_START)
 
dd FIRMWARE_RV730_ME
dd RV730ME_START
dd (RV730ME_END - RV730ME_START)
 
dd FIRMWARE_RV770_ME
dd RV770ME_START
dd (RV770ME_END - RV770ME_START)
 
 
dd FIRMWARE_RV610_PFP
dd RV610PFP_START
dd (RV610PFP_END - RV610PFP_START)
 
dd FIRMWARE_RV620_PFP
dd RV620PFP_START
dd (RV620PFP_END - RV620PFP_START)
 
dd FIRMWARE_RV630_PFP
dd RV630PFP_START
dd (RV630PFP_END - RV630PFP_START)
 
dd FIRMWARE_RV635_PFP
dd RV635PFP_START
dd (RV635PFP_END - RV635PFP_START)
 
dd FIRMWARE_RV670_PFP
dd RV670PFP_START
dd (RV670PFP_END - RV670PFP_START)
 
 
dd FIRMWARE_RV710_PFP
dd RV670PFP_START
dd (RV710PFP_END - RV710PFP_START)
 
dd FIRMWARE_RV730_PFP
dd RV730PFP_START
dd (RV730PFP_END - RV730PFP_START)
 
dd FIRMWARE_RV770_PFP
dd RV770PFP_START
dd (RV770PFP_END - RV770PFP_START)
 
dd FIRMWARE_R600_RLC
dd R600RLC_START
dd (R600RLC_END - R600RLC_START)
 
dd FIRMWARE_R700_RLC
dd R700RLC_START
dd (R700RLC_END - R700RLC_START)
 
 
___end_builtin_fw:
 
 
FIRMWARE_R100 db 'radeon/R100_cp.bin',0
FIRMWARE_R200 db 'radeon/R200_cp.bin',0
FIRMWARE_R300 db 'radeon/R300_cp.bin',0
FIRMWARE_R420 db 'radeon/R420_cp.bin',0
FIRMWARE_RS690 db 'radeon/RS690_cp.bin',0
FIRMWARE_RS600 db 'radeon/RS600_cp.bin',0
FIRMWARE_R520 db 'radeon/R520_cp.bin', 0
FIRMWARE_R100_CP db 'radeon/R100_cp.bin',0
FIRMWARE_R200_CP db 'radeon/R200_cp.bin',0
FIRMWARE_R300_CP db 'radeon/R300_cp.bin',0
FIRMWARE_R420_CP db 'radeon/R420_cp.bin',0
FIRMWARE_R520_CP db 'radeon/R520_cp.bin',0
 
FIRMWARE_RS600_CP db 'radeon/RS600_cp.bin',0
FIRMWARE_RS690_CP db 'radeon/RS690_cp.bin',0
 
FIRMWARE_RS780_ME db 'radeon/RS780_me.bin',0
FIRMWARE_RS780_PFP db 'radeon/RS780_pfp.bin',0
 
FIRMWARE_RV610_ME db 'radeon/RV610_me.bin',0
FIRMWARE_RV620_ME db 'radeon/RV620_me.bin',0
FIRMWARE_RV630_ME db 'radeon/RV630_me.bin',0
FIRMWARE_RV635_ME db 'radeon/RV635_me.bin',0
FIRMWARE_RV670_ME db 'radeon/RV670_me.bin',0
FIRMWARE_RV710_ME db 'radeon/RV710_me.bin',0
FIRMWARE_RV730_ME db 'radeon/RV730_me.bin',0
FIRMWARE_RV770_ME db 'radeon/RV770_me.bin',0
 
FIRMWARE_RV610_PFP db 'radeon/RV610_pfp.bin',0
FIRMWARE_RV620_PFP db 'radeon/RV620_pfp.bin',0
FIRMWARE_RV630_PFP db 'radeon/RV630_pfp.bin',0
FIRMWARE_RV635_PFP db 'radeon/RV635_pfp.bin',0
FIRMWARE_RV670_PFP db 'radeon/RV670_pfp.bin',0
FIRMWARE_RV710_PFP db 'radeon/RV710_pfp.bin',0
FIRMWARE_RV730_PFP db 'radeon/RV730_pfp.bin',0
FIRMWARE_RV770_PFP db 'radeon/RV770_pfp.bin',0
 
FIRMWARE_R600_RLC db 'radeon/R600_rlc.bin',0
FIRMWARE_R700_RLC db 'radeon/R700_rlc.bin',0
 
 
align 16
 
R100CP_START:
file 'firmware/r100_cp.bin'
R100CP_END:
 
align 16
R200CP_START:
file 'firmware/r200_cp.bin'
R200CP_END:
 
align 16
R300CP_START:
file 'firmware/r300_cp.bin'
R300CP_END:
 
align 16
R420CP_START:
file 'firmware/r420_cp.bin'
R420CP_END:
 
RS690CP_START:
file 'firmware/rs690_cp.bin'
RS690CP_END:
align 16
R520CP_START:
file 'firmware/r520_cp.bin'
R520CP_END:
 
align 16
RS600CP_START:
file 'firmware/rs600_cp.bin'
RS600CP_END:
 
align 16
R520CP_START:
file 'firmware/r520_cp.bin'
R520CP_END:
RS690CP_START:
file 'firmware/rs690_cp.bin'
RS690CP_END:
 
align 16
RS780ME_START:
file 'firmware/rs780_me.bin'
RS780ME_END:
 
align 16
RS780PFP_START:
file 'firmware/rs780_pfp.bin'
RS780PFP_END:
 
align 16
RV610ME_START:
file 'firmware/rv610_me.bin'
RV610ME_END:
 
align 16
RV620ME_START:
file 'firmware/rv620_me.bin'
RV620ME_END:
 
align 16
RV630ME_START:
file 'firmware/rv630_me.bin'
RV630ME_END:
 
align 16
RV635ME_START:
file 'firmware/rv635_me.bin'
RV635ME_END:
 
align 16
RV670ME_START:
file 'firmware/rv670_me.bin'
RV670ME_END:
 
 
align 16
RV710ME_START:
file 'firmware/rv710_me.bin'
RV710ME_END:
 
align 16
RV730ME_START:
file 'firmware/rv730_me.bin'
RV730ME_END:
 
align 16
RV770ME_START:
file 'firmware/rv770_me.bin'
RV770ME_END:
 
 
align 16
RV610PFP_START:
file 'firmware/rv610_pfp.bin'
RV610PFP_END:
 
 
align 16
RV620PFP_START:
file 'firmware/rv620_pfp.bin'
RV620PFP_END:
 
align 16
RV630PFP_START:
file 'firmware/rv630_pfp.bin'
RV630PFP_END:
 
 
align 16
RV635PFP_START:
file 'firmware/rv635_pfp.bin'
RV635PFP_END:
 
align 16
RV670PFP_START:
file 'firmware/rv670_pfp.bin'
RV670PFP_END:
 
align 16
RV710PFP_START:
file 'firmware/rv710_pfp.bin'
RV710PFP_END:
 
align 16
RV730PFP_START:
file 'firmware/rv730_pfp.bin'
RV730PFP_END:
 
 
align 16
RV770PFP_START:
file 'firmware/rv770_pfp.bin'
RV770PFP_END:
 
 
align 16
R600RLC_START:
file 'firmware/r600_rlc.bin'
R600RLC_END:
 
align 16
R700RLC_START:
file 'firmware/r700_rlc.bin'
R700RLC_END:
/drivers/video/drm/radeon/makefile
89,14 → 89,38
cursor.S \
fwblob.asm
 
FW_SRCS= \
firmware/R100_cp.bin.ihex \
firmware/R200_cp.bin.ihex \
firmware/R300_cp.bin.ihex \
firmware/R420_cp.bin.ihex \
firmware/RS690_cp.bin.ihex \
firmware/RS600_cp.bin.ihex \
firmware/R520_cp.bin.ihex \
FW_BINS= \
firmware/R100_cp.bin \
firmware/R200_cp.bin \
firmware/R300_cp.bin \
firmware/R420_cp.bin \
firmware/R520_cp.bin \
\
firmware/RS690_cp.bin \
firmware/RS600_cp.bin \
firmware/RS780_me.bin \
firmware/RS780_pfp.bin \
\
firmware/RV610_me.bin \
firmware/RV620_me.bin \
firmware/RV630_me.bin \
firmware/RV635_me.bin \
firmware/RV670_me.bin \
firmware/RV710_me.bin \
firmware/RV730_me.bin \
firmware/RV770_me.bin \
\
firmware/RV610_pfp.bin \
firmware/RV620_pfp.bin \
firmware/RV630_pfp.bin \
firmware/RV635_pfp.bin \
firmware/RV670_pfp.bin \
firmware/RV710_pfp.bin \
firmware/RV730_pfp.bin \
firmware/RV770_pfp.bin \
\
firmware/R600_rlc.bin \
firmware/R700_rlc.bin
 
 
SRC_DEP:=
106,13 → 130,10
$(patsubst %.c, %.o, $(NAME_SRC))))
 
 
FW_BINS = $(patsubst %.bin.ihex, %.bin, $(FW_SRCS))
 
 
 
all: $(NAME).dll
 
$(NAME).dll: $(NAME_OBJS) $(SRC_DEP) $(HFILES) atikms.lds Makefile
$(NAME).dll: $(NAME_OBJS) $(FW_BINS) $(SRC_DEP) $(HFILES) atikms.lds Makefile
ld -L$(LIBPATH) $(LDFLAGS) -T atikms.lds -o $@ $(NAME_OBJS) $(LIBS)
 
 
/drivers/video/drm/radeon/r420.c
355,7 → 355,6
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// r420_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
/drivers/video/drm/radeon/r520.c
188,6 → 188,7
}
/* Enable IRQ */
// rs600_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
/drivers/video/drm/radeon/r600.c
1391,6 → 1391,173
{
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
}
 
int r600_init_microcode(struct radeon_device *rdev)
{
struct platform_device *pdev;
const char *chip_name;
const char *rlc_chip_name;
size_t pfp_req_size, me_req_size, rlc_req_size;
char fw_name[30];
int err;
 
DRM_DEBUG("\n");
 
pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
err = IS_ERR(pdev);
if (err) {
printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
return -EINVAL;
}
 
switch (rdev->family) {
case CHIP_R600:
chip_name = "R600";
rlc_chip_name = "R600";
break;
case CHIP_RV610:
chip_name = "RV610";
rlc_chip_name = "R600";
break;
case CHIP_RV630:
chip_name = "RV630";
rlc_chip_name = "R600";
break;
case CHIP_RV620:
chip_name = "RV620";
rlc_chip_name = "R600";
break;
case CHIP_RV635:
chip_name = "RV635";
rlc_chip_name = "R600";
break;
case CHIP_RV670:
chip_name = "RV670";
rlc_chip_name = "R600";
break;
case CHIP_RS780:
case CHIP_RS880:
chip_name = "RS780";
rlc_chip_name = "R600";
break;
case CHIP_RV770:
chip_name = "RV770";
rlc_chip_name = "R700";
break;
case CHIP_RV730:
case CHIP_RV740:
chip_name = "RV730";
rlc_chip_name = "R700";
break;
case CHIP_RV710:
chip_name = "RV710";
rlc_chip_name = "R700";
break;
default: BUG();
}
 
if (rdev->family >= CHIP_RV770) {
pfp_req_size = R700_PFP_UCODE_SIZE * 4;
me_req_size = R700_PM4_UCODE_SIZE * 4;
rlc_req_size = R700_RLC_UCODE_SIZE * 4;
} else {
pfp_req_size = PFP_UCODE_SIZE * 4;
me_req_size = PM4_UCODE_SIZE * 12;
rlc_req_size = RLC_UCODE_SIZE * 4;
}
 
DRM_INFO("Loading %s Microcode\n", chip_name);
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
if (err)
goto out;
if (rdev->pfp_fw->size != pfp_req_size) {
printk(KERN_ERR
"r600_cp: Bogus length %zu in firmware \"%s\"\n",
rdev->pfp_fw->size, fw_name);
err = -EINVAL;
goto out;
}
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
if (err)
goto out;
if (rdev->me_fw->size != me_req_size) {
printk(KERN_ERR
"r600_cp: Bogus length %zu in firmware \"%s\"\n",
rdev->me_fw->size, fw_name);
err = -EINVAL;
}
 
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
if (err)
goto out;
if (rdev->rlc_fw->size != rlc_req_size) {
printk(KERN_ERR
"r600_rlc: Bogus length %zu in firmware \"%s\"\n",
rdev->rlc_fw->size, fw_name);
err = -EINVAL;
}
 
out:
platform_device_unregister(pdev);
 
if (err) {
if (err != -EINVAL)
printk(KERN_ERR
"r600_cp: Failed to load firmware \"%s\"\n",
fw_name);
release_firmware(rdev->pfp_fw);
rdev->pfp_fw = NULL;
release_firmware(rdev->me_fw);
rdev->me_fw = NULL;
release_firmware(rdev->rlc_fw);
rdev->rlc_fw = NULL;
}
return err;
}
 
static int r600_cp_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data;
int i;
 
if (!rdev->me_fw || !rdev->pfp_fw)
return -EINVAL;
 
r600_cp_stop(rdev);
 
WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
 
/* Reset cp */
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
RREG32(GRBM_SOFT_RESET);
mdelay(15);
WREG32(GRBM_SOFT_RESET, 0);
 
WREG32(CP_ME_RAM_WADDR, 0);
 
fw_data = (const __be32 *)rdev->me_fw->data;
WREG32(CP_ME_RAM_WADDR, 0);
for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
WREG32(CP_ME_RAM_DATA,
be32_to_cpup(fw_data++));
 
fw_data = (const __be32 *)rdev->pfp_fw->data;
WREG32(CP_PFP_UCODE_ADDR, 0);
for (i = 0; i < PFP_UCODE_SIZE; i++)
WREG32(CP_PFP_UCODE_DATA,
be32_to_cpup(fw_data++));
 
WREG32(CP_PFP_UCODE_ADDR, 0);
WREG32(CP_ME_RAM_WADDR, 0);
WREG32(CP_ME_RAM_RADDR, 0);
return 0;
}
 
int r600_cp_start(struct radeon_device *rdev)
{
int r;
1419,6 → 1586,56
WREG32(R_0086D8_CP_ME_CNTL, cp_me);
return 0;
}
 
int r600_cp_resume(struct radeon_device *rdev)
{
u32 tmp;
u32 rb_bufsz;
int r;
 
/* Reset cp */
WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
RREG32(GRBM_SOFT_RESET);
mdelay(15);
WREG32(GRBM_SOFT_RESET, 0);
 
/* Set ring buffer size */
rb_bufsz = drm_order(rdev->cp.ring_size / 8);
tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT;
#endif
WREG32(CP_RB_CNTL, tmp);
WREG32(CP_SEM_WAIT_TIMER, 0x4);
 
/* Set the write pointer delay */
WREG32(CP_RB_WPTR_DELAY, 0);
 
/* Initialize the ring buffer's read and write pointers */
WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
WREG32(CP_RB_RPTR_WR, 0);
WREG32(CP_RB_WPTR, 0);
WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
mdelay(1);
WREG32(CP_RB_CNTL, tmp);
 
WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
rdev->cp.rptr = RREG32(CP_RB_RPTR);
rdev->cp.wptr = RREG32(CP_RB_WPTR);
 
r600_cp_start(rdev);
rdev->cp.ready = true;
r = radeon_ring_test(rdev);
if (r) {
rdev->cp.ready = false;
return r;
}
return 0;
}
 
void r600_cp_commit(struct radeon_device *rdev)
{
WREG32(CP_RB_WPTR, rdev->cp.wptr);
1450,6 → 1667,60
rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
}
}
 
int r600_ring_test(struct radeon_device *rdev)
{
uint32_t scratch;
uint32_t tmp = 0;
unsigned i;
int r;
 
r = radeon_scratch_get(rdev, &scratch);
if (r) {
DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
return r;
}
WREG32(scratch, 0xCAFEDEAD);
r = radeon_ring_lock(rdev, 3);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
radeon_scratch_free(rdev, scratch);
return r;
}
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
radeon_ring_write(rdev, 0xDEADBEEF);
radeon_ring_unlock_commit(rdev);
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(scratch);
if (tmp == 0xDEADBEEF)
break;
DRM_UDELAY(1);
}
if (i < rdev->usec_timeout) {
DRM_INFO("ring test succeeded in %d usecs\n", i);
} else {
DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
scratch, tmp);
r = -EINVAL;
}
radeon_scratch_free(rdev, scratch);
return r;
}
void r600_fence_ring_emit(struct radeon_device *rdev,
struct radeon_fence *fence)
{
/* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
/* Emit fence sequence & fire IRQ */
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
radeon_ring_write(rdev, fence->seq);
radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
radeon_ring_write(rdev, 1);
/* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
radeon_ring_write(rdev, RB_INT_STAT);
}
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
uint32_t tiling_flags, uint32_t pitch,
uint32_t offset, uint32_t obj_size)
1485,6 → 1756,14
{
int r;
 
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
r = r600_init_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load firmware!\n");
return r;
}
}
 
r600_mc_program(rdev);
if (rdev->flags & RADEON_IS_AGP) {
r600_agp_enable(rdev);
1495,22 → 1774,15
}
r600_gpu_init(rdev);
 
// r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
// &rdev->r600_blit.shader_gpu_addr);
// if (r) {
// DRM_ERROR("failed to pin blit object %d\n", r);
// return r;
// }
 
// r = radeon_ring_init(rdev, rdev->cp.ring_size);
// if (r)
// return r;
// r = r600_cp_load_microcode(rdev);
// if (r)
// return r;
// r = r600_cp_resume(rdev);
// if (r)
// return r;
r = radeon_ring_init(rdev, rdev->cp.ring_size);
if (r)
return r;
r = r600_cp_load_microcode(rdev);
if (r)
return r;
r = r600_cp_resume(rdev);
if (r)
return r;
/* write back buffer are not vital so don't worry about failure */
// r600_wb_enable(rdev);
return 0;
1609,8 → 1881,8
// if (r)
// return r;
 
// rdev->cp.ring_obj = NULL;
// r600_ring_init(rdev, 1024 * 1024);
rdev->cp.ring_obj = NULL;
r600_ring_init(rdev, 1024 * 1024);
 
// rdev->ih.ring_obj = NULL;
// r600_ih_ring_init(rdev, 64 * 1024);
1619,12 → 1891,6
if (r)
return r;
 
// r = r600_blit_init(rdev);
// if (r) {
// DRM_ERROR("radeon: failled blitter (%d).\n", r);
// return r;
// }
 
rdev->accel_working = true;
r = r600_startup(rdev);
if (r) {
/drivers/video/drm/radeon/radeon.h
780,7 → 780,7
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 
struct radeon_device {
void *dev;
struct device *dev;
struct drm_device *ddev;
struct pci_dev *pdev;
/* ASIC */
/drivers/video/drm/radeon/radeon_asic.h
99,7 → 99,7
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
// .get_vblank_counter = &r100_get_vblank_counter,
// .fence_ring_emit = &r100_fence_ring_emit,
.fence_ring_emit = &r100_fence_ring_emit,
// .cs_parse = &r100_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = NULL,
159,7 → 159,7
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
// .get_vblank_counter = &r100_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
203,7 → 203,7
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
// .get_vblank_counter = &r100_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
252,7 → 252,7
// .irq_set = &r100_irq_set,
// .irq_process = &r100_irq_process,
// .get_vblank_counter = &r100_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
311,7 → 311,7
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
// .get_vblank_counter = &rs600_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
357,7 → 357,7
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
// .get_vblank_counter = &rs600_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
409,7 → 409,7
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
// .get_vblank_counter = &rs600_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
452,7 → 452,7
// .irq_set = &rs600_irq_set,
// .irq_process = &rs600_irq_process,
// .get_vblank_counter = &rs600_get_vblank_counter,
// .fence_ring_emit = &r300_fence_ring_emit,
.fence_ring_emit = &r300_fence_ring_emit,
// .cs_parse = &r300_cs_parse,
// .copy_blit = &r100_copy_blit,
// .copy_dma = &r300_copy_dma,
519,16 → 519,16
// .fini = &r600_fini,
// .suspend = &r600_suspend,
// .resume = &r600_resume,
// .cp_commit = &r600_cp_commit,
.cp_commit = &r600_cp_commit,
.vga_set_state = &r600_vga_set_state,
.gpu_reset = &r600_gpu_reset,
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page,
// .ring_test = &r600_ring_test,
.ring_test = &r600_ring_test,
// .ring_ib_execute = &r600_ring_ib_execute,
// .irq_set = &r600_irq_set,
// .irq_process = &r600_irq_process,
// .fence_ring_emit = &r600_fence_ring_emit,
.fence_ring_emit = &r600_fence_ring_emit,
// .cs_parse = &r600_cs_parse,
// .copy_blit = &r600_copy_blit,
// .copy_dma = &r600_copy_blit,
563,16 → 563,16
// .fini = &rv770_fini,
// .suspend = &rv770_suspend,
// .resume = &rv770_resume,
// .cp_commit = &r600_cp_commit,
.cp_commit = &r600_cp_commit,
.gpu_reset = &rv770_gpu_reset,
.vga_set_state = &r600_vga_set_state,
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page,
// .ring_test = &r600_ring_test,
.ring_test = &r600_ring_test,
// .ring_ib_execute = &r600_ring_ib_execute,
// .irq_set = &r600_irq_set,
// .irq_process = &r600_irq_process,
// .fence_ring_emit = &r600_fence_ring_emit,
.fence_ring_emit = &r600_fence_ring_emit,
// .cs_parse = &r600_cs_parse,
// .copy_blit = &r600_copy_blit,
// .copy_dma = &r600_copy_blit,
/drivers/video/drm/radeon/rs400.c
414,11 → 414,11
// r100_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
// r = r100_cp_init(rdev, 1024 * 1024);
// if (r) {
// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
// return r;
// }
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
return r;
}
// r = r100_wb_init(rdev);
// if (r)
// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
498,7 → 498,6
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// rs400_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
/drivers/video/drm/radeon/rs600.c
515,11 → 515,11
// rs600_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
// r = r100_cp_init(rdev, 1024 * 1024);
// if (r) {
// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
// return r;
// }
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
return r;
}
// r = r100_wb_init(rdev);
// if (r)
// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
598,7 → 598,6
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// rs600_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
/drivers/video/drm/radeon/rs690.c
625,15 → 625,14
if (r)
return r;
/* Enable IRQ */
// rdev->irq.sw_int = true;
// rs600_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
// r = r100_cp_init(rdev, 1024 * 1024);
// if (r) {
// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
// return r;
// }
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
return r;
}
// r = r100_wb_init(rdev);
// if (r)
// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
714,7 → 713,6
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// rs690_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
/drivers/video/drm/radeon/rv515.c
491,11 → 491,11
// rs600_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
// r = r100_cp_init(rdev, 1024 * 1024);
// if (r) {
// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
// return r;
// }
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
return r;
}
// r = r100_wb_init(rdev);
// if (r)
// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
578,13 → 578,11
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// rv515_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
rv370_pcie_gart_fini(rdev);
// radeon_agp_fini(rdev);
// radeon_irq_kms_fini(rdev);
rdev->accel_working = false;
}
return 0;
/drivers/video/drm/radeon/rv770.c
25,7 → 25,7
* Alex Deucher
* Jerome Glisse
*/
//#include <linux/firmware.h>
#include <linux/firmware.h>
//#include <linux/platform_device.h>
#include "drmP.h"
#include "radeon.h"
234,7 → 234,7
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
}
 
#if 0
 
static int rv770_cp_load_microcode(struct radeon_device *rdev)
{
const __be32 *fw_data;
269,7 → 269,6
return 0;
}
 
#endif
 
/*
* Core functions
871,6 → 870,14
{
int r;
 
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
r = r600_init_microcode(rdev);
if (r) {
DRM_ERROR("Failed to load firmware!\n");
return r;
}
}
 
rv770_mc_program(rdev);
if (rdev->flags & RADEON_IS_AGP) {
rv770_agp_enable(rdev);
880,24 → 887,15
return r;
}
rv770_gpu_init(rdev);
 
 
// r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
// &rdev->r600_blit.shader_gpu_addr);
// if (r) {
// DRM_ERROR("failed to pin blit object %d\n", r);
// return r;
// }
 
// r = radeon_ring_init(rdev, rdev->cp.ring_size);
// if (r)
// return r;
// r = rv770_cp_load_microcode(rdev);
// if (r)
// return r;
// r = r600_cp_resume(rdev);
// if (r)
// return r;
r = radeon_ring_init(rdev, rdev->cp.ring_size);
if (r)
return r;
r = rv770_cp_load_microcode(rdev);
if (r)
return r;
r = r600_cp_resume(rdev);
if (r)
return r;
/* write back buffer are not vital so don't worry about failure */
// r600_wb_enable(rdev);
return 0;
904,6 → 902,11
}
 
 
 
 
 
 
 
/* Plan is to move initialization in that function and use
* helper function so that radeon_device_init pretty much
* do nothing more than calling asic specific function. This
971,30 → 974,20
if (r)
return r;
 
// if (!rdev->me_fw || !rdev->pfp_fw) {
// r = r600_cp_init_microcode(rdev);
// if (r) {
// DRM_ERROR("Failed to load firmware!\n");
// return r;
// }
// }
 
rdev->cp.ring_obj = NULL;
r600_ring_init(rdev, 1024 * 1024);
 
 
r = r600_pcie_gart_init(rdev);
if (r)
return r;
 
rdev->accel_working = true;
// r = r600_blit_init(rdev);
// if (r) {
// DRM_ERROR("radeon: failled blitter (%d).\n", r);
// rdev->accel_working = false;
// }
 
r = rv770_startup(rdev);
if (r) {
// rv770_suspend(rdev);
// r600_wb_fini(rdev);
// radeon_ring_fini(rdev);
dev_err(rdev->dev, "disabling GPU acceleration\n");
 
rv770_pcie_gart_fini(rdev);
rdev->accel_working = false;
}