0,0 → 1,132 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
;; ;; |
;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;; |
;; Distributed under terms of the GNU General Public License ;; |
;; ;; |
;; GNU GENERAL PUBLIC LICENSE ;; |
;; Version 2, June 1991 ;; |
;; ;; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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; PCI Bus defines |
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PCI_HEADER_TYPE = 0x0e ; 8 bit |
PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit |
PCI_BASE_ADDRESS_1 = 0x14 ; 32 bits |
PCI_BASE_ADDRESS_2 = 0x18 ; 32 bits |
PCI_BASE_ADDRESS_3 = 0x1c ; 32 bits |
PCI_BASE_ADDRESS_4 = 0x20 ; 32 bits |
PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits |
PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0 |
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; PCI programming |
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PCI_VENDOR_ID = 0x00 ; 16 bit |
PCI_DEVICE_ID = 0x02 ; 16 bits |
PCI_REG_COMMAND = 0x4 ; command register |
PCI_REG_STATUS = 0x6 ; status register |
PCI_REVISION_ID = 0x08 ; 8 bits |
PCI_REG_LATENCY = 0xd ; latency timer register |
PCI_REG_CAP_PTR = 0x34 ; capabilities pointer |
PCI_REG_IRQ = 0x3c |
PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block |
PCI_REG_PM_STATUS = 0x4 ; power management status register |
PCI_REG_PM_CTRL = 0x4 ; power management control register |
PCI_BIT_PIO = 1 ; bit0: io space control |
PCI_BIT_MMIO = 2 ; bit1: memory space control |
PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master |
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macro PCI_find_io { |
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local .check, .inc, .got |
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xor eax, eax |
mov esi, PCI_BASE_ADDRESS_0 |
.check: |
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
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test eax, PCI_BASE_ADDRESS_IO_MASK |
jz .inc |
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test eax, PCI_BASE_ADDRESS_SPACE_IO |
jz .inc |
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and eax, PCI_BASE_ADDRESS_IO_MASK |
jmp .got |
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.inc: |
add esi, 4 |
cmp esi, PCI_BASE_ADDRESS_5 |
jbe .check |
xor eax, eax |
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.got: |
mov [device.io_addr], eax |
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} |
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macro PCI_find_mmio32 { |
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local .check, .inc, .got |
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mov esi, PCI_BASE_ADDRESS_0 |
.check: |
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi |
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test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address? |
jnz .inc |
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test eax, 100b ; 64 bit? |
jnz .inc |
and eax, not 1111b |
jmp .got |
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.inc: |
add esi, 4 |
cmp esi, PCI_BASE_ADDRESS_5 |
jbe .check |
xor eax, eax |
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.got: |
mov [device.mmio_addr], eax |
} |
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macro PCI_find_irq { |
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stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_IRQ |
mov [device.irq_line], al |
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} |
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macro PCI_find_rev { |
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stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REVISION_ID |
mov [device.revision], al |
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} |
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macro PCI_make_bus_master bus, dev { |
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stdcall PciRead32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND |
or al, PCI_BIT_MASTER |
stdcall PciWrite32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND, eax |
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} |
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macro PCI_adjust_latency min { |
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local .not |
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stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY |
cmp al, min |
ja .not |
mov al, min |
stdcall PciWrite8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY, eax |
.not: |
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} |
Property changes: |
Added: svn:eol-style |
+native |
\ No newline at end of property |