1,12 → 1,13 |
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#ifndef __PCI_H__ |
#define __PCI_H__ |
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#include <types.h> |
#include <list.h> |
#include <ioport.h> |
#include <pci_regs.h> |
#include <linux/errno.h> |
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#ifndef __PCI_H__ |
#define __PCI_H__ |
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/* pci_slot represents a physical slot */ |
struct pci_slot { |
struct pci_bus *bus; /* The bus this slot is on */ |
238,16 → 239,6 |
return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
} |
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struct resource |
{ |
resource_size_t start; |
resource_size_t end; |
const char *name; |
unsigned long flags; |
struct resource *parent, *sibling, *child; |
}; |
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/* This defines the direction arg to the DMA mapping routines. */ |
#define PCI_DMA_BIDIRECTIONAL 0 |
#define PCI_DMA_TODEVICE 1 |
287,75 → 278,6 |
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/* |
* IO resources have these defined flags. |
*/ |
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
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#define IORESOURCE_IO 0x00000100 /* Resource type */ |
#define IORESOURCE_MEM 0x00000200 |
#define IORESOURCE_IRQ 0x00000400 |
#define IORESOURCE_DMA 0x00000800 |
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#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ |
#define IORESOURCE_READONLY 0x00002000 |
#define IORESOURCE_CACHEABLE 0x00004000 |
#define IORESOURCE_RANGELENGTH 0x00008000 |
#define IORESOURCE_SHADOWABLE 0x00010000 |
#define IORESOURCE_BUS_HAS_VGA 0x00080000 |
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#define IORESOURCE_DISABLED 0x10000000 |
#define IORESOURCE_UNSET 0x20000000 |
#define IORESOURCE_AUTO 0x40000000 |
#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
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/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
#define IORESOURCE_IRQ_LOWEDGE (1<<1) |
#define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
#define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
#define IORESOURCE_IRQ_SHAREABLE (1<<4) |
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/* ISA PnP DMA specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_DMA_TYPE_MASK (3<<0) |
#define IORESOURCE_DMA_8BIT (0<<0) |
#define IORESOURCE_DMA_8AND16BIT (1<<0) |
#define IORESOURCE_DMA_16BIT (2<<0) |
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#define IORESOURCE_DMA_MASTER (1<<2) |
#define IORESOURCE_DMA_BYTE (1<<3) |
#define IORESOURCE_DMA_WORD (1<<4) |
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#define IORESOURCE_DMA_SPEED_MASK (3<<6) |
#define IORESOURCE_DMA_COMPATIBLE (0<<6) |
#define IORESOURCE_DMA_TYPEA (1<<6) |
#define IORESOURCE_DMA_TYPEB (2<<6) |
#define IORESOURCE_DMA_TYPEF (3<<6) |
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/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ |
#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
#define IORESOURCE_MEM_TYPE_MASK (3<<3) |
#define IORESOURCE_MEM_8BIT (0<<3) |
#define IORESOURCE_MEM_16BIT (1<<3) |
#define IORESOURCE_MEM_8AND16BIT (2<<3) |
#define IORESOURCE_MEM_32BIT (3<<3) |
#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
#define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
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/* PCI ROM control bits (IORESOURCE_BITS) */ |
#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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/* |
* For PCI devices, the region numbers are assigned this way: |
* |
* 0-5 standard PCI regions |
388,6 → 310,14 |
#define PCI_UNKNOWN ((pci_power_t __force) 5) |
#define PCI_POWER_ERROR ((pci_power_t __force) -1) |
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enum pci_bar_type { |
pci_bar_unknown, /* Standard PCI BAR probe */ |
pci_bar_io, /* An io port BAR */ |
pci_bar_mem32, /* A 32-bit memory BAR */ |
pci_bar_mem64, /* A 64-bit memory BAR */ |
}; |
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/* |
* The pci_dev structure is used to describe PCI devices. |
*/ |
479,7 → 409,7 |
// u32 saved_config_space[16]; /* config space saved at suspend time */ |
// struct hlist_head saved_cap_space; |
// struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
// int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
// struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
// struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
}; |
622,6 → 552,7 |
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extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
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int enum_pci_devices(void); |
642,7 → 573,10 |
int cap); |
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
struct pci_bus * pci_find_next_bus(const struct pci_bus *from); |
unsigned int pci_scan_child_bus(struct pci_bus *bus); |
void pcibios_fixup_bus(struct pci_bus *b); |
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static inline bool pci_is_root_bus(struct pci_bus *pbus) |
{ |
return !(pbus->parent); |
675,6 → 609,49 |
return !!pci_pcie_cap(dev); |
} |
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int pci_read_config_dyte(struct pci_dev *dev, int where, u16 *val); |
int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); |
int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
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static inline int pci_iov_init(struct pci_dev *dev) |
{ |
return -ENODEV; |
} |
static inline void pci_iov_release(struct pci_dev *dev) |
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{ |
} |
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
enum pci_bar_type *type) |
{ |
return 0; |
} |
static inline void pci_restore_iov_state(struct pci_dev *dev) |
{ |
} |
static inline int pci_iov_bus_range(struct pci_bus *bus) |
{ |
return 0; |
} |
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static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
{ |
return -ENODEV; |
} |
static inline void pci_disable_ats(struct pci_dev *dev) |
{ |
} |
static inline int pci_ats_queue_depth(struct pci_dev *dev) |
{ |
return -ENODEV; |
} |
static inline int pci_ats_enabled(struct pci_dev *dev) |
{ |
return 0; |
} |
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#define pci_name(x) "radeon" |
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#endif //__PCI__H__ |