| 25,6 → 25,7 |
|---|
| |
| #include <linux/types.h> |
| #include <linux/i2c.h> |
| #include <linux/delay.h> |
| |
| /* |
| * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
| 311,6 → 312,14 |
|---|
| #define MODE_I2C_READ 4 |
| #define MODE_I2C_STOP 8 |
| |
| /** |
| * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp |
| * aux algorithm |
| * @running: set by the algo indicating whether an i2c is ongoing or whether |
| * the i2c bus is quiescent |
| * @address: i2c target address for the currently ongoing transfer |
| * @aux_ch: driver callback to transfer a single byte of the i2c payload |
| */ |
| struct i2c_algo_dp_aux_data { |
| bool running; |
| u16 address; |
| 322,4 → 331,34 |
|---|
| int |
| i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
| |
| |
| #define DP_LINK_STATUS_SIZE 6 |
| bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane_count); |
| bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane_count); |
| u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane); |
| u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane); |
| |
| #define DP_RECEIVER_CAP_SIZE 0xf |
| void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| |
| u8 drm_dp_link_rate_to_bw_code(int link_rate); |
| int drm_dp_bw_code_to_link_rate(u8 link_bw); |
| |
| static inline int |
| drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |
| return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
| } |
| |
| static inline u8 |
| drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |
| return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
| } |
| |
| #endif /* _DRM_DP_HELPER_H_ */ |