| 26,7 → 26,19 |
|---|
| #include <linux/types.h> |
| #include <linux/i2c.h> |
| |
| /* From the VESA DisplayPort spec */ |
| /* |
| * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
| * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
| * 1.0 devices basically don't exist in the wild. |
| * |
| * Abbreviations, in chronological order: |
| * |
| * eDP: Embedded DisplayPort version 1 |
| * DPI: DisplayPort Interoperability Guideline v1.1a |
| * 1.2: DisplayPort 1.2 |
| * |
| * 1.2 formally includes both eDP and DPI definitions. |
| */ |
| |
| #define AUX_NATIVE_WRITE 0x8 |
| #define AUX_NATIVE_READ 0x9 |
| 53,7 → 65,7 |
|---|
| |
| #define DP_MAX_LANE_COUNT 0x002 |
| # define DP_MAX_LANE_COUNT_MASK 0x1f |
| # define DP_TPS3_SUPPORTED (1 << 6) |
| # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
| # define DP_ENHANCED_FRAME_CAP (1 << 7) |
| |
| #define DP_MAX_DOWNSPREAD 0x003 |
| 69,15 → 81,33 |
|---|
| /* 10b = TMDS or HDMI */ |
| /* 11b = Other */ |
| # define DP_FORMAT_CONVERSION (1 << 3) |
| # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
| |
| #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
| |
| #define DP_EDP_CONFIGURATION_CAP 0x00d |
| #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
| #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
| # define DP_PORT_COUNT_MASK 0x0f |
| # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
| # define DP_OUI_SUPPORT (1 << 7) |
| |
| #define DP_PSR_SUPPORT 0x070 |
| #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
| # define DP_I2C_SPEED_1K 0x01 |
| # define DP_I2C_SPEED_5K 0x02 |
| # define DP_I2C_SPEED_10K 0x04 |
| # define DP_I2C_SPEED_100K 0x08 |
| # define DP_I2C_SPEED_400K 0x10 |
| # define DP_I2C_SPEED_1M 0x20 |
| |
| #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
| #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
| |
| /* Multiple stream transport */ |
| #define DP_MSTM_CAP 0x021 /* 1.2 */ |
| # define DP_MST_CAP (1 << 0) |
| |
| #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
| # define DP_PSR_IS_SUPPORTED 1 |
| #define DP_PSR_CAPS 0x071 |
| #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
| # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
| # define DP_PSR_SETUP_TIME_330 (0 << 1) |
| # define DP_PSR_SETUP_TIME_275 (1 << 1) |
| 89,11 → 119,36 |
|---|
| # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
| # define DP_PSR_SETUP_TIME_SHIFT 1 |
| |
| /* |
| * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
| * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
| * each port's descriptor is one byte wide. If it was set, each port's is |
| * four bytes wide, starting with the one byte from the base info. As of |
| * DP interop v1.1a only VGA defines additional detail. |
| */ |
| |
| /* offset 0 */ |
| #define DP_DOWNSTREAM_PORT_0 0x80 |
| # define DP_DS_PORT_TYPE_MASK (7 << 0) |
| # define DP_DS_PORT_TYPE_DP 0 |
| # define DP_DS_PORT_TYPE_VGA 1 |
| # define DP_DS_PORT_TYPE_DVI 2 |
| # define DP_DS_PORT_TYPE_HDMI 3 |
| # define DP_DS_PORT_TYPE_NON_EDID 4 |
| # define DP_DS_PORT_HPD (1 << 3) |
| /* offset 1 for VGA is maximum megapixels per second / 8 */ |
| /* offset 2 */ |
| # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
| # define DP_DS_VGA_8BPC 0 |
| # define DP_DS_VGA_10BPC 1 |
| # define DP_DS_VGA_12BPC 2 |
| # define DP_DS_VGA_16BPC 3 |
| |
| /* link configuration */ |
| #define DP_LINK_BW_SET 0x100 |
| # define DP_LINK_BW_1_62 0x06 |
| # define DP_LINK_BW_2_7 0x0a |
| # define DP_LINK_BW_5_4 0x14 |
| # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
| |
| #define DP_LANE_COUNT_SET 0x101 |
| # define DP_LANE_COUNT_MASK 0x0f |
| 103,7 → 158,7 |
|---|
| # define DP_TRAINING_PATTERN_DISABLE 0 |
| # define DP_TRAINING_PATTERN_1 1 |
| # define DP_TRAINING_PATTERN_2 2 |
| # define DP_TRAINING_PATTERN_3 3 |
| # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
| # define DP_TRAINING_PATTERN_MASK 0x3 |
| |
| # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
| 144,16 → 199,32 |
|---|
| |
| #define DP_DOWNSPREAD_CTRL 0x107 |
| # define DP_SPREAD_AMP_0_5 (1 << 4) |
| # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
| |
| #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
| # define DP_SET_ANSI_8B10B (1 << 0) |
| |
| #define DP_PSR_EN_CFG 0x170 |
| #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
| /* bitmask as for DP_I2C_SPEED_CAP */ |
| |
| #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
| |
| #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
| # define DP_MST_EN (1 << 0) |
| # define DP_UP_REQ_EN (1 << 1) |
| # define DP_UPSTREAM_IS_SRC (1 << 2) |
| |
| #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
| # define DP_PSR_ENABLE (1 << 0) |
| # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
| # define DP_PSR_CRC_VERIFICATION (1 << 2) |
| # define DP_PSR_FRAME_CAPTURE (1 << 3) |
| |
| #define DP_SINK_COUNT 0x200 |
| /* prior to 1.2 bit 7 was reserved mbz */ |
| # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
| # define DP_SINK_CP_READY (1 << 6) |
| |
| #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
| # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
| # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
| 160,8 → 231,6 |
|---|
| # define DP_CP_IRQ (1 << 2) |
| # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
| |
| #define DP_EDP_CONFIGURATION_SET 0x10a |
| |
| #define DP_LANE0_1_STATUS 0x202 |
| #define DP_LANE2_3_STATUS 0x203 |
| # define DP_LANE_CR_DONE (1 << 0) |
| 213,18 → 282,22 |
|---|
| # define DP_TEST_NAK (1 << 1) |
| # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
| |
| #define DP_SOURCE_OUI 0x300 |
| #define DP_SINK_OUI 0x400 |
| #define DP_BRANCH_OUI 0x500 |
| |
| #define DP_SET_POWER 0x600 |
| # define DP_SET_POWER_D0 0x1 |
| # define DP_SET_POWER_D3 0x2 |
| |
| #define DP_PSR_ERROR_STATUS 0x2006 |
| #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
| # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
| # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
| |
| #define DP_PSR_ESI 0x2007 |
| #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
| # define DP_PSR_CAPS_CHANGE (1 << 0) |
| |
| #define DP_PSR_STATUS 0x2008 |
| #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
| # define DP_PSR_SINK_INACTIVE 0 |
| # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
| # define DP_PSR_SINK_ACTIVE_RFB 2 |