/drivers/video/drm/i915/Makefile |
---|
3,7 → 3,7 |
CC = gcc.exe |
FASM = e:/fasm/fasm.exe |
DEFINES = -D__KERNEL__ -DCONFIG_X86_32 -DCONFIG_DRM_I915_FBDEV |
DEFINES = -D__KERNEL__ -DCONFIG_X86_32 -DCONFIG_DRM_I915_FBDEV -DCONFIG_DMI |
DDK_TOPDIR = /d/kos/kolibri/drivers/ddk |
DRV_INCLUDES = /d/kos/kolibri/drivers/include |
/drivers/video/drm/i915/Makefile.lto |
---|
2,7 → 2,7 |
CC = gcc |
FASM = e:/fasm/fasm.exe |
DEFINES = -D__KERNEL__ -DCONFIG_X86_32 -DCONFIG_DRM_I915_FBDEV |
DEFINES = -D__KERNEL__ -DCONFIG_X86_32 -DCONFIG_DRM_I915_FBDEV -DCONFIG_DMI |
DDK_TOPDIR = /d/kos/kolibri/drivers/ddk |
DRV_INCLUDES = /d/kos/kolibri/drivers/include |
/drivers/video/drm/i915/intel_bios.c |
---|
24,8 → 24,9 |
* Eric Anholt <eric@anholt.net> |
* |
*/ |
#include <linux/dmi.h> |
#include <drm/drm_dp_helper.h> |
#include <drm/drmP.h> |
#include <drm/drm_dp_helper.h> |
#include <drm/i915_drm.h> |
#include "i915_drv.h" |
#include "intel_bios.h" |
1122,6 → 1123,26 |
} |
} |
static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) |
{ |
DRM_DEBUG_KMS("Falling back to manually reading VBT from " |
"VBIOS ROM for %s\n", |
id->ident); |
return 1; |
} |
static const struct dmi_system_id intel_no_opregion_vbt[] = { |
{ |
.callback = intel_no_opregion_vbt_callback, |
.ident = "ThinkCentre A57", |
.matches = { |
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), |
DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"), |
}, |
}, |
{ } |
}; |
static struct bdb_header *validate_vbt(char *base, size_t size, |
struct vbt_header *vbt, |
const char *source) |
1185,7 → 1206,7 |
init_vbt_defaults(dev_priv); |
/* XXX Should this validation be moved to intel_opregion.c? */ |
if (dev_priv->opregion.vbt) |
if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt) |
bdb = validate_vbt((char *)dev_priv->opregion.header, OPREGION_SIZE, |
(struct vbt_header *)dev_priv->opregion.vbt, |
"OpRegion"); |
/drivers/video/drm/i915/intel_crt.c |
---|
24,6 → 24,7 |
* Eric Anholt <eric@anholt.net> |
*/ |
#include <linux/dmi.h> |
#include <linux/i2c.h> |
#include <linux/slab.h> |
#include <drm/drmP.h> |
803,6 → 804,32 |
.destroy = intel_encoder_destroy, |
}; |
static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
{ |
DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
return 1; |
} |
static const struct dmi_system_id intel_no_crt[] = { |
{ |
.callback = intel_no_crt_dmi_callback, |
.ident = "ACER ZGB", |
.matches = { |
DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
}, |
}, |
{ |
.callback = intel_no_crt_dmi_callback, |
.ident = "DELL XPS 8700", |
.matches = { |
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
}, |
}, |
{ } |
}; |
void intel_crt_init(struct drm_device *dev) |
{ |
struct drm_connector *connector; |
810,6 → 837,10 |
struct intel_connector *intel_connector; |
struct drm_i915_private *dev_priv = dev->dev_private; |
/* Skip machines without VGA that falsely report hotplug events */ |
if (dmi_check_system(intel_no_crt)) |
return; |
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
if (!crt) |
return; |
/drivers/video/drm/i915/intel_display.c |
---|
24,7 → 24,7 |
* Eric Anholt <eric@anholt.net> |
*/ |
//#include <linux/dmi.h> |
#include <linux/dmi.h> |
#include <linux/module.h> |
//#include <linux/input.h> |
#include <linux/i2c.h> |
2244,6 → 2244,15 |
if (need_vtd_wa(dev) && alignment < 256 * 1024) |
alignment = 256 * 1024; |
/* |
* Global gtt pte registers are special registers which actually forward |
* writes to a chunk of system memory. Which means that there is no risk |
* that the register values disappear as soon as we call |
* intel_runtime_pm_put(), so it is correct to wrap only the |
* pin/unpin/fence and not more. |
*/ |
intel_runtime_pm_get(dev_priv); |
dev_priv->mm.interruptible = false; |
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
if (ret) |
2261,6 → 2270,7 |
i915_gem_object_pin_fence(obj); |
dev_priv->mm.interruptible = true; |
intel_runtime_pm_put(dev_priv); |
return 0; |
err_unpin: |
2267,6 → 2277,7 |
i915_gem_object_unpin_from_display_plane(obj); |
err_interruptible: |
dev_priv->mm.interruptible = true; |
intel_runtime_pm_put(dev_priv); |
return ret; |
} |
4184,10 → 4195,6 |
intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
intel_disable_pipe(dev_priv, pipe); |
if (intel_crtc->config.dp_encoder_is_mst) |
intel_ddi_set_vc_payload_alloc(crtc, false); |
ironlake_pfit_disable(intel_crtc); |
for_each_encoder_on_crtc(dev, crtc, encoder) |
4252,6 → 4259,9 |
intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
intel_disable_pipe(dev_priv, pipe); |
if (intel_crtc->config.dp_encoder_is_mst) |
intel_ddi_set_vc_payload_alloc(crtc, false); |
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
ironlake_pfit_disable(intel_crtc); |
8238,6 → 8248,15 |
goto fail_locked; |
} |
/* |
* Global gtt pte registers are special registers which actually |
* forward writes to a chunk of system memory. Which means that |
* there is no risk that the register values disappear as soon |
* as we call intel_runtime_pm_put(), so it is correct to wrap |
* only the pin/unpin/fence and not more. |
*/ |
intel_runtime_pm_get(dev_priv); |
/* Note that the w/a also requires 2 PTE of padding following |
* the bo. We currently fill all unused PTE with the shadow |
* page and so we should always have valid PTE following the |
8250,6 → 8269,7 |
ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
if (ret) { |
DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
intel_runtime_pm_put(dev_priv); |
goto fail_locked; |
} |
8256,10 → 8276,13 |
ret = i915_gem_object_put_fence(obj); |
if (ret) { |
DRM_DEBUG_KMS("failed to release fence for cursor"); |
intel_runtime_pm_put(dev_priv); |
goto fail_unpin; |
} |
addr = i915_gem_obj_ggtt_offset(obj); |
intel_runtime_pm_put(dev_priv); |
} else { |
int align = IS_I830(dev) ? 16 * 1024 : 256; |
// ret = i915_gem_object_attach_phys(obj, align); |
12186,6 → 12209,9 |
/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ |
{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, |
/* Acer C720 Chromebook (Core i3 4005U) */ |
{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, |
/* Toshiba CB35 Chromebook (Celeron 2955U) */ |
{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, |
12208,7 → 12234,11 |
q->subsystem_device == PCI_ANY_ID)) |
q->hook(dev); |
} |
for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
intel_dmi_quirks[i].hook(dev); |
} |
} |
/* Disable the VGA plane that we never use */ |
static void i915_disable_vga(struct drm_device *dev) |
/drivers/video/drm/i915/intel_dp.c |
---|
3615,24 → 3615,12 |
return intel_dp_detect_dpcd(intel_dp); |
} |
static enum drm_connector_status |
g4x_dp_detect(struct intel_dp *intel_dp) |
static int g4x_digital_port_connected(struct drm_device *dev, |
struct intel_digital_port *intel_dig_port) |
{ |
struct drm_device *dev = intel_dp_to_dev(intel_dp); |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
uint32_t bit; |
/* Can't disconnect eDP, but you can close the lid... */ |
if (is_edp(intel_dp)) { |
enum drm_connector_status status; |
status = intel_panel_detect(dev); |
if (status == connector_status_unknown) |
status = connector_status_connected; |
return status; |
} |
if (IS_VALLEYVIEW(dev)) { |
switch (intel_dig_port->port) { |
case PORT_B: |
3645,7 → 3633,7 |
bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
break; |
default: |
return connector_status_unknown; |
return -EINVAL; |
} |
} else { |
switch (intel_dig_port->port) { |
3659,11 → 3647,36 |
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
break; |
default: |
return connector_status_unknown; |
return -EINVAL; |
} |
} |
if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
return 0; |
return 1; |
} |
static enum drm_connector_status |
g4x_dp_detect(struct intel_dp *intel_dp) |
{ |
struct drm_device *dev = intel_dp_to_dev(intel_dp); |
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
int ret; |
/* Can't disconnect eDP, but you can close the lid... */ |
if (is_edp(intel_dp)) { |
enum drm_connector_status status; |
status = intel_panel_detect(dev); |
if (status == connector_status_unknown) |
status = connector_status_connected; |
return status; |
} |
ret = g4x_digital_port_connected(dev, intel_dig_port); |
if (ret == -EINVAL) |
return connector_status_unknown; |
else if (ret == 0) |
return connector_status_disconnected; |
return intel_dp_detect_dpcd(intel_dp); |
4016,8 → 4029,14 |
intel_display_power_get(dev_priv, power_domain); |
if (long_hpd) { |
if (HAS_PCH_SPLIT(dev)) { |
if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
goto mst_fail; |
} else { |
if (g4x_digital_port_connected(dev, intel_dig_port) != 1) |
goto mst_fail; |
} |
if (!intel_dp_get_dpcd(intel_dp)) { |
goto mst_fail; |
/drivers/video/drm/i915/intel_lvds.c |
---|
28,7 → 28,7 |
*/ |
//#include <acpi/button.h> |
//#include <linux/dmi.h> |
#include <linux/dmi.h> |
#include <linux/i2c.h> |
#include <linux/slab.h> |
#include <drm/drmP.h> |
538,7 → 538,7 |
.destroy = intel_encoder_destroy, |
}; |
static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
{ |
DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
return 1; |
845,8 → 845,8 |
if (i915.lvds_channel_mode > 0) |
return i915.lvds_channel_mode == 2; |
// if (dmi_check_system(intel_dual_link_lvds)) |
// return true; |
if (dmi_check_system(intel_dual_link_lvds)) |
return true; |
/* BIOS should set the proper LVDS register value at boot, but |
* in reality, it doesn't set the value when the lid is closed; |
904,8 → 904,8 |
return; |
/* Skip init on machines we know falsely report LVDS */ |
// if (dmi_check_system(intel_no_lvds)) |
// return false; |
if (dmi_check_system(intel_no_lvds)) |
return; |
pin = GMBUS_PORT_PANEL; |
if (!lvds_is_present_in_vbt(dev, &pin)) { |
/drivers/video/drm/i915/intel_panel.c |
---|
796,7 → 796,7 |
cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
if (cpu_ctl2 & BLM_PWM_ENABLE) { |
WARN(1, "cpu backlight already enabled\n"); |
DRM_DEBUG_KMS("cpu backlight already enabled\n"); |
cpu_ctl2 &= ~BLM_PWM_ENABLE; |
I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); |
} |
840,7 → 840,7 |
ctl = I915_READ(BLC_PWM_CTL); |
if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { |
WARN(1, "backlight already enabled\n"); |
DRM_DEBUG_KMS("backlight already enabled\n"); |
I915_WRITE(BLC_PWM_CTL, 0); |
} |
871,7 → 871,7 |
ctl2 = I915_READ(BLC_PWM_CTL2); |
if (ctl2 & BLM_PWM_ENABLE) { |
WARN(1, "backlight already enabled\n"); |
DRM_DEBUG_KMS("backlight already enabled\n"); |
ctl2 &= ~BLM_PWM_ENABLE; |
I915_WRITE(BLC_PWM_CTL2, ctl2); |
} |
905,7 → 905,7 |
ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
if (ctl2 & BLM_PWM_ENABLE) { |
WARN(1, "backlight already enabled\n"); |
DRM_DEBUG_KMS("backlight already enabled\n"); |
ctl2 &= ~BLM_PWM_ENABLE; |
I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); |
} |
/drivers/video/drm/i915/main.c |
---|
220,6 → 220,8 |
return 0; |
} |
dmi_scan_machine(); |
driver_wq_state = I915_DEV_INIT; |
CreateKernelThread(i915_driver_thread); |
/drivers/video/drm/radeon/main.c |
---|
5,6 → 5,8 |
#include "radeon.h" |
#include "bitmap.h" |
void __init dmi_scan_machine(void); |
#define KMS_DEV_CLOSE 0 |
#define KMS_DEV_INIT 1 |
#define KMS_DEV_READY 2 |
/drivers/video/drm/radeon/radeon_device.c |
---|
1492,7 → 1492,7 |
dev->dev_private = (void *)rdev; |
/* update BUS flag */ |
if (drm_device_is_agp(dev)) { |
if (drm_pci_device_is_agp(dev)) { |
flags |= RADEON_IS_AGP; |
} else if (drm_device_is_pcie(dev)) { |
flags |= RADEON_IS_PCIE; |