Subversion Repositories Kolibri OS

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Regard whitespace Rev 1427 → Rev 1428

/drivers/include/drm/drmP.h
1472,7 → 1472,7
struct drm_ati_pcigart_info * gart_info);
 
extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
size_t align, dma_addr_t maxaddr);
size_t align);
extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
 
/drivers/include/drm/drm_crtc_helper.h
35,7 → 35,7
 
//#include <linux/spinlock.h>
#include <linux/types.h>
//#include <linux/idr.h>
#include <linux/idr.h>
 
#include <linux/fb.h>
 
/drivers/include/linux/asm/unaligned.h
0,0 → 1,14
#ifndef _ASM_X86_UNALIGNED_H
#define _ASM_X86_UNALIGNED_H
 
/*
* The x86 can do unaligned accesses itself.
*/
 
#include <linux/unaligned/access_ok.h>
#include <linux/unaligned/generic.h>
 
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
 
#endif /* _ASM_X86_UNALIGNED_H */
/drivers/include/linux/unaligned/access_ok.h
0,0 → 1,67
#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
#define _LINUX_UNALIGNED_ACCESS_OK_H
 
#include <linux/kernel.h>
#include <asm/byteorder.h>
 
static inline u16 get_unaligned_le16(const void *p)
{
return le16_to_cpup((__le16 *)p);
}
 
static inline u32 get_unaligned_le32(const void *p)
{
return le32_to_cpup((__le32 *)p);
}
 
static inline u64 get_unaligned_le64(const void *p)
{
return le64_to_cpup((__le64 *)p);
}
 
static inline u16 get_unaligned_be16(const void *p)
{
return be16_to_cpup((__be16 *)p);
}
 
static inline u32 get_unaligned_be32(const void *p)
{
return be32_to_cpup((__be32 *)p);
}
 
static inline u64 get_unaligned_be64(const void *p)
{
return be64_to_cpup((__be64 *)p);
}
 
static inline void put_unaligned_le16(u16 val, void *p)
{
*((__le16 *)p) = cpu_to_le16(val);
}
 
static inline void put_unaligned_le32(u32 val, void *p)
{
*((__le32 *)p) = cpu_to_le32(val);
}
 
static inline void put_unaligned_le64(u64 val, void *p)
{
*((__le64 *)p) = cpu_to_le64(val);
}
 
static inline void put_unaligned_be16(u16 val, void *p)
{
*((__be16 *)p) = cpu_to_be16(val);
}
 
static inline void put_unaligned_be32(u32 val, void *p)
{
*((__be32 *)p) = cpu_to_be32(val);
}
 
static inline void put_unaligned_be64(u64 val, void *p)
{
*((__be64 *)p) = cpu_to_be64(val);
}
 
#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
/drivers/include/linux/unaligned/generic.h
0,0 → 1,68
#ifndef _LINUX_UNALIGNED_GENERIC_H
#define _LINUX_UNALIGNED_GENERIC_H
 
/*
* Cause a link-time error if we try an unaligned access other than
* 1,2,4 or 8 bytes long
*/
extern void __bad_unaligned_access_size(void);
 
#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
__bad_unaligned_access_size())))); \
}))
 
#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
__bad_unaligned_access_size())))); \
}))
 
#define __put_unaligned_le(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_le16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_le32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_le64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
 
#define __put_unaligned_be(val, ptr) ({ \
void *__gu_p = (ptr); \
switch (sizeof(*(ptr))) { \
case 1: \
*(u8 *)__gu_p = (__force u8)(val); \
break; \
case 2: \
put_unaligned_be16((__force u16)(val), __gu_p); \
break; \
case 4: \
put_unaligned_be32((__force u32)(val), __gu_p); \
break; \
case 8: \
put_unaligned_be64((__force u64)(val), __gu_p); \
break; \
default: \
__bad_unaligned_access_size(); \
break; \
} \
(void)0; })
 
#endif /* _LINUX_UNALIGNED_GENERIC_H */
/drivers/video/drm/drm_edid.c
598,6 → 598,50
return mode;
}
 
/*
* EDID is delightfully ambiguous about how interlaced modes are to be
* encoded. Our internal representation is of frame height, but some
* HDTV detailed timings are encoded as field height.
*
* The format list here is from CEA, in frame size. Technically we
* should be checking refresh rate too. Whatever.
*/
static void
drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
struct detailed_pixel_timing *pt)
{
int i;
static const struct {
int w, h;
} cea_interlaced[] = {
{ 1920, 1080 },
{ 720, 480 },
{ 1440, 480 },
{ 2880, 480 },
{ 720, 576 },
{ 1440, 576 },
{ 2880, 576 },
};
static const int n_sizes =
sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
 
if (!(pt->misc & DRM_EDID_PT_INTERLACED))
return;
 
for (i = 0; i < n_sizes; i++) {
if ((mode->hdisplay == cea_interlaced[i].w) &&
(mode->vdisplay == cea_interlaced[i].h / 2)) {
mode->vdisplay *= 2;
mode->vsync_start *= 2;
mode->vsync_end *= 2;
mode->vtotal *= 2;
mode->vtotal |= 1;
}
}
 
mode->flags |= DRM_MODE_FLAG_INTERLACE;
}
 
/**
* drm_mode_detailed - create a new mode from an EDID detailed timing section
* @dev: DRM device (needed to create new mode)
680,8 → 724,7
 
drm_mode_set_name(mode);
 
if (pt->misc & DRM_EDID_PT_INTERLACED)
mode->flags |= DRM_MODE_FLAG_INTERLACE;
drm_mode_do_interlace_quirk(mode, pt);
 
if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
/drivers/video/drm/radeon/atom.c
24,6 → 24,7
 
#include <linux/module.h>
#include <linux/sched.h>
#include <asm/unaligned.h>
 
#define ATOM_DEBUG
 
212,7 → 213,9
case ATOM_ARG_PS:
idx = U8(*ptr);
(*ptr)++;
val = le32_to_cpu(ctx->ps[idx]);
/* get_unaligned_le32 avoids unaligned accesses from atombios
* tables, noticed on a DEC Alpha. */
val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
if (print)
DEBUG("PS[0x%02X,0x%04X]", idx, val);
break;
/drivers/video/drm/radeon/atombios_dp.c
350,7 → 350,7
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
if (args.ucReplyStatus && !args.ucDataOutLen) {
if (args.ucReplyStatus == 0x20 && retry_count < 10)
if (args.ucReplyStatus == 0x20 && retry_count++ < 10)
goto retry;
DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
/drivers/video/drm/radeon/r520.c
279,7 → 279,6
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n");
// rv515_suspend(rdev);
// r100_cp_fini(rdev);
// r100_wb_fini(rdev);
// r100_ib_fini(rdev);
/drivers/video/drm/radeon/r600.c
1894,6 → 1894,7
rdev->accel_working = true;
r = r600_startup(rdev);
if (r) {
dev_err(rdev->dev, "disabling GPU acceleration\n");
// r600_suspend(rdev);
// r600_wb_fini(rdev);
// radeon_ring_fini(rdev);
/drivers/video/drm/radeon/r600_reg_auto_r6xx.h
0,0 → 1,3087
/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
 
#ifndef _AUTOREGS
#define _AUTOREGS
 
enum {
 
VGT_VTX_VECT_EJECT_REG = 0x000088b0,
PRIM_COUNT_mask = 0x3ff << 0,
PRIM_COUNT_shift = 0,
VGT_LAST_COPY_STATE = 0x000088c0,
SRC_STATE_ID_mask = 0x07 << 0,
SRC_STATE_ID_shift = 0,
DST_STATE_ID_mask = 0x07 << 16,
DST_STATE_ID_shift = 16,
VGT_CACHE_INVALIDATION = 0x000088c4,
CACHE_INVALIDATION_mask = 0x03 << 0,
CACHE_INVALIDATION_shift = 0,
VC_ONLY = 0x00,
TC_ONLY = 0x01,
VC_AND_TC = 0x02,
VS_NO_EXTRA_BUFFER_bit = 1 << 5,
VGT_GS_PER_ES = 0x000088c8,
VGT_ES_PER_GS = 0x000088cc,
VGT_GS_VERTEX_REUSE = 0x000088d4,
VERT_REUSE_mask = 0x1f << 0,
VERT_REUSE_shift = 0,
VGT_MC_LAT_CNTL = 0x000088d8,
MC_TIME_STAMP_RES_mask = 0x03 << 0,
MC_TIME_STAMP_RES_shift = 0,
X_0_992_MAX_LATENCY = 0x00,
X_0_496_MAX_LATENCY = 0x01,
X_0_248_MAX_LATENCY = 0x02,
X_0_124_MAX_LATENCY = 0x03,
VGT_GS_PER_VS = 0x000088e8,
GS_PER_VS_mask = 0x0f << 0,
GS_PER_VS_shift = 0,
VGT_CNTL_STATUS = 0x000088f0,
VGT_OUT_INDX_BUSY_bit = 1 << 0,
VGT_OUT_BUSY_bit = 1 << 1,
VGT_PT_BUSY_bit = 1 << 2,
VGT_TE_BUSY_bit = 1 << 3,
VGT_VR_BUSY_bit = 1 << 4,
VGT_GRP_BUSY_bit = 1 << 5,
VGT_DMA_REQ_BUSY_bit = 1 << 6,
VGT_DMA_BUSY_bit = 1 << 7,
VGT_GS_BUSY_bit = 1 << 8,
VGT_BUSY_bit = 1 << 9,
VGT_PRIMITIVE_TYPE = 0x00008958,
VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0,
VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0,
DI_PT_NONE = 0x00,
DI_PT_POINTLIST = 0x01,
DI_PT_LINELIST = 0x02,
DI_PT_LINESTRIP = 0x03,
DI_PT_TRILIST = 0x04,
DI_PT_TRIFAN = 0x05,
DI_PT_TRISTRIP = 0x06,
DI_PT_UNUSED_0 = 0x07,
DI_PT_UNUSED_1 = 0x08,
DI_PT_UNUSED_2 = 0x09,
DI_PT_LINELIST_ADJ = 0x0a,
DI_PT_LINESTRIP_ADJ = 0x0b,
DI_PT_TRILIST_ADJ = 0x0c,
DI_PT_TRISTRIP_ADJ = 0x0d,
DI_PT_UNUSED_3 = 0x0e,
DI_PT_UNUSED_4 = 0x0f,
DI_PT_TRI_WITH_WFLAGS = 0x10,
DI_PT_RECTLIST = 0x11,
DI_PT_LINELOOP = 0x12,
DI_PT_QUADLIST = 0x13,
DI_PT_QUADSTRIP = 0x14,
DI_PT_POLYGON = 0x15,
DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
DI_PT_2D_FILL_RECT_LIST = 0x1a,
DI_PT_2D_LINE_STRIP = 0x1b,
DI_PT_2D_TRI_STRIP = 0x1c,
VGT_INDEX_TYPE = 0x0000895c,
INDEX_TYPE_mask = 0x03 << 0,
INDEX_TYPE_shift = 0,
DI_INDEX_SIZE_16_BIT = 0x00,
DI_INDEX_SIZE_32_BIT = 0x01,
VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960,
VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964,
VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968,
VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c,
VGT_NUM_INDICES = 0x00008970,
VGT_NUM_INSTANCES = 0x00008974,
PA_CL_CNTL_STATUS = 0x00008a10,
CL_BUSY_bit = 1 << 31,
PA_CL_ENHANCE = 0x00008a14,
CLIP_VTX_REORDER_ENA_bit = 1 << 0,
NUM_CLIP_SEQ_mask = 0x03 << 1,
NUM_CLIP_SEQ_shift = 1,
CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3,
VE_NAN_PROC_DISABLE_bit = 1 << 4,
PA_SU_CNTL_STATUS = 0x00008a50,
SU_BUSY_bit = 1 << 31,
PA_SC_LINE_STIPPLE_STATE = 0x00008b10,
CURRENT_PTR_mask = 0x0f << 0,
CURRENT_PTR_shift = 0,
CURRENT_COUNT_mask = 0xff << 8,
CURRENT_COUNT_shift = 8,
PA_SC_MULTI_CHIP_CNTL = 0x00008b20,
LOG2_NUM_CHIPS_mask = 0x07 << 0,
LOG2_NUM_CHIPS_shift = 0,
MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3,
MULTI_CHIP_TILE_SIZE_shift = 3,
X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00,
X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01,
X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02,
X_128X128_PIXEL_TILE_PER_CHIP = 0x03,
CHIP_TILE_X_LOC_mask = 0x07 << 5,
CHIP_TILE_X_LOC_shift = 5,
CHIP_TILE_Y_LOC_mask = 0x07 << 8,
CHIP_TILE_Y_LOC_shift = 8,
CHIP_SUPER_TILE_B_bit = 1 << 11,
PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40,
S0_X_mask = 0x0f << 0,
S0_X_shift = 0,
S0_Y_mask = 0x0f << 4,
S0_Y_shift = 4,
S1_X_mask = 0x0f << 8,
S1_X_shift = 8,
S1_Y_mask = 0x0f << 12,
S1_Y_shift = 12,
PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44,
/* S0_X_mask = 0x0f << 0, */
/* S0_X_shift = 0, */
/* S0_Y_mask = 0x0f << 4, */
/* S0_Y_shift = 4, */
/* S1_X_mask = 0x0f << 8, */
/* S1_X_shift = 8, */
/* S1_Y_mask = 0x0f << 12, */
/* S1_Y_shift = 12, */
S2_X_mask = 0x0f << 16,
S2_X_shift = 16,
S2_Y_mask = 0x0f << 20,
S2_Y_shift = 20,
S3_X_mask = 0x0f << 24,
S3_X_shift = 24,
S3_Y_mask = 0x0f << 28,
S3_Y_shift = 28,
PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48,
/* S0_X_mask = 0x0f << 0, */
/* S0_X_shift = 0, */
/* S0_Y_mask = 0x0f << 4, */
/* S0_Y_shift = 4, */
/* S1_X_mask = 0x0f << 8, */
/* S1_X_shift = 8, */
/* S1_Y_mask = 0x0f << 12, */
/* S1_Y_shift = 12, */
/* S2_X_mask = 0x0f << 16, */
/* S2_X_shift = 16, */
/* S2_Y_mask = 0x0f << 20, */
/* S2_Y_shift = 20, */
/* S3_X_mask = 0x0f << 24, */
/* S3_X_shift = 24, */
/* S3_Y_mask = 0x0f << 28, */
/* S3_Y_shift = 28, */
PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c,
S4_X_mask = 0x0f << 0,
S4_X_shift = 0,
S4_Y_mask = 0x0f << 4,
S4_Y_shift = 4,
S5_X_mask = 0x0f << 8,
S5_X_shift = 8,
S5_Y_mask = 0x0f << 12,
S5_Y_shift = 12,
S6_X_mask = 0x0f << 16,
S6_X_shift = 16,
S6_Y_mask = 0x0f << 20,
S6_Y_shift = 20,
S7_X_mask = 0x0f << 24,
S7_X_shift = 24,
S7_Y_mask = 0x0f << 28,
S7_Y_shift = 28,
PA_SC_CNTL_STATUS = 0x00008be0,
MPASS_OVERFLOW_bit = 1 << 30,
PA_SC_ENHANCE = 0x00008bf0,
FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0,
FORCE_EOV_MAX_CLK_CNT_shift = 0,
FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12,
FORCE_EOV_MAX_TILE_CNT_shift = 12,
SQ_CONFIG = 0x00008c00,
VC_ENABLE_bit = 1 << 0,
EXPORT_SRC_C_bit = 1 << 1,
DX9_CONSTS_bit = 1 << 2,
ALU_INST_PREFER_VECTOR_bit = 1 << 3,
SQ_CONFIG__DX10_CLAMP_bit = 1 << 4,
ALU_PREFER_ONE_WATERFALL_bit = 1 << 5,
ALU_MAX_ONE_WATERFALL_bit = 1 << 6,
CLAUSE_SEQ_PRIO_mask = 0x03 << 8,
CLAUSE_SEQ_PRIO_shift = 8,
SQ_CL_PRIO_RND_ROBIN = 0x00,
SQ_CL_PRIO_MACRO_SEQ = 0x01,
SQ_CL_PRIO_NONE = 0x02,
PS_PRIO_mask = 0x03 << 24,
PS_PRIO_shift = 24,
VS_PRIO_mask = 0x03 << 26,
VS_PRIO_shift = 26,
GS_PRIO_mask = 0x03 << 28,
GS_PRIO_shift = 28,
ES_PRIO_mask = 0x03 << 30,
ES_PRIO_shift = 30,
SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04,
NUM_PS_GPRS_mask = 0xff << 0,
NUM_PS_GPRS_shift = 0,
NUM_VS_GPRS_mask = 0xff << 16,
NUM_VS_GPRS_shift = 16,
NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28,
NUM_CLAUSE_TEMP_GPRS_shift = 28,
SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08,
NUM_GS_GPRS_mask = 0xff << 0,
NUM_GS_GPRS_shift = 0,
NUM_ES_GPRS_mask = 0xff << 16,
NUM_ES_GPRS_shift = 16,
SQ_THREAD_RESOURCE_MGMT = 0x00008c0c,
NUM_PS_THREADS_mask = 0xff << 0,
NUM_PS_THREADS_shift = 0,
NUM_VS_THREADS_mask = 0xff << 8,
NUM_VS_THREADS_shift = 8,
NUM_GS_THREADS_mask = 0xff << 16,
NUM_GS_THREADS_shift = 16,
NUM_ES_THREADS_mask = 0xff << 24,
NUM_ES_THREADS_shift = 24,
SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10,
NUM_PS_STACK_ENTRIES_mask = 0xfff << 0,
NUM_PS_STACK_ENTRIES_shift = 0,
NUM_VS_STACK_ENTRIES_mask = 0xfff << 16,
NUM_VS_STACK_ENTRIES_shift = 16,
SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14,
NUM_GS_STACK_ENTRIES_mask = 0xfff << 0,
NUM_GS_STACK_ENTRIES_shift = 0,
NUM_ES_STACK_ENTRIES_mask = 0xfff << 16,
NUM_ES_STACK_ENTRIES_shift = 16,
SQ_ESGS_RING_BASE = 0x00008c40,
SQ_ESGS_RING_SIZE = 0x00008c44,
SQ_GSVS_RING_BASE = 0x00008c48,
SQ_GSVS_RING_SIZE = 0x00008c4c,
SQ_ESTMP_RING_BASE = 0x00008c50,
SQ_ESTMP_RING_SIZE = 0x00008c54,
SQ_GSTMP_RING_BASE = 0x00008c58,
SQ_GSTMP_RING_SIZE = 0x00008c5c,
SQ_VSTMP_RING_BASE = 0x00008c60,
SQ_VSTMP_RING_SIZE = 0x00008c64,
SQ_PSTMP_RING_BASE = 0x00008c68,
SQ_PSTMP_RING_SIZE = 0x00008c6c,
SQ_FBUF_RING_BASE = 0x00008c70,
SQ_FBUF_RING_SIZE = 0x00008c74,
SQ_REDUC_RING_BASE = 0x00008c78,
SQ_REDUC_RING_SIZE = 0x00008c7c,
SQ_ALU_WORD1_OP3 = 0x00008dfc,
SRC2_SEL_mask = 0x1ff << 0,
SRC2_SEL_shift = 0,
SQ_ALU_SRC_0 = 0xf8,
SQ_ALU_SRC_1 = 0xf9,
SQ_ALU_SRC_1_INT = 0xfa,
SQ_ALU_SRC_M_1_INT = 0xfb,
SQ_ALU_SRC_0_5 = 0xfc,
SQ_ALU_SRC_LITERAL = 0xfd,
SQ_ALU_SRC_PV = 0xfe,
SQ_ALU_SRC_PS = 0xff,
SRC2_REL_bit = 1 << 9,
SRC2_CHAN_mask = 0x03 << 10,
SRC2_CHAN_shift = 10,
SQ_CHAN_X = 0x00,
SQ_CHAN_Y = 0x01,
SQ_CHAN_Z = 0x02,
SQ_CHAN_W = 0x03,
SRC2_NEG_bit = 1 << 12,
SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
SQ_ALU_WORD1_OP3__ALU_INST_shift = 13,
SQ_OP3_INST_MUL_LIT = 0x0c,
SQ_OP3_INST_MUL_LIT_M2 = 0x0d,
SQ_OP3_INST_MUL_LIT_M4 = 0x0e,
SQ_OP3_INST_MUL_LIT_D2 = 0x0f,
SQ_OP3_INST_MULADD = 0x10,
SQ_OP3_INST_MULADD_M2 = 0x11,
SQ_OP3_INST_MULADD_M4 = 0x12,
SQ_OP3_INST_MULADD_D2 = 0x13,
SQ_OP3_INST_MULADD_IEEE = 0x14,
SQ_OP3_INST_MULADD_IEEE_M2 = 0x15,
SQ_OP3_INST_MULADD_IEEE_M4 = 0x16,
SQ_OP3_INST_MULADD_IEEE_D2 = 0x17,
SQ_OP3_INST_CNDE = 0x18,
SQ_OP3_INST_CNDGT = 0x19,
SQ_OP3_INST_CNDGE = 0x1a,
SQ_OP3_INST_CNDE_INT = 0x1c,
SQ_OP3_INST_CNDGT_INT = 0x1d,
SQ_OP3_INST_CNDGE_INT = 0x1e,
SQ_TEX_WORD2 = 0x00008dfc,
OFFSET_X_mask = 0x1f << 0,
OFFSET_X_shift = 0,
OFFSET_Y_mask = 0x1f << 5,
OFFSET_Y_shift = 5,
OFFSET_Z_mask = 0x1f << 10,
OFFSET_Z_shift = 10,
SAMPLER_ID_mask = 0x1f << 15,
SAMPLER_ID_shift = 15,
SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20,
SQ_TEX_WORD2__SRC_SEL_X_shift = 20,
SQ_SEL_X = 0x00,
SQ_SEL_Y = 0x01,
SQ_SEL_Z = 0x02,
SQ_SEL_W = 0x03,
SQ_SEL_0 = 0x04,
SQ_SEL_1 = 0x05,
SRC_SEL_Y_mask = 0x07 << 23,
SRC_SEL_Y_shift = 23,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SRC_SEL_Z_mask = 0x07 << 26,
SRC_SEL_Z_shift = 26,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SRC_SEL_W_mask = 0x07 << 29,
SRC_SEL_W_shift = 29,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
BURST_COUNT_mask = 0x0f << 17,
BURST_COUNT_shift = 17,
END_OF_PROGRAM_bit = 1 << 21,
VALID_PIXEL_MODE_bit = 1 << 22,
SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23,
SQ_CF_INST_MEM_STREAM0 = 0x20,
SQ_CF_INST_MEM_STREAM1 = 0x21,
SQ_CF_INST_MEM_STREAM2 = 0x22,
SQ_CF_INST_MEM_STREAM3 = 0x23,
SQ_CF_INST_MEM_SCRATCH = 0x24,
SQ_CF_INST_MEM_REDUCTION = 0x25,
SQ_CF_INST_MEM_RING = 0x26,
SQ_CF_INST_EXPORT = 0x27,
SQ_CF_INST_EXPORT_DONE = 0x28,
WHOLE_QUAD_MODE_bit = 1 << 30,
BARRIER_bit = 1 << 31,
SQ_CF_ALU_WORD1 = 0x00008dfc,
KCACHE_MODE1_mask = 0x03 << 0,
KCACHE_MODE1_shift = 0,
SQ_CF_KCACHE_NOP = 0x00,
SQ_CF_KCACHE_LOCK_1 = 0x01,
SQ_CF_KCACHE_LOCK_2 = 0x02,
SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03,
KCACHE_ADDR0_mask = 0xff << 2,
KCACHE_ADDR0_shift = 2,
KCACHE_ADDR1_mask = 0xff << 10,
KCACHE_ADDR1_shift = 10,
SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18,
SQ_CF_ALU_WORD1__COUNT_shift = 18,
SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26,
SQ_CF_ALU_WORD1__CF_INST_shift = 26,
SQ_CF_INST_ALU = 0x08,
SQ_CF_INST_ALU_PUSH_BEFORE = 0x09,
SQ_CF_INST_ALU_POP_AFTER = 0x0a,
SQ_CF_INST_ALU_POP2_AFTER = 0x0b,
SQ_CF_INST_ALU_CONTINUE = 0x0d,
SQ_CF_INST_ALU_BREAK = 0x0e,
SQ_CF_INST_ALU_ELSE_AFTER = 0x0f,
/* WHOLE_QUAD_MODE_bit = 1 << 30, */
/* BARRIER_bit = 1 << 31, */
SQ_TEX_WORD1 = 0x00008dfc,
SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0,
SQ_TEX_WORD1__DST_GPR_shift = 0,
SQ_TEX_WORD1__DST_REL_bit = 1 << 7,
SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9,
SQ_TEX_WORD1__DST_SEL_X_shift = 9,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SQ_SEL_MASK = 0x07,
SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
SQ_TEX_WORD1__DST_SEL_Y_shift = 12,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
SQ_TEX_WORD1__DST_SEL_Z_shift = 15,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18,
SQ_TEX_WORD1__DST_SEL_W_shift = 18,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21,
SQ_TEX_WORD1__LOD_BIAS_shift = 21,
COORD_TYPE_X_bit = 1 << 28,
COORD_TYPE_Y_bit = 1 << 29,
COORD_TYPE_Z_bit = 1 << 30,
COORD_TYPE_W_bit = 1 << 31,
SQ_VTX_WORD0 = 0x00008dfc,
VTX_INST_mask = 0x1f << 0,
VTX_INST_shift = 0,
SQ_VTX_INST_FETCH = 0x00,
SQ_VTX_INST_SEMANTIC = 0x01,
FETCH_TYPE_mask = 0x03 << 5,
FETCH_TYPE_shift = 5,
SQ_VTX_FETCH_VERTEX_DATA = 0x00,
SQ_VTX_FETCH_INSTANCE_DATA = 0x01,
SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02,
FETCH_WHOLE_QUAD_bit = 1 << 7,
BUFFER_ID_mask = 0xff << 8,
BUFFER_ID_shift = 8,
SRC_GPR_mask = 0x7f << 16,
SRC_GPR_shift = 16,
SRC_REL_bit = 1 << 23,
SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24,
SQ_VTX_WORD0__SRC_SEL_X_shift = 24,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
MEGA_FETCH_COUNT_mask = 0x3f << 26,
MEGA_FETCH_COUNT_shift = 26,
SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc,
SEL_X_mask = 0x07 << 0,
SEL_X_shift = 0,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SEL_Y_mask = 0x07 << 3,
SEL_Y_shift = 3,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SEL_Z_mask = 0x07 << 6,
SEL_Z_shift = 6,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SEL_W_mask = 0x07 << 9,
SEL_W_shift = 9,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_ALU_WORD1 = 0x00008dfc,
ENCODING_mask = 0x07 << 15,
ENCODING_shift = 15,
BANK_SWIZZLE_mask = 0x07 << 18,
BANK_SWIZZLE_shift = 18,
SQ_ALU_VEC_012 = 0x00,
SQ_ALU_VEC_021 = 0x01,
SQ_ALU_VEC_120 = 0x02,
SQ_ALU_VEC_102 = 0x03,
SQ_ALU_VEC_201 = 0x04,
SQ_ALU_VEC_210 = 0x05,
SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21,
SQ_ALU_WORD1__DST_GPR_shift = 21,
SQ_ALU_WORD1__DST_REL_bit = 1 << 28,
DST_CHAN_mask = 0x03 << 29,
DST_CHAN_shift = 29,
CHAN_X = 0x00,
CHAN_Y = 0x01,
CHAN_Z = 0x02,
CHAN_W = 0x03,
SQ_ALU_WORD1__CLAMP_bit = 1 << 31,
SQ_CF_ALU_WORD0 = 0x00008dfc,
SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0,
SQ_CF_ALU_WORD0__ADDR_shift = 0,
KCACHE_BANK0_mask = 0x0f << 22,
KCACHE_BANK0_shift = 22,
KCACHE_BANK1_mask = 0x0f << 26,
KCACHE_BANK1_shift = 26,
KCACHE_MODE0_mask = 0x03 << 30,
KCACHE_MODE0_shift = 30,
/* SQ_CF_KCACHE_NOP = 0x00, */
/* SQ_CF_KCACHE_LOCK_1 = 0x01, */
/* SQ_CF_KCACHE_LOCK_2 = 0x02, */
/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */
SQ_VTX_WORD2 = 0x00008dfc,
SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0,
SQ_VTX_WORD2__OFFSET_shift = 0,
SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16,
SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16,
SQ_ENDIAN_NONE = 0x00,
SQ_ENDIAN_8IN16 = 0x01,
SQ_ENDIAN_8IN32 = 0x02,
CONST_BUF_NO_STRIDE_bit = 1 << 18,
MEGA_FETCH_bit = 1 << 19,
SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
SRC0_ABS_bit = 1 << 0,
SRC1_ABS_bit = 1 << 1,
UPDATE_EXECUTE_MASK_bit = 1 << 2,
UPDATE_PRED_bit = 1 << 3,
WRITE_MASK_bit = 1 << 4,
SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5,
SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5,
SQ_ALU_OMOD_OFF = 0x00,
SQ_ALU_OMOD_M2 = 0x01,
SQ_ALU_OMOD_M4 = 0x02,
SQ_ALU_OMOD_D2 = 0x03,
SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
SQ_OP2_INST_ADD = 0x00,
SQ_OP2_INST_MUL = 0x01,
SQ_OP2_INST_MUL_IEEE = 0x02,
SQ_OP2_INST_MAX = 0x03,
SQ_OP2_INST_MIN = 0x04,
SQ_OP2_INST_MAX_DX10 = 0x05,
SQ_OP2_INST_MIN_DX10 = 0x06,
SQ_OP2_INST_SETE = 0x08,
SQ_OP2_INST_SETGT = 0x09,
SQ_OP2_INST_SETGE = 0x0a,
SQ_OP2_INST_SETNE = 0x0b,
SQ_OP2_INST_SETE_DX10 = 0x0c,
SQ_OP2_INST_SETGT_DX10 = 0x0d,
SQ_OP2_INST_SETGE_DX10 = 0x0e,
SQ_OP2_INST_SETNE_DX10 = 0x0f,
SQ_OP2_INST_FRACT = 0x10,
SQ_OP2_INST_TRUNC = 0x11,
SQ_OP2_INST_CEIL = 0x12,
SQ_OP2_INST_RNDNE = 0x13,
SQ_OP2_INST_FLOOR = 0x14,
SQ_OP2_INST_MOVA = 0x15,
SQ_OP2_INST_MOVA_FLOOR = 0x16,
SQ_OP2_INST_MOVA_INT = 0x18,
SQ_OP2_INST_MOV = 0x19,
SQ_OP2_INST_NOP = 0x1a,
SQ_OP2_INST_PRED_SETGT_UINT = 0x1e,
SQ_OP2_INST_PRED_SETGE_UINT = 0x1f,
SQ_OP2_INST_PRED_SETE = 0x20,
SQ_OP2_INST_PRED_SETGT = 0x21,
SQ_OP2_INST_PRED_SETGE = 0x22,
SQ_OP2_INST_PRED_SETNE = 0x23,
SQ_OP2_INST_PRED_SET_INV = 0x24,
SQ_OP2_INST_PRED_SET_POP = 0x25,
SQ_OP2_INST_PRED_SET_CLR = 0x26,
SQ_OP2_INST_PRED_SET_RESTORE = 0x27,
SQ_OP2_INST_PRED_SETE_PUSH = 0x28,
SQ_OP2_INST_PRED_SETGT_PUSH = 0x29,
SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a,
SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b,
SQ_OP2_INST_KILLE = 0x2c,
SQ_OP2_INST_KILLGT = 0x2d,
SQ_OP2_INST_KILLGE = 0x2e,
SQ_OP2_INST_KILLNE = 0x2f,
SQ_OP2_INST_AND_INT = 0x30,
SQ_OP2_INST_OR_INT = 0x31,
SQ_OP2_INST_XOR_INT = 0x32,
SQ_OP2_INST_NOT_INT = 0x33,
SQ_OP2_INST_ADD_INT = 0x34,
SQ_OP2_INST_SUB_INT = 0x35,
SQ_OP2_INST_MAX_INT = 0x36,
SQ_OP2_INST_MIN_INT = 0x37,
SQ_OP2_INST_MAX_UINT = 0x38,
SQ_OP2_INST_MIN_UINT = 0x39,
SQ_OP2_INST_SETE_INT = 0x3a,
SQ_OP2_INST_SETGT_INT = 0x3b,
SQ_OP2_INST_SETGE_INT = 0x3c,
SQ_OP2_INST_SETNE_INT = 0x3d,
SQ_OP2_INST_SETGT_UINT = 0x3e,
SQ_OP2_INST_SETGE_UINT = 0x3f,
SQ_OP2_INST_KILLGT_UINT = 0x40,
SQ_OP2_INST_KILLGE_UINT = 0x41,
SQ_OP2_INST_PRED_SETE_INT = 0x42,
SQ_OP2_INST_PRED_SETGT_INT = 0x43,
SQ_OP2_INST_PRED_SETGE_INT = 0x44,
SQ_OP2_INST_PRED_SETNE_INT = 0x45,
SQ_OP2_INST_KILLE_INT = 0x46,
SQ_OP2_INST_KILLGT_INT = 0x47,
SQ_OP2_INST_KILLGE_INT = 0x48,
SQ_OP2_INST_KILLNE_INT = 0x49,
SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a,
SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b,
SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c,
SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d,
SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e,
SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f,
SQ_OP2_INST_DOT4 = 0x50,
SQ_OP2_INST_DOT4_IEEE = 0x51,
SQ_OP2_INST_CUBE = 0x52,
SQ_OP2_INST_MAX4 = 0x53,
SQ_OP2_INST_MOVA_GPR_INT = 0x60,
SQ_OP2_INST_EXP_IEEE = 0x61,
SQ_OP2_INST_LOG_CLAMPED = 0x62,
SQ_OP2_INST_LOG_IEEE = 0x63,
SQ_OP2_INST_RECIP_CLAMPED = 0x64,
SQ_OP2_INST_RECIP_FF = 0x65,
SQ_OP2_INST_RECIP_IEEE = 0x66,
SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67,
SQ_OP2_INST_RECIPSQRT_FF = 0x68,
SQ_OP2_INST_RECIPSQRT_IEEE = 0x69,
SQ_OP2_INST_SQRT_IEEE = 0x6a,
SQ_OP2_INST_FLT_TO_INT = 0x6b,
SQ_OP2_INST_INT_TO_FLT = 0x6c,
SQ_OP2_INST_UINT_TO_FLT = 0x6d,
SQ_OP2_INST_SIN = 0x6e,
SQ_OP2_INST_COS = 0x6f,
SQ_OP2_INST_ASHR_INT = 0x70,
SQ_OP2_INST_LSHR_INT = 0x71,
SQ_OP2_INST_LSHL_INT = 0x72,
SQ_OP2_INST_MULLO_INT = 0x73,
SQ_OP2_INST_MULHI_INT = 0x74,
SQ_OP2_INST_MULLO_UINT = 0x75,
SQ_OP2_INST_MULHI_UINT = 0x76,
SQ_OP2_INST_RECIP_INT = 0x77,
SQ_OP2_INST_RECIP_UINT = 0x78,
SQ_OP2_INST_FLT_TO_UINT = 0x79,
SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc,
ARRAY_SIZE_mask = 0xfff << 0,
ARRAY_SIZE_shift = 0,
COMP_MASK_mask = 0x0f << 12,
COMP_MASK_shift = 12,
SQ_CF_WORD0 = 0x00008dfc,
SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
ARRAY_BASE_mask = 0x1fff << 0,
ARRAY_BASE_shift = 0,
SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13,
SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,
SQ_EXPORT_PIXEL = 0x00,
SQ_EXPORT_POS = 0x01,
SQ_EXPORT_PARAM = 0x02,
X_UNUSED_FOR_SX_EXPORTS = 0x03,
RW_GPR_mask = 0x7f << 15,
RW_GPR_shift = 15,
RW_REL_bit = 1 << 22,
INDEX_GPR_mask = 0x7f << 23,
INDEX_GPR_shift = 23,
ELEM_SIZE_mask = 0x03 << 30,
ELEM_SIZE_shift = 30,
SQ_VTX_WORD1 = 0x00008dfc,
SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9,
SQ_VTX_WORD1__DST_SEL_X_shift = 9,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
SQ_VTX_WORD1__DST_SEL_Y_shift = 12,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
SQ_VTX_WORD1__DST_SEL_Z_shift = 15,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18,
SQ_VTX_WORD1__DST_SEL_W_shift = 18,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
/* SQ_SEL_MASK = 0x07, */
USE_CONST_FIELDS_bit = 1 << 21,
SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22,
SQ_VTX_WORD1__DATA_FORMAT_shift = 22,
SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28,
SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28,
SQ_NUM_FORMAT_NORM = 0x00,
SQ_NUM_FORMAT_INT = 0x01,
SQ_NUM_FORMAT_SCALED = 0x02,
SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30,
SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31,
SQ_ALU_WORD1_OP2 = 0x00008dfc,
/* SRC0_ABS_bit = 1 << 0, */
/* SRC1_ABS_bit = 1 << 1, */
/* UPDATE_EXECUTE_MASK_bit = 1 << 2, */
/* UPDATE_PRED_bit = 1 << 3, */
/* WRITE_MASK_bit = 1 << 4, */
FOG_MERGE_bit = 1 << 5,
SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6,
SQ_ALU_WORD1_OP2__OMOD_shift = 6,
/* SQ_ALU_OMOD_OFF = 0x00, */
/* SQ_ALU_OMOD_M2 = 0x01, */
/* SQ_ALU_OMOD_M4 = 0x02, */
/* SQ_ALU_OMOD_D2 = 0x03, */
SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
/* SQ_OP2_INST_ADD = 0x00, */
/* SQ_OP2_INST_MUL = 0x01, */
/* SQ_OP2_INST_MUL_IEEE = 0x02, */
/* SQ_OP2_INST_MAX = 0x03, */
/* SQ_OP2_INST_MIN = 0x04, */
/* SQ_OP2_INST_MAX_DX10 = 0x05, */
/* SQ_OP2_INST_MIN_DX10 = 0x06, */
/* SQ_OP2_INST_SETE = 0x08, */
/* SQ_OP2_INST_SETGT = 0x09, */
/* SQ_OP2_INST_SETGE = 0x0a, */
/* SQ_OP2_INST_SETNE = 0x0b, */
/* SQ_OP2_INST_SETE_DX10 = 0x0c, */
/* SQ_OP2_INST_SETGT_DX10 = 0x0d, */
/* SQ_OP2_INST_SETGE_DX10 = 0x0e, */
/* SQ_OP2_INST_SETNE_DX10 = 0x0f, */
/* SQ_OP2_INST_FRACT = 0x10, */
/* SQ_OP2_INST_TRUNC = 0x11, */
/* SQ_OP2_INST_CEIL = 0x12, */
/* SQ_OP2_INST_RNDNE = 0x13, */
/* SQ_OP2_INST_FLOOR = 0x14, */
/* SQ_OP2_INST_MOVA = 0x15, */
/* SQ_OP2_INST_MOVA_FLOOR = 0x16, */
/* SQ_OP2_INST_MOVA_INT = 0x18, */
/* SQ_OP2_INST_MOV = 0x19, */
/* SQ_OP2_INST_NOP = 0x1a, */
/* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */
/* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */
/* SQ_OP2_INST_PRED_SETE = 0x20, */
/* SQ_OP2_INST_PRED_SETGT = 0x21, */
/* SQ_OP2_INST_PRED_SETGE = 0x22, */
/* SQ_OP2_INST_PRED_SETNE = 0x23, */
/* SQ_OP2_INST_PRED_SET_INV = 0x24, */
/* SQ_OP2_INST_PRED_SET_POP = 0x25, */
/* SQ_OP2_INST_PRED_SET_CLR = 0x26, */
/* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */
/* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */
/* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */
/* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */
/* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */
/* SQ_OP2_INST_KILLE = 0x2c, */
/* SQ_OP2_INST_KILLGT = 0x2d, */
/* SQ_OP2_INST_KILLGE = 0x2e, */
/* SQ_OP2_INST_KILLNE = 0x2f, */
/* SQ_OP2_INST_AND_INT = 0x30, */
/* SQ_OP2_INST_OR_INT = 0x31, */
/* SQ_OP2_INST_XOR_INT = 0x32, */
/* SQ_OP2_INST_NOT_INT = 0x33, */
/* SQ_OP2_INST_ADD_INT = 0x34, */
/* SQ_OP2_INST_SUB_INT = 0x35, */
/* SQ_OP2_INST_MAX_INT = 0x36, */
/* SQ_OP2_INST_MIN_INT = 0x37, */
/* SQ_OP2_INST_MAX_UINT = 0x38, */
/* SQ_OP2_INST_MIN_UINT = 0x39, */
/* SQ_OP2_INST_SETE_INT = 0x3a, */
/* SQ_OP2_INST_SETGT_INT = 0x3b, */
/* SQ_OP2_INST_SETGE_INT = 0x3c, */
/* SQ_OP2_INST_SETNE_INT = 0x3d, */
/* SQ_OP2_INST_SETGT_UINT = 0x3e, */
/* SQ_OP2_INST_SETGE_UINT = 0x3f, */
/* SQ_OP2_INST_KILLGT_UINT = 0x40, */
/* SQ_OP2_INST_KILLGE_UINT = 0x41, */
/* SQ_OP2_INST_PRED_SETE_INT = 0x42, */
/* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */
/* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */
/* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */
/* SQ_OP2_INST_KILLE_INT = 0x46, */
/* SQ_OP2_INST_KILLGT_INT = 0x47, */
/* SQ_OP2_INST_KILLGE_INT = 0x48, */
/* SQ_OP2_INST_KILLNE_INT = 0x49, */
/* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */
/* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */
/* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */
/* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */
/* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */
/* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */
/* SQ_OP2_INST_DOT4 = 0x50, */
/* SQ_OP2_INST_DOT4_IEEE = 0x51, */
/* SQ_OP2_INST_CUBE = 0x52, */
/* SQ_OP2_INST_MAX4 = 0x53, */
/* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */
/* SQ_OP2_INST_EXP_IEEE = 0x61, */
/* SQ_OP2_INST_LOG_CLAMPED = 0x62, */
/* SQ_OP2_INST_LOG_IEEE = 0x63, */
/* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */
/* SQ_OP2_INST_RECIP_FF = 0x65, */
/* SQ_OP2_INST_RECIP_IEEE = 0x66, */
/* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */
/* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */
/* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */
/* SQ_OP2_INST_SQRT_IEEE = 0x6a, */
/* SQ_OP2_INST_FLT_TO_INT = 0x6b, */
/* SQ_OP2_INST_INT_TO_FLT = 0x6c, */
/* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */
/* SQ_OP2_INST_SIN = 0x6e, */
/* SQ_OP2_INST_COS = 0x6f, */
/* SQ_OP2_INST_ASHR_INT = 0x70, */
/* SQ_OP2_INST_LSHR_INT = 0x71, */
/* SQ_OP2_INST_LSHL_INT = 0x72, */
/* SQ_OP2_INST_MULLO_INT = 0x73, */
/* SQ_OP2_INST_MULHI_INT = 0x74, */
/* SQ_OP2_INST_MULLO_UINT = 0x75, */
/* SQ_OP2_INST_MULHI_UINT = 0x76, */
/* SQ_OP2_INST_RECIP_INT = 0x77, */
/* SQ_OP2_INST_RECIP_UINT = 0x78, */
/* SQ_OP2_INST_FLT_TO_UINT = 0x79, */
SQ_CF_WORD1 = 0x00008dfc,
POP_COUNT_mask = 0x07 << 0,
POP_COUNT_shift = 0,
CF_CONST_mask = 0x1f << 3,
CF_CONST_shift = 3,
COND_mask = 0x03 << 8,
COND_shift = 8,
SQ_CF_COND_ACTIVE = 0x00,
SQ_CF_COND_FALSE = 0x01,
SQ_CF_COND_BOOL = 0x02,
SQ_CF_COND_NOT_BOOL = 0x03,
SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
SQ_CF_WORD1__COUNT_shift = 10,
CALL_COUNT_mask = 0x3f << 13,
CALL_COUNT_shift = 13,
COUNT_3_bit = 1 << 19,
/* END_OF_PROGRAM_bit = 1 << 21, */
/* VALID_PIXEL_MODE_bit = 1 << 22, */
SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
SQ_CF_WORD1__CF_INST_shift = 23,
SQ_CF_INST_NOP = 0x00,
SQ_CF_INST_TEX = 0x01,
SQ_CF_INST_VTX = 0x02,
SQ_CF_INST_VTX_TC = 0x03,
SQ_CF_INST_LOOP_START = 0x04,
SQ_CF_INST_LOOP_END = 0x05,
SQ_CF_INST_LOOP_START_DX10 = 0x06,
SQ_CF_INST_LOOP_START_NO_AL = 0x07,
SQ_CF_INST_LOOP_CONTINUE = 0x08,
SQ_CF_INST_LOOP_BREAK = 0x09,
SQ_CF_INST_JUMP = 0x0a,
SQ_CF_INST_PUSH = 0x0b,
SQ_CF_INST_PUSH_ELSE = 0x0c,
SQ_CF_INST_ELSE = 0x0d,
SQ_CF_INST_POP = 0x0e,
SQ_CF_INST_POP_JUMP = 0x0f,
SQ_CF_INST_POP_PUSH = 0x10,
SQ_CF_INST_POP_PUSH_ELSE = 0x11,
SQ_CF_INST_CALL = 0x12,
SQ_CF_INST_CALL_FS = 0x13,
SQ_CF_INST_RETURN = 0x14,
SQ_CF_INST_EMIT_VERTEX = 0x15,
SQ_CF_INST_EMIT_CUT_VERTEX = 0x16,
SQ_CF_INST_CUT_VERTEX = 0x17,
SQ_CF_INST_KILL = 0x18,
/* WHOLE_QUAD_MODE_bit = 1 << 30, */
/* BARRIER_bit = 1 << 31, */
SQ_VTX_WORD1_SEM = 0x00008dfc,
SEMANTIC_ID_mask = 0xff << 0,
SEMANTIC_ID_shift = 0,
SQ_TEX_WORD0 = 0x00008dfc,
TEX_INST_mask = 0x1f << 0,
TEX_INST_shift = 0,
SQ_TEX_INST_VTX_FETCH = 0x00,
SQ_TEX_INST_VTX_SEMANTIC = 0x01,
SQ_TEX_INST_LD = 0x03,
SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04,
SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05,
SQ_TEX_INST_GET_LOD = 0x06,
SQ_TEX_INST_GET_GRADIENTS_H = 0x07,
SQ_TEX_INST_GET_GRADIENTS_V = 0x08,
SQ_TEX_INST_GET_LERP = 0x09,
SQ_TEX_INST_RESERVED_10 = 0x0a,
SQ_TEX_INST_SET_GRADIENTS_H = 0x0b,
SQ_TEX_INST_SET_GRADIENTS_V = 0x0c,
SQ_TEX_INST_PASS = 0x0d,
X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e,
SQ_TEX_INST_SAMPLE = 0x10,
SQ_TEX_INST_SAMPLE_L = 0x11,
SQ_TEX_INST_SAMPLE_LB = 0x12,
SQ_TEX_INST_SAMPLE_LZ = 0x13,
SQ_TEX_INST_SAMPLE_G = 0x14,
SQ_TEX_INST_SAMPLE_G_L = 0x15,
SQ_TEX_INST_SAMPLE_G_LB = 0x16,
SQ_TEX_INST_SAMPLE_G_LZ = 0x17,
SQ_TEX_INST_SAMPLE_C = 0x18,
SQ_TEX_INST_SAMPLE_C_L = 0x19,
SQ_TEX_INST_SAMPLE_C_LB = 0x1a,
SQ_TEX_INST_SAMPLE_C_LZ = 0x1b,
SQ_TEX_INST_SAMPLE_C_G = 0x1c,
SQ_TEX_INST_SAMPLE_C_G_L = 0x1d,
SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e,
SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f,
BC_FRAC_MODE_bit = 1 << 5,
/* FETCH_WHOLE_QUAD_bit = 1 << 7, */
RESOURCE_ID_mask = 0xff << 8,
RESOURCE_ID_shift = 8,
/* SRC_GPR_mask = 0x7f << 16, */
/* SRC_GPR_shift = 16, */
/* SRC_REL_bit = 1 << 23, */
SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
SQ_VTX_WORD1_GPR = 0x00008dfc,
SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0,
SQ_VTX_WORD1_GPR__DST_GPR_shift = 0,
SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
SQ_ALU_WORD0 = 0x00008dfc,
SRC0_SEL_mask = 0x1ff << 0,
SRC0_SEL_shift = 0,
/* SQ_ALU_SRC_0 = 0xf8, */
/* SQ_ALU_SRC_1 = 0xf9, */
/* SQ_ALU_SRC_1_INT = 0xfa, */
/* SQ_ALU_SRC_M_1_INT = 0xfb, */
/* SQ_ALU_SRC_0_5 = 0xfc, */
/* SQ_ALU_SRC_LITERAL = 0xfd, */
/* SQ_ALU_SRC_PV = 0xfe, */
/* SQ_ALU_SRC_PS = 0xff, */
SRC0_REL_bit = 1 << 9,
SRC0_CHAN_mask = 0x03 << 10,
SRC0_CHAN_shift = 10,
/* SQ_CHAN_X = 0x00, */
/* SQ_CHAN_Y = 0x01, */
/* SQ_CHAN_Z = 0x02, */
/* SQ_CHAN_W = 0x03, */
SRC0_NEG_bit = 1 << 12,
SRC1_SEL_mask = 0x1ff << 13,
SRC1_SEL_shift = 13,
/* SQ_ALU_SRC_0 = 0xf8, */
/* SQ_ALU_SRC_1 = 0xf9, */
/* SQ_ALU_SRC_1_INT = 0xfa, */
/* SQ_ALU_SRC_M_1_INT = 0xfb, */
/* SQ_ALU_SRC_0_5 = 0xfc, */
/* SQ_ALU_SRC_LITERAL = 0xfd, */
/* SQ_ALU_SRC_PV = 0xfe, */
/* SQ_ALU_SRC_PS = 0xff, */
SRC1_REL_bit = 1 << 22,
SRC1_CHAN_mask = 0x03 << 23,
SRC1_CHAN_shift = 23,
/* SQ_CHAN_X = 0x00, */
/* SQ_CHAN_Y = 0x01, */
/* SQ_CHAN_Z = 0x02, */
/* SQ_CHAN_W = 0x03, */
SRC1_NEG_bit = 1 << 25,
INDEX_MODE_mask = 0x07 << 26,
INDEX_MODE_shift = 26,
SQ_INDEX_AR_X = 0x00,
SQ_INDEX_AR_Y = 0x01,
SQ_INDEX_AR_Z = 0x02,
SQ_INDEX_AR_W = 0x03,
SQ_INDEX_LOOP = 0x04,
PRED_SEL_mask = 0x03 << 29,
PRED_SEL_shift = 29,
SQ_PRED_SEL_OFF = 0x00,
SQ_PRED_SEL_ZERO = 0x02,
SQ_PRED_SEL_ONE = 0x03,
LAST_bit = 1 << 31,
SX_EXPORT_BUFFER_SIZES = 0x0000900c,
COLOR_BUFFER_SIZE_mask = 0xff << 0,
COLOR_BUFFER_SIZE_shift = 0,
POSITION_BUFFER_SIZE_mask = 0xff << 8,
POSITION_BUFFER_SIZE_shift = 8,
SMX_BUFFER_SIZE_mask = 0xff << 16,
SMX_BUFFER_SIZE_shift = 16,
SX_MEMORY_EXPORT_BASE = 0x00009010,
SX_MEMORY_EXPORT_SIZE = 0x00009014,
SPI_CONFIG_CNTL = 0x00009100,
GPR_WRITE_PRIORITY_mask = 0x1f << 0,
GPR_WRITE_PRIORITY_shift = 0,
X_PRIORITY_ORDER = 0x00,
X_PRIORITY_ORDER_VS = 0x01,
DISABLE_INTERP_1_bit = 1 << 5,
DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6,
DEBUG_THREAD_TYPE_SEL_shift = 6,
DEBUG_GROUP_SEL_mask = 0x1f << 8,
DEBUG_GROUP_SEL_shift = 8,
DEBUG_GRBM_OVERRIDE_bit = 1 << 13,
SPI_CONFIG_CNTL_1 = 0x0000913c,
VTX_DONE_DELAY_mask = 0x0f << 0,
VTX_DONE_DELAY_shift = 0,
X_DELAY_10_CLKS = 0x00,
X_DELAY_11_CLKS = 0x01,
X_DELAY_12_CLKS = 0x02,
X_DELAY_13_CLKS = 0x03,
X_DELAY_14_CLKS = 0x04,
X_DELAY_15_CLKS = 0x05,
X_DELAY_16_CLKS = 0x06,
X_DELAY_17_CLKS = 0x07,
X_DELAY_2_CLKS = 0x08,
X_DELAY_3_CLKS = 0x09,
X_DELAY_4_CLKS = 0x0a,
X_DELAY_5_CLKS = 0x0b,
X_DELAY_6_CLKS = 0x0c,
X_DELAY_7_CLKS = 0x0d,
X_DELAY_8_CLKS = 0x0e,
X_DELAY_9_CLKS = 0x0f,
INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4,
TD_FILTER4 = 0x00009400,
WEIGHT_1_mask = 0x7ff << 0,
WEIGHT_1_shift = 0,
WEIGHT_0_mask = 0x7ff << 11,
WEIGHT_0_shift = 11,
WEIGHT_PAIR_bit = 1 << 22,
PHASE_mask = 0x0f << 23,
PHASE_shift = 23,
DIRECTION_bit = 1 << 27,
TD_FILTER4_1 = 0x00009404,
TD_FILTER4_1_num = 35,
/* WEIGHT_1_mask = 0x7ff << 0, */
/* WEIGHT_1_shift = 0, */
/* WEIGHT_0_mask = 0x7ff << 11, */
/* WEIGHT_0_shift = 11, */
TD_CNTL = 0x00009490,
SYNC_PHASE_SH_mask = 0x03 << 0,
SYNC_PHASE_SH_shift = 0,
SYNC_PHASE_VC_SMX_mask = 0x03 << 4,
SYNC_PHASE_VC_SMX_shift = 4,
TD0_CNTL = 0x00009494,
TD0_CNTL_num = 4,
ID_OVERRIDE_mask = 0x03 << 28,
ID_OVERRIDE_shift = 28,
TD0_STATUS = 0x000094a4,
TD0_STATUS_num = 4,
BUSY_bit = 1 << 31,
TA_CNTL = 0x00009504,
GRADIENT_CREDIT_mask = 0x1f << 0,
GRADIENT_CREDIT_shift = 0,
WALKER_CREDIT_mask = 0x1f << 8,
WALKER_CREDIT_shift = 8,
ALIGNER_CREDIT_mask = 0x1f << 16,
ALIGNER_CREDIT_shift = 16,
TD_FIFO_CREDIT_mask = 0x3ff << 22,
TD_FIFO_CREDIT_shift = 22,
TA_CNTL_AUX = 0x00009508,
DISABLE_CUBE_WRAP_bit = 1 << 0,
SYNC_GRADIENT_bit = 1 << 24,
SYNC_WALKER_bit = 1 << 25,
SYNC_ALIGNER_bit = 1 << 26,
BILINEAR_PRECISION_bit = 1 << 31,
TA0_CNTL = 0x00009510,
/* ID_OVERRIDE_mask = 0x03 << 28, */
/* ID_OVERRIDE_shift = 28, */
TA1_CNTL = 0x00009514,
/* ID_OVERRIDE_mask = 0x03 << 28, */
/* ID_OVERRIDE_shift = 28, */
TA2_CNTL = 0x00009518,
/* ID_OVERRIDE_mask = 0x03 << 28, */
/* ID_OVERRIDE_shift = 28, */
TA3_CNTL = 0x0000951c,
/* ID_OVERRIDE_mask = 0x03 << 28, */
/* ID_OVERRIDE_shift = 28, */
TA0_STATUS = 0x00009520,
FG_PFIFO_EMPTYB_bit = 1 << 12,
FG_LFIFO_EMPTYB_bit = 1 << 13,
FG_SFIFO_EMPTYB_bit = 1 << 14,
FL_PFIFO_EMPTYB_bit = 1 << 16,
FL_LFIFO_EMPTYB_bit = 1 << 17,
FL_SFIFO_EMPTYB_bit = 1 << 18,
FA_PFIFO_EMPTYB_bit = 1 << 20,
FA_LFIFO_EMPTYB_bit = 1 << 21,
FA_SFIFO_EMPTYB_bit = 1 << 22,
IN_BUSY_bit = 1 << 24,
FG_BUSY_bit = 1 << 25,
FL_BUSY_bit = 1 << 27,
TA_BUSY_bit = 1 << 28,
FA_BUSY_bit = 1 << 29,
AL_BUSY_bit = 1 << 30,
/* BUSY_bit = 1 << 31, */
TA1_STATUS = 0x00009524,
/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
/* IN_BUSY_bit = 1 << 24, */
/* FG_BUSY_bit = 1 << 25, */
/* FL_BUSY_bit = 1 << 27, */
/* TA_BUSY_bit = 1 << 28, */
/* FA_BUSY_bit = 1 << 29, */
/* AL_BUSY_bit = 1 << 30, */
/* BUSY_bit = 1 << 31, */
TA2_STATUS = 0x00009528,
/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
/* IN_BUSY_bit = 1 << 24, */
/* FG_BUSY_bit = 1 << 25, */
/* FL_BUSY_bit = 1 << 27, */
/* TA_BUSY_bit = 1 << 28, */
/* FA_BUSY_bit = 1 << 29, */
/* AL_BUSY_bit = 1 << 30, */
/* BUSY_bit = 1 << 31, */
TA3_STATUS = 0x0000952c,
/* FG_PFIFO_EMPTYB_bit = 1 << 12, */
/* FG_LFIFO_EMPTYB_bit = 1 << 13, */
/* FG_SFIFO_EMPTYB_bit = 1 << 14, */
/* FL_PFIFO_EMPTYB_bit = 1 << 16, */
/* FL_LFIFO_EMPTYB_bit = 1 << 17, */
/* FL_SFIFO_EMPTYB_bit = 1 << 18, */
/* FA_PFIFO_EMPTYB_bit = 1 << 20, */
/* FA_LFIFO_EMPTYB_bit = 1 << 21, */
/* FA_SFIFO_EMPTYB_bit = 1 << 22, */
/* IN_BUSY_bit = 1 << 24, */
/* FG_BUSY_bit = 1 << 25, */
/* FL_BUSY_bit = 1 << 27, */
/* TA_BUSY_bit = 1 << 28, */
/* FA_BUSY_bit = 1 << 29, */
/* AL_BUSY_bit = 1 << 30, */
/* BUSY_bit = 1 << 31, */
TC_STATUS = 0x00009600,
TC_BUSY_bit = 1 << 0,
TC_INVALIDATE = 0x00009604,
START_bit = 1 << 0,
TC_CNTL = 0x00009608,
FORCE_HIT_bit = 1 << 0,
FORCE_MISS_bit = 1 << 1,
L2_SIZE_mask = 0x0f << 5,
L2_SIZE_shift = 5,
_256K = 0x00,
_224K = 0x01,
_192K = 0x02,
_160K = 0x03,
_128K = 0x04,
_96K = 0x05,
_64K = 0x06,
_32K = 0x07,
L2_DISABLE_LATE_HIT_bit = 1 << 9,
DISABLE_VERT_PERF_bit = 1 << 10,
DISABLE_INVAL_BUSY_bit = 1 << 11,
DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12,
PARTITION_MODE_mask = 0x03 << 13,
PARTITION_MODE_shift = 13,
X_VERTEX = 0x00,
MISS_ARB_MODE_bit = 1 << 15,
HIT_ARB_MODE_bit = 1 << 16,
DISABLE_WRITE_DELAY_bit = 1 << 17,
HIT_FIFO_DEPTH_bit = 1 << 18,
VC_CNTL = 0x00009700,
L2_INVALIDATE_bit = 1 << 0,
RESERVED_bit = 1 << 1,
CC_FORCE_MISS_bit = 1 << 2,
MI_CHAN_SEL_mask = 0x03 << 3,
MI_CHAN_SEL_shift = 3,
X_MC0_USES_CH_0_1 = 0x00,
X_MC0_USES_CH_0_3 = 0x01,
X_VC_MC0_IS_ACTIVE = 0x02,
X_VC_MC1_IS_DISABLED = 0x03,
MI_STEER_DISABLE_bit = 1 << 5,
MI_CREDIT_CTR_mask = 0x0f << 6,
MI_CREDIT_CTR_shift = 6,
MI_CREDIT_WE_bit = 1 << 10,
MI_REQ_STALL_THLD_mask = 0x07 << 11,
MI_REQ_STALL_THLD_shift = 11,
X_LATENCY_EXCEEDS_399_CLOCKS = 0x00,
X_LATENCY_EXCEEDS_415_CLOCKS = 0x01,
X_LATENCY_EXCEEDS_431_CLOCKS = 0x02,
X_LATENCY_EXCEEDS_447_CLOCKS = 0x03,
X_LATENCY_EXCEEDS_463_CLOCKS = 0x04,
X_LATENCY_EXCEEDS_479_CLOCKS = 0x05,
X_LATENCY_EXCEEDS_495_CLOCKS = 0x06,
X_LATENCY_EXCEEDS_511_CLOCKS = 0x07,
VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14,
VC_CNTL__MI_TIMESTAMP_RES_shift = 14,
X_1X_SYSTEM_CLOCK = 0x00,
X_2X_SYSTEM_CLOCK = 0x01,
X_4X_SYSTEM_CLOCK = 0x02,
X_8X_SYSTEM_CLOCK = 0x03,
X_16X_SYSTEM_CLOCK = 0x04,
X_32X_SYSTEM_CLOCK = 0x05,
X_64X_SYSTEM_CLOCK = 0x06,
X_128X_SYSTEM_CLOCK = 0x07,
X_256X_SYSTEM_CLOCK = 0x08,
X_512X_SYSTEM_CLOCK = 0x09,
X_1024X_SYSTEM_CLOCK = 0x0a,
X_2048X_SYSTEM_CLOCK = 0x0b,
X_4092X_SYSTEM_CLOCK = 0x0c,
X_8192X_SYSTEM_CLOCK = 0x0d,
X_16384X_SYSTEM_CLOCK = 0x0e,
X_32768X_SYSTEM_CLOCK = 0x0f,
VC_CNTL_STATUS = 0x00009704,
RP_BUSY_bit = 1 << 0,
RG_BUSY_bit = 1 << 1,
VC_BUSY_bit = 1 << 2,
CLAMP_DETECT_bit = 1 << 3,
VC_CONFIG = 0x00009718,
WRITE_DIS_bit = 1 << 0,
GPR_DATA_PHASE_ADJ_mask = 0x07 << 1,
GPR_DATA_PHASE_ADJ_shift = 1,
X_LATENCY_BASE_0_CYCLES = 0x00,
X_LATENCY_BASE_1_CYCLES = 0x01,
X_LATENCY_BASE_2_CYCLES = 0x02,
X_LATENCY_BASE_3_CYCLES = 0x03,
TD_SIMD_SYNC_ADJ_mask = 0x07 << 4,
TD_SIMD_SYNC_ADJ_shift = 4,
X_0_CYCLES_DELAY = 0x00,
X_1_CYCLES_DELAY = 0x01,
X_2_CYCLES_DELAY = 0x02,
X_3_CYCLES_DELAY = 0x03,
X_4_CYCLES_DELAY = 0x04,
X_5_CYCLES_DELAY = 0x05,
X_6_CYCLES_DELAY = 0x06,
X_7_CYCLES_DELAY = 0x07,
SMX_DC_CTL0 = 0x0000a020,
WR_GATHER_STREAM0_bit = 1 << 0,
WR_GATHER_STREAM1_bit = 1 << 1,
WR_GATHER_STREAM2_bit = 1 << 2,
WR_GATHER_STREAM3_bit = 1 << 3,
WR_GATHER_SCRATCH_bit = 1 << 4,
WR_GATHER_REDUC_BUF_bit = 1 << 5,
WR_GATHER_RING_BUF_bit = 1 << 6,
WR_GATHER_F_BUF_bit = 1 << 7,
DISABLE_CACHES_bit = 1 << 8,
AUTO_FLUSH_INVAL_EN_bit = 1 << 10,
AUTO_FLUSH_EN_bit = 1 << 11,
AUTO_FLUSH_CNT_mask = 0xffff << 12,
AUTO_FLUSH_CNT_shift = 12,
MC_RD_STALL_FACTOR_mask = 0x03 << 28,
MC_RD_STALL_FACTOR_shift = 28,
MC_WR_STALL_FACTOR_mask = 0x03 << 30,
MC_WR_STALL_FACTOR_shift = 30,
SMX_DC_CTL1 = 0x0000a024,
OP_FIFO_SKID_mask = 0x7f << 0,
OP_FIFO_SKID_shift = 0,
CACHE_LINE_SIZE_bit = 1 << 8,
MULTI_FLUSH_MODE_bit = 1 << 9,
MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10,
MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10,
DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16,
DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17,
DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18,
DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19,
SMX_DC_CTL2 = 0x0000a028,
INVALIDATE_CACHES_bit = 1 << 0,
CACHES_INVALID_bit = 1 << 1,
CACHES_DIRTY_bit = 1 << 2,
FLUSH_ALL_bit = 1 << 4,
FLUSH_GS_THREADS_bit = 1 << 8,
FLUSH_ES_THREADS_bit = 1 << 9,
SMX_DC_MC_INTF_CTL = 0x0000a02c,
MC_RD_REQ_CRED_mask = 0xff << 0,
MC_RD_REQ_CRED_shift = 0,
MC_WR_REQ_CRED_mask = 0xff << 16,
MC_WR_REQ_CRED_shift = 16,
TD_PS_SAMPLER0_BORDER_RED = 0x0000a400,
TD_PS_SAMPLER0_BORDER_RED_num = 18,
TD_PS_SAMPLER0_BORDER_RED_offset = 16,
TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404,
TD_PS_SAMPLER0_BORDER_GREEN_num = 18,
TD_PS_SAMPLER0_BORDER_GREEN_offset = 16,
TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408,
TD_PS_SAMPLER0_BORDER_BLUE_num = 18,
TD_PS_SAMPLER0_BORDER_BLUE_offset = 16,
TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c,
TD_PS_SAMPLER0_BORDER_ALPHA_num = 18,
TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16,
TD_VS_SAMPLER0_BORDER_RED = 0x0000a600,
TD_VS_SAMPLER0_BORDER_RED_num = 18,
TD_VS_SAMPLER0_BORDER_RED_offset = 16,
TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604,
TD_VS_SAMPLER0_BORDER_GREEN_num = 18,
TD_VS_SAMPLER0_BORDER_GREEN_offset = 16,
TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608,
TD_VS_SAMPLER0_BORDER_BLUE_num = 18,
TD_VS_SAMPLER0_BORDER_BLUE_offset = 16,
TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c,
TD_VS_SAMPLER0_BORDER_ALPHA_num = 18,
TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16,
TD_GS_SAMPLER0_BORDER_RED = 0x0000a800,
TD_GS_SAMPLER0_BORDER_RED_num = 18,
TD_GS_SAMPLER0_BORDER_RED_offset = 16,
TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804,
TD_GS_SAMPLER0_BORDER_GREEN_num = 18,
TD_GS_SAMPLER0_BORDER_GREEN_offset = 16,
TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808,
TD_GS_SAMPLER0_BORDER_BLUE_num = 18,
TD_GS_SAMPLER0_BORDER_BLUE_offset = 16,
TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c,
TD_GS_SAMPLER0_BORDER_ALPHA_num = 18,
TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3,
TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3,
DB_DEPTH_SIZE = 0x00028000,
PITCH_TILE_MAX_mask = 0x3ff << 0,
PITCH_TILE_MAX_shift = 0,
SLICE_TILE_MAX_mask = 0xfffff << 10,
SLICE_TILE_MAX_shift = 10,
DB_DEPTH_VIEW = 0x00028004,
SLICE_START_mask = 0x7ff << 0,
SLICE_START_shift = 0,
SLICE_MAX_mask = 0x7ff << 13,
SLICE_MAX_shift = 13,
DB_DEPTH_BASE = 0x0002800c,
DB_DEPTH_INFO = 0x00028010,
DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0,
DB_DEPTH_INFO__FORMAT_shift = 0,
DEPTH_INVALID = 0x00,
DEPTH_16 = 0x01,
DEPTH_X8_24 = 0x02,
DEPTH_8_24 = 0x03,
DEPTH_X8_24_FLOAT = 0x04,
DEPTH_8_24_FLOAT = 0x05,
DEPTH_32_FLOAT = 0x06,
DEPTH_X24_8_32_FLOAT = 0x07,
DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3,
DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15,
DB_DEPTH_INFO__ARRAY_MODE_shift = 15,
ARRAY_2D_TILED_THIN1 = 0x04,
TILE_SURFACE_ENABLE_bit = 1 << 25,
TILE_COMPACT_bit = 1 << 26,
ZRANGE_PRECISION_bit = 1 << 31,
DB_HTILE_DATA_BASE = 0x00028014,
DB_STENCIL_CLEAR = 0x00028028,
DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0,
DB_STENCIL_CLEAR__CLEAR_shift = 0,
MIN_mask = 0xff << 16,
MIN_shift = 16,
DB_DEPTH_CLEAR = 0x0002802c,
PA_SC_SCREEN_SCISSOR_TL = 0x00028030,
PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0,
PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16,
PA_SC_SCREEN_SCISSOR_BR = 0x00028034,
PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0,
PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16,
CB_COLOR0_BASE = 0x00028040,
CB_COLOR0_BASE_num = 8,
CB_COLOR0_SIZE = 0x00028060,
CB_COLOR0_SIZE_num = 8,
/* PITCH_TILE_MAX_mask = 0x3ff << 0, */
/* PITCH_TILE_MAX_shift = 0, */
/* SLICE_TILE_MAX_mask = 0xfffff << 10, */
/* SLICE_TILE_MAX_shift = 10, */
CB_COLOR0_VIEW = 0x00028080,
CB_COLOR0_VIEW_num = 8,
/* SLICE_START_mask = 0x7ff << 0, */
/* SLICE_START_shift = 0, */
/* SLICE_MAX_mask = 0x7ff << 13, */
/* SLICE_MAX_shift = 13, */
CB_COLOR0_INFO = 0x000280a0,
CB_COLOR0_INFO_num = 8,
ENDIAN_mask = 0x03 << 0,
ENDIAN_shift = 0,
ENDIAN_NONE = 0x00,
ENDIAN_8IN16 = 0x01,
ENDIAN_8IN32 = 0x02,
ENDIAN_8IN64 = 0x03,
CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
CB_COLOR0_INFO__FORMAT_shift = 2,
COLOR_INVALID = 0x00,
COLOR_8 = 0x01,
COLOR_4_4 = 0x02,
COLOR_3_3_2 = 0x03,
COLOR_16 = 0x05,
COLOR_16_FLOAT = 0x06,
COLOR_8_8 = 0x07,
COLOR_5_6_5 = 0x08,
COLOR_6_5_5 = 0x09,
COLOR_1_5_5_5 = 0x0a,
COLOR_4_4_4_4 = 0x0b,
COLOR_5_5_5_1 = 0x0c,
COLOR_32 = 0x0d,
COLOR_32_FLOAT = 0x0e,
COLOR_16_16 = 0x0f,
COLOR_16_16_FLOAT = 0x10,
COLOR_8_24 = 0x11,
COLOR_8_24_FLOAT = 0x12,
COLOR_24_8 = 0x13,
COLOR_24_8_FLOAT = 0x14,
COLOR_10_11_11 = 0x15,
COLOR_10_11_11_FLOAT = 0x16,
COLOR_11_11_10 = 0x17,
COLOR_11_11_10_FLOAT = 0x18,
COLOR_2_10_10_10 = 0x19,
COLOR_8_8_8_8 = 0x1a,
COLOR_10_10_10_2 = 0x1b,
COLOR_X24_8_32_FLOAT = 0x1c,
COLOR_32_32 = 0x1d,
COLOR_32_32_FLOAT = 0x1e,
COLOR_16_16_16_16 = 0x1f,
COLOR_16_16_16_16_FLOAT = 0x20,
COLOR_32_32_32_32 = 0x22,
COLOR_32_32_32_32_FLOAT = 0x23,
CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8,
CB_COLOR0_INFO__ARRAY_MODE_shift = 8,
ARRAY_LINEAR_GENERAL = 0x00,
ARRAY_LINEAR_ALIGNED = 0x01,
/* ARRAY_2D_TILED_THIN1 = 0x04, */
NUMBER_TYPE_mask = 0x07 << 12,
NUMBER_TYPE_shift = 12,
NUMBER_UNORM = 0x00,
NUMBER_SNORM = 0x01,
NUMBER_USCALED = 0x02,
NUMBER_SSCALED = 0x03,
NUMBER_UINT = 0x04,
NUMBER_SINT = 0x05,
NUMBER_SRGB = 0x06,
NUMBER_FLOAT = 0x07,
CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15,
COMP_SWAP_mask = 0x03 << 16,
COMP_SWAP_shift = 16,
SWAP_STD = 0x00,
SWAP_ALT = 0x01,
SWAP_STD_REV = 0x02,
SWAP_ALT_REV = 0x03,
CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18,
CB_COLOR0_INFO__TILE_MODE_shift = 18,
TILE_DISABLE = 0x00,
TILE_CLEAR_ENABLE = 0x01,
TILE_FRAG_ENABLE = 0x02,
BLEND_CLAMP_bit = 1 << 20,
CLEAR_COLOR_bit = 1 << 21,
BLEND_BYPASS_bit = 1 << 22,
BLEND_FLOAT32_bit = 1 << 23,
SIMPLE_FLOAT_bit = 1 << 24,
CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25,
/* TILE_COMPACT_bit = 1 << 26, */
SOURCE_FORMAT_bit = 1 << 27,
CB_COLOR0_TILE = 0x000280c0,
CB_COLOR0_TILE_num = 8,
CB_COLOR0_FRAG = 0x000280e0,
CB_COLOR0_FRAG_num = 8,
CB_COLOR0_MASK = 0x00028100,
CB_COLOR0_MASK_num = 8,
CMASK_BLOCK_MAX_mask = 0xfff << 0,
CMASK_BLOCK_MAX_shift = 0,
FMASK_TILE_MAX_mask = 0xfffff << 12,
FMASK_TILE_MAX_shift = 12,
CB_CLEAR_RED = 0x00028120,
CB_CLEAR_GREEN = 0x00028124,
CB_CLEAR_BLUE = 0x00028128,
CB_CLEAR_ALPHA = 0x0002812c,
SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140,
SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16,
SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0,
SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0,
SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180,
SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16,
SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0,
SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0,
SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0,
SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16,
SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0,
SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0,
PA_SC_WINDOW_OFFSET = 0x00028200,
WINDOW_X_OFFSET_mask = 0x7fff << 0,
WINDOW_X_OFFSET_shift = 0,
WINDOW_Y_OFFSET_mask = 0x7fff << 16,
WINDOW_Y_OFFSET_shift = 16,
PA_SC_WINDOW_SCISSOR_TL = 0x00028204,
PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0,
PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16,
WINDOW_OFFSET_DISABLE_bit = 1 << 31,
PA_SC_WINDOW_SCISSOR_BR = 0x00028208,
PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0,
PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16,
PA_SC_CLIPRECT_RULE = 0x0002820c,
CLIP_RULE_mask = 0xffff << 0,
CLIP_RULE_shift = 0,
PA_SC_CLIPRECT_0_TL = 0x00028210,
PA_SC_CLIPRECT_0_TL_num = 4,
PA_SC_CLIPRECT_0_TL_offset = 8,
PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0,
PA_SC_CLIPRECT_0_TL__TL_X_shift = 0,
PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16,
PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16,
PA_SC_CLIPRECT_0_BR = 0x00028214,
PA_SC_CLIPRECT_0_BR_num = 4,
PA_SC_CLIPRECT_0_BR_offset = 8,
PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0,
PA_SC_CLIPRECT_0_BR__BR_X_shift = 0,
PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16,
PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16,
CB_TARGET_MASK = 0x00028238,
TARGET0_ENABLE_mask = 0x0f << 0,
TARGET0_ENABLE_shift = 0,
TARGET1_ENABLE_mask = 0x0f << 4,
TARGET1_ENABLE_shift = 4,
TARGET2_ENABLE_mask = 0x0f << 8,
TARGET2_ENABLE_shift = 8,
TARGET3_ENABLE_mask = 0x0f << 12,
TARGET3_ENABLE_shift = 12,
TARGET4_ENABLE_mask = 0x0f << 16,
TARGET4_ENABLE_shift = 16,
TARGET5_ENABLE_mask = 0x0f << 20,
TARGET5_ENABLE_shift = 20,
TARGET6_ENABLE_mask = 0x0f << 24,
TARGET6_ENABLE_shift = 24,
TARGET7_ENABLE_mask = 0x0f << 28,
TARGET7_ENABLE_shift = 28,
CB_SHADER_MASK = 0x0002823c,
OUTPUT0_ENABLE_mask = 0x0f << 0,
OUTPUT0_ENABLE_shift = 0,
OUTPUT1_ENABLE_mask = 0x0f << 4,
OUTPUT1_ENABLE_shift = 4,
OUTPUT2_ENABLE_mask = 0x0f << 8,
OUTPUT2_ENABLE_shift = 8,
OUTPUT3_ENABLE_mask = 0x0f << 12,
OUTPUT3_ENABLE_shift = 12,
OUTPUT4_ENABLE_mask = 0x0f << 16,
OUTPUT4_ENABLE_shift = 16,
OUTPUT5_ENABLE_mask = 0x0f << 20,
OUTPUT5_ENABLE_shift = 20,
OUTPUT6_ENABLE_mask = 0x0f << 24,
OUTPUT6_ENABLE_shift = 24,
OUTPUT7_ENABLE_mask = 0x0f << 28,
OUTPUT7_ENABLE_shift = 28,
PA_SC_GENERIC_SCISSOR_TL = 0x00028240,
PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0,
PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16,
/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
PA_SC_GENERIC_SCISSOR_BR = 0x00028244,
PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0,
PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16,
PA_SC_VPORT_SCISSOR_0_TL = 0x00028250,
PA_SC_VPORT_SCISSOR_0_TL_num = 16,
PA_SC_VPORT_SCISSOR_0_TL_offset = 8,
PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0,
PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0,
PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16,
PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16,
/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
PA_SC_VPORT_SCISSOR_0_BR = 0x00028254,
PA_SC_VPORT_SCISSOR_0_BR_num = 16,
PA_SC_VPORT_SCISSOR_0_BR_offset = 8,
PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0,
PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0,
PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16,
PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16,
PA_SC_VPORT_ZMIN_0 = 0x000282d0,
PA_SC_VPORT_ZMIN_0_num = 16,
PA_SC_VPORT_ZMIN_0_offset = 8,
PA_SC_VPORT_ZMAX_0 = 0x000282d4,
PA_SC_VPORT_ZMAX_0_num = 16,
PA_SC_VPORT_ZMAX_0_offset = 8,
SX_MISC = 0x00028350,
MULTIPASS_bit = 1 << 0,
SQ_VTX_SEMANTIC_0 = 0x00028380,
SQ_VTX_SEMANTIC_0_num = 32,
/* SEMANTIC_ID_mask = 0xff << 0, */
/* SEMANTIC_ID_shift = 0, */
VGT_MAX_VTX_INDX = 0x00028400,
VGT_MIN_VTX_INDX = 0x00028404,
VGT_INDX_OFFSET = 0x00028408,
VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c,
SX_ALPHA_TEST_CONTROL = 0x00028410,
ALPHA_FUNC_mask = 0x07 << 0,
ALPHA_FUNC_shift = 0,
REF_NEVER = 0x00,
REF_LESS = 0x01,
REF_EQUAL = 0x02,
REF_LEQUAL = 0x03,
REF_GREATER = 0x04,
REF_NOTEQUAL = 0x05,
REF_GEQUAL = 0x06,
REF_ALWAYS = 0x07,
ALPHA_TEST_ENABLE_bit = 1 << 3,
ALPHA_TEST_BYPASS_bit = 1 << 8,
CB_BLEND_RED = 0x00028414,
CB_BLEND_GREEN = 0x00028418,
CB_BLEND_BLUE = 0x0002841c,
CB_BLEND_ALPHA = 0x00028420,
CB_FOG_RED = 0x00028424,
CB_FOG_GREEN = 0x00028428,
CB_FOG_BLUE = 0x0002842c,
DB_STENCILREFMASK = 0x00028430,
STENCILREF_mask = 0xff << 0,
STENCILREF_shift = 0,
STENCILMASK_mask = 0xff << 8,
STENCILMASK_shift = 8,
STENCILWRITEMASK_mask = 0xff << 16,
STENCILWRITEMASK_shift = 16,
DB_STENCILREFMASK_BF = 0x00028434,
STENCILREF_BF_mask = 0xff << 0,
STENCILREF_BF_shift = 0,
STENCILMASK_BF_mask = 0xff << 8,
STENCILMASK_BF_shift = 8,
STENCILWRITEMASK_BF_mask = 0xff << 16,
STENCILWRITEMASK_BF_shift = 16,
SX_ALPHA_REF = 0x00028438,
PA_CL_VPORT_XSCALE_0 = 0x0002843c,
PA_CL_VPORT_XSCALE_0_num = 16,
PA_CL_VPORT_XSCALE_0_offset = 24,
PA_CL_VPORT_XOFFSET_0 = 0x00028440,
PA_CL_VPORT_XOFFSET_0_num = 16,
PA_CL_VPORT_XOFFSET_0_offset = 24,
PA_CL_VPORT_YSCALE_0 = 0x00028444,
PA_CL_VPORT_YSCALE_0_num = 16,
PA_CL_VPORT_YSCALE_0_offset = 24,
PA_CL_VPORT_YOFFSET_0 = 0x00028448,
PA_CL_VPORT_YOFFSET_0_num = 16,
PA_CL_VPORT_YOFFSET_0_offset = 24,
PA_CL_VPORT_ZSCALE_0 = 0x0002844c,
PA_CL_VPORT_ZSCALE_0_num = 16,
PA_CL_VPORT_ZSCALE_0_offset = 24,
PA_CL_VPORT_ZOFFSET_0 = 0x00028450,
PA_CL_VPORT_ZOFFSET_0_num = 16,
PA_CL_VPORT_ZOFFSET_0_offset = 24,
SPI_VS_OUT_ID_0 = 0x00028614,
SPI_VS_OUT_ID_0_num = 10,
SEMANTIC_0_mask = 0xff << 0,
SEMANTIC_0_shift = 0,
SEMANTIC_1_mask = 0xff << 8,
SEMANTIC_1_shift = 8,
SEMANTIC_2_mask = 0xff << 16,
SEMANTIC_2_shift = 16,
SEMANTIC_3_mask = 0xff << 24,
SEMANTIC_3_shift = 24,
SPI_PS_INPUT_CNTL_0 = 0x00028644,
SPI_PS_INPUT_CNTL_0_num = 32,
SEMANTIC_mask = 0xff << 0,
SEMANTIC_shift = 0,
DEFAULT_VAL_mask = 0x03 << 8,
DEFAULT_VAL_shift = 8,
X_0_0F = 0x00,
FLAT_SHADE_bit = 1 << 10,
SEL_CENTROID_bit = 1 << 11,
SEL_LINEAR_bit = 1 << 12,
CYL_WRAP_mask = 0x0f << 13,
CYL_WRAP_shift = 13,
PT_SPRITE_TEX_bit = 1 << 17,
SEL_SAMPLE_bit = 1 << 18,
SPI_VS_OUT_CONFIG = 0x000286c4,
VS_PER_COMPONENT_bit = 1 << 0,
VS_EXPORT_COUNT_mask = 0x1f << 1,
VS_EXPORT_COUNT_shift = 1,
VS_EXPORTS_FOG_bit = 1 << 8,
VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9,
VS_OUT_FOG_VEC_ADDR_shift = 9,
SPI_PS_IN_CONTROL_0 = 0x000286cc,
NUM_INTERP_mask = 0x3f << 0,
NUM_INTERP_shift = 0,
POSITION_ENA_bit = 1 << 8,
POSITION_CENTROID_bit = 1 << 9,
POSITION_ADDR_mask = 0x1f << 10,
POSITION_ADDR_shift = 10,
PARAM_GEN_mask = 0x0f << 15,
PARAM_GEN_shift = 15,
PARAM_GEN_ADDR_mask = 0x7f << 19,
PARAM_GEN_ADDR_shift = 19,
BARYC_SAMPLE_CNTL_mask = 0x03 << 26,
BARYC_SAMPLE_CNTL_shift = 26,
CENTROIDS_ONLY = 0x00,
CENTERS_ONLY = 0x01,
CENTROIDS_AND_CENTERS = 0x02,
UNDEF = 0x03,
PERSP_GRADIENT_ENA_bit = 1 << 28,
LINEAR_GRADIENT_ENA_bit = 1 << 29,
POSITION_SAMPLE_bit = 1 << 30,
BARYC_AT_SAMPLE_ENA_bit = 1 << 31,
SPI_PS_IN_CONTROL_1 = 0x000286d0,
GEN_INDEX_PIX_bit = 1 << 0,
GEN_INDEX_PIX_ADDR_mask = 0x7f << 1,
GEN_INDEX_PIX_ADDR_shift = 1,
FRONT_FACE_ENA_bit = 1 << 8,
FRONT_FACE_CHAN_mask = 0x03 << 9,
FRONT_FACE_CHAN_shift = 9,
FRONT_FACE_ALL_BITS_bit = 1 << 11,
FRONT_FACE_ADDR_mask = 0x1f << 12,
FRONT_FACE_ADDR_shift = 12,
FOG_ADDR_mask = 0x7f << 17,
FOG_ADDR_shift = 17,
FIXED_PT_POSITION_ENA_bit = 1 << 24,
FIXED_PT_POSITION_ADDR_mask = 0x1f << 25,
FIXED_PT_POSITION_ADDR_shift = 25,
SPI_INTERP_CONTROL_0 = 0x000286d4,
FLAT_SHADE_ENA_bit = 1 << 0,
PNT_SPRITE_ENA_bit = 1 << 1,
PNT_SPRITE_OVRD_X_mask = 0x07 << 2,
PNT_SPRITE_OVRD_X_shift = 2,
SPI_PNT_SPRITE_SEL_0 = 0x00,
SPI_PNT_SPRITE_SEL_1 = 0x01,
SPI_PNT_SPRITE_SEL_S = 0x02,
SPI_PNT_SPRITE_SEL_T = 0x03,
SPI_PNT_SPRITE_SEL_NONE = 0x04,
PNT_SPRITE_OVRD_Y_mask = 0x07 << 5,
PNT_SPRITE_OVRD_Y_shift = 5,
/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
/* SPI_PNT_SPRITE_SEL_S = 0x02, */
/* SPI_PNT_SPRITE_SEL_T = 0x03, */
/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
PNT_SPRITE_OVRD_Z_mask = 0x07 << 8,
PNT_SPRITE_OVRD_Z_shift = 8,
/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
/* SPI_PNT_SPRITE_SEL_S = 0x02, */
/* SPI_PNT_SPRITE_SEL_T = 0x03, */
/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
PNT_SPRITE_OVRD_W_mask = 0x07 << 11,
PNT_SPRITE_OVRD_W_shift = 11,
/* SPI_PNT_SPRITE_SEL_0 = 0x00, */
/* SPI_PNT_SPRITE_SEL_1 = 0x01, */
/* SPI_PNT_SPRITE_SEL_S = 0x02, */
/* SPI_PNT_SPRITE_SEL_T = 0x03, */
/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
PNT_SPRITE_TOP_1_bit = 1 << 14,
SPI_INPUT_Z = 0x000286d8,
PROVIDE_Z_TO_SPI_bit = 1 << 0,
SPI_FOG_CNTL = 0x000286dc,
PASS_FOG_THROUGH_PS_bit = 1 << 0,
PIXEL_FOG_FUNC_mask = 0x03 << 1,
PIXEL_FOG_FUNC_shift = 1,
SPI_FOG_NONE = 0x00,
SPI_FOG_EXP = 0x01,
SPI_FOG_EXP2 = 0x02,
SPI_FOG_LINEAR = 0x03,
PIXEL_FOG_SRC_SEL_bit = 1 << 3,
VS_FOG_CLAMP_DISABLE_bit = 1 << 4,
SPI_FOG_FUNC_SCALE = 0x000286e0,
SPI_FOG_FUNC_BIAS = 0x000286e4,
CB_BLEND0_CONTROL = 0x00028780,
CB_BLEND0_CONTROL_num = 8,
COLOR_SRCBLEND_mask = 0x1f << 0,
COLOR_SRCBLEND_shift = 0,
COLOR_COMB_FCN_mask = 0x07 << 5,
COLOR_COMB_FCN_shift = 5,
COLOR_DESTBLEND_mask = 0x1f << 8,
COLOR_DESTBLEND_shift = 8,
OPACITY_WEIGHT_bit = 1 << 13,
ALPHA_SRCBLEND_mask = 0x1f << 16,
ALPHA_SRCBLEND_shift = 16,
ALPHA_COMB_FCN_mask = 0x07 << 21,
ALPHA_COMB_FCN_shift = 21,
ALPHA_DESTBLEND_mask = 0x1f << 24,
ALPHA_DESTBLEND_shift = 24,
SEPARATE_ALPHA_BLEND_bit = 1 << 29,
VGT_DMA_BASE_HI = 0x000287e4,
VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0,
VGT_DMA_BASE_HI__BASE_ADDR_shift = 0,
VGT_DMA_BASE = 0x000287e8,
VGT_DRAW_INITIATOR = 0x000287f0,
SOURCE_SELECT_mask = 0x03 << 0,
SOURCE_SELECT_shift = 0,
DI_SRC_SEL_DMA = 0x00,
DI_SRC_SEL_IMMEDIATE = 0x01,
DI_SRC_SEL_AUTO_INDEX = 0x02,
DI_SRC_SEL_RESERVED = 0x03,
MAJOR_MODE_mask = 0x03 << 2,
MAJOR_MODE_shift = 2,
DI_MAJOR_MODE_0 = 0x00,
DI_MAJOR_MODE_1 = 0x01,
SPRITE_EN_bit = 1 << 4,
NOT_EOP_bit = 1 << 5,
USE_OPAQUE_bit = 1 << 6,
VGT_IMMED_DATA = 0x000287f4,
VGT_EVENT_ADDRESS_REG = 0x000287f8,
ADDRESS_LOW_mask = 0xfffffff << 0,
ADDRESS_LOW_shift = 0,
DB_DEPTH_CONTROL = 0x00028800,
STENCIL_ENABLE_bit = 1 << 0,
Z_ENABLE_bit = 1 << 1,
Z_WRITE_ENABLE_bit = 1 << 2,
ZFUNC_mask = 0x07 << 4,
ZFUNC_shift = 4,
FRAG_NEVER = 0x00,
FRAG_LESS = 0x01,
FRAG_EQUAL = 0x02,
FRAG_LEQUAL = 0x03,
FRAG_GREATER = 0x04,
FRAG_NOTEQUAL = 0x05,
FRAG_GEQUAL = 0x06,
FRAG_ALWAYS = 0x07,
BACKFACE_ENABLE_bit = 1 << 7,
STENCILFUNC_mask = 0x07 << 8,
STENCILFUNC_shift = 8,
/* REF_NEVER = 0x00, */
/* REF_LESS = 0x01, */
/* REF_EQUAL = 0x02, */
/* REF_LEQUAL = 0x03, */
/* REF_GREATER = 0x04, */
/* REF_NOTEQUAL = 0x05, */
/* REF_GEQUAL = 0x06, */
/* REF_ALWAYS = 0x07, */
STENCILFAIL_mask = 0x07 << 11,
STENCILFAIL_shift = 11,
STENCIL_KEEP = 0x00,
STENCIL_ZERO = 0x01,
STENCIL_REPLACE = 0x02,
STENCIL_INCR_CLAMP = 0x03,
STENCIL_DECR_CLAMP = 0x04,
STENCIL_INVERT = 0x05,
STENCIL_INCR_WRAP = 0x06,
STENCIL_DECR_WRAP = 0x07,
STENCILZPASS_mask = 0x07 << 14,
STENCILZPASS_shift = 14,
/* STENCIL_KEEP = 0x00, */
/* STENCIL_ZERO = 0x01, */
/* STENCIL_REPLACE = 0x02, */
/* STENCIL_INCR_CLAMP = 0x03, */
/* STENCIL_DECR_CLAMP = 0x04, */
/* STENCIL_INVERT = 0x05, */
/* STENCIL_INCR_WRAP = 0x06, */
/* STENCIL_DECR_WRAP = 0x07, */
STENCILZFAIL_mask = 0x07 << 17,
STENCILZFAIL_shift = 17,
/* STENCIL_KEEP = 0x00, */
/* STENCIL_ZERO = 0x01, */
/* STENCIL_REPLACE = 0x02, */
/* STENCIL_INCR_CLAMP = 0x03, */
/* STENCIL_DECR_CLAMP = 0x04, */
/* STENCIL_INVERT = 0x05, */
/* STENCIL_INCR_WRAP = 0x06, */
/* STENCIL_DECR_WRAP = 0x07, */
STENCILFUNC_BF_mask = 0x07 << 20,
STENCILFUNC_BF_shift = 20,
/* REF_NEVER = 0x00, */
/* REF_LESS = 0x01, */
/* REF_EQUAL = 0x02, */
/* REF_LEQUAL = 0x03, */
/* REF_GREATER = 0x04, */
/* REF_NOTEQUAL = 0x05, */
/* REF_GEQUAL = 0x06, */
/* REF_ALWAYS = 0x07, */
STENCILFAIL_BF_mask = 0x07 << 23,
STENCILFAIL_BF_shift = 23,
/* STENCIL_KEEP = 0x00, */
/* STENCIL_ZERO = 0x01, */
/* STENCIL_REPLACE = 0x02, */
/* STENCIL_INCR_CLAMP = 0x03, */
/* STENCIL_DECR_CLAMP = 0x04, */
/* STENCIL_INVERT = 0x05, */
/* STENCIL_INCR_WRAP = 0x06, */
/* STENCIL_DECR_WRAP = 0x07, */
STENCILZPASS_BF_mask = 0x07 << 26,
STENCILZPASS_BF_shift = 26,
/* STENCIL_KEEP = 0x00, */
/* STENCIL_ZERO = 0x01, */
/* STENCIL_REPLACE = 0x02, */
/* STENCIL_INCR_CLAMP = 0x03, */
/* STENCIL_DECR_CLAMP = 0x04, */
/* STENCIL_INVERT = 0x05, */
/* STENCIL_INCR_WRAP = 0x06, */
/* STENCIL_DECR_WRAP = 0x07, */
STENCILZFAIL_BF_mask = 0x07 << 29,
STENCILZFAIL_BF_shift = 29,
/* STENCIL_KEEP = 0x00, */
/* STENCIL_ZERO = 0x01, */
/* STENCIL_REPLACE = 0x02, */
/* STENCIL_INCR_CLAMP = 0x03, */
/* STENCIL_DECR_CLAMP = 0x04, */
/* STENCIL_INVERT = 0x05, */
/* STENCIL_INCR_WRAP = 0x06, */
/* STENCIL_DECR_WRAP = 0x07, */
CB_BLEND_CONTROL = 0x00028804,
/* COLOR_SRCBLEND_mask = 0x1f << 0, */
/* COLOR_SRCBLEND_shift = 0, */
BLEND_ZERO = 0x00,
BLEND_ONE = 0x01,
BLEND_SRC_COLOR = 0x02,
BLEND_ONE_MINUS_SRC_COLOR = 0x03,
BLEND_SRC_ALPHA = 0x04,
BLEND_ONE_MINUS_SRC_ALPHA = 0x05,
BLEND_DST_ALPHA = 0x06,
BLEND_ONE_MINUS_DST_ALPHA = 0x07,
BLEND_DST_COLOR = 0x08,
BLEND_ONE_MINUS_DST_COLOR = 0x09,
BLEND_SRC_ALPHA_SATURATE = 0x0a,
BLEND_BOTH_SRC_ALPHA = 0x0b,
BLEND_BOTH_INV_SRC_ALPHA = 0x0c,
BLEND_CONSTANT_COLOR = 0x0d,
BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e,
BLEND_SRC1_COLOR = 0x0f,
BLEND_INV_SRC1_COLOR = 0x10,
BLEND_SRC1_ALPHA = 0x11,
BLEND_INV_SRC1_ALPHA = 0x12,
BLEND_CONSTANT_ALPHA = 0x13,
BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
/* COLOR_COMB_FCN_mask = 0x07 << 5, */
/* COLOR_COMB_FCN_shift = 5, */
COMB_DST_PLUS_SRC = 0x00,
COMB_SRC_MINUS_DST = 0x01,
COMB_MIN_DST_SRC = 0x02,
COMB_MAX_DST_SRC = 0x03,
COMB_DST_MINUS_SRC = 0x04,
/* COLOR_DESTBLEND_mask = 0x1f << 8, */
/* COLOR_DESTBLEND_shift = 8, */
/* BLEND_ZERO = 0x00, */
/* BLEND_ONE = 0x01, */
/* BLEND_SRC_COLOR = 0x02, */
/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
/* BLEND_SRC_ALPHA = 0x04, */
/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
/* BLEND_DST_ALPHA = 0x06, */
/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
/* BLEND_DST_COLOR = 0x08, */
/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
/* BLEND_CONSTANT_COLOR = 0x0d, */
/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
/* BLEND_SRC1_COLOR = 0x0f, */
/* BLEND_INV_SRC1_COLOR = 0x10, */
/* BLEND_SRC1_ALPHA = 0x11, */
/* BLEND_INV_SRC1_ALPHA = 0x12, */
/* BLEND_CONSTANT_ALPHA = 0x13, */
/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
/* OPACITY_WEIGHT_bit = 1 << 13, */
/* ALPHA_SRCBLEND_mask = 0x1f << 16, */
/* ALPHA_SRCBLEND_shift = 16, */
/* BLEND_ZERO = 0x00, */
/* BLEND_ONE = 0x01, */
/* BLEND_SRC_COLOR = 0x02, */
/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
/* BLEND_SRC_ALPHA = 0x04, */
/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
/* BLEND_DST_ALPHA = 0x06, */
/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
/* BLEND_DST_COLOR = 0x08, */
/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
/* BLEND_CONSTANT_COLOR = 0x0d, */
/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
/* BLEND_SRC1_COLOR = 0x0f, */
/* BLEND_INV_SRC1_COLOR = 0x10, */
/* BLEND_SRC1_ALPHA = 0x11, */
/* BLEND_INV_SRC1_ALPHA = 0x12, */
/* BLEND_CONSTANT_ALPHA = 0x13, */
/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
/* ALPHA_COMB_FCN_mask = 0x07 << 21, */
/* ALPHA_COMB_FCN_shift = 21, */
/* COMB_DST_PLUS_SRC = 0x00, */
/* COMB_SRC_MINUS_DST = 0x01, */
/* COMB_MIN_DST_SRC = 0x02, */
/* COMB_MAX_DST_SRC = 0x03, */
/* COMB_DST_MINUS_SRC = 0x04, */
/* ALPHA_DESTBLEND_mask = 0x1f << 24, */
/* ALPHA_DESTBLEND_shift = 24, */
/* BLEND_ZERO = 0x00, */
/* BLEND_ONE = 0x01, */
/* BLEND_SRC_COLOR = 0x02, */
/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
/* BLEND_SRC_ALPHA = 0x04, */
/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
/* BLEND_DST_ALPHA = 0x06, */
/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
/* BLEND_DST_COLOR = 0x08, */
/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
/* BLEND_BOTH_SRC_ALPHA = 0x0b, */
/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
/* BLEND_CONSTANT_COLOR = 0x0d, */
/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
/* BLEND_SRC1_COLOR = 0x0f, */
/* BLEND_INV_SRC1_COLOR = 0x10, */
/* BLEND_SRC1_ALPHA = 0x11, */
/* BLEND_INV_SRC1_ALPHA = 0x12, */
/* BLEND_CONSTANT_ALPHA = 0x13, */
/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
/* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */
CB_COLOR_CONTROL = 0x00028808,
FOG_ENABLE_bit = 1 << 0,
MULTIWRITE_ENABLE_bit = 1 << 1,
DITHER_ENABLE_bit = 1 << 2,
DEGAMMA_ENABLE_bit = 1 << 3,
SPECIAL_OP_mask = 0x07 << 4,
SPECIAL_OP_shift = 4,
SPECIAL_NORMAL = 0x00,
SPECIAL_DISABLE = 0x01,
SPECIAL_FAST_CLEAR = 0x02,
SPECIAL_FORCE_CLEAR = 0x03,
SPECIAL_EXPAND_COLOR = 0x04,
SPECIAL_EXPAND_TEXTURE = 0x05,
SPECIAL_EXPAND_SAMPLES = 0x06,
SPECIAL_RESOLVE_BOX = 0x07,
PER_MRT_BLEND_bit = 1 << 7,
TARGET_BLEND_ENABLE_mask = 0xff << 8,
TARGET_BLEND_ENABLE_shift = 8,
ROP3_mask = 0xff << 16,
ROP3_shift = 16,
DB_SHADER_CONTROL = 0x0002880c,
Z_EXPORT_ENABLE_bit = 1 << 0,
STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1,
Z_ORDER_mask = 0x03 << 4,
Z_ORDER_shift = 4,
LATE_Z = 0x00,
EARLY_Z_THEN_LATE_Z = 0x01,
RE_Z = 0x02,
EARLY_Z_THEN_RE_Z = 0x03,
KILL_ENABLE_bit = 1 << 6,
COVERAGE_TO_MASK_ENABLE_bit = 1 << 7,
MASK_EXPORT_ENABLE_bit = 1 << 8,
DUAL_EXPORT_ENABLE_bit = 1 << 9,
EXEC_ON_HIER_FAIL_bit = 1 << 10,
EXEC_ON_NOOP_bit = 1 << 11,
PA_CL_CLIP_CNTL = 0x00028810,
UCP_ENA_0_bit = 1 << 0,
UCP_ENA_1_bit = 1 << 1,
UCP_ENA_2_bit = 1 << 2,
UCP_ENA_3_bit = 1 << 3,
UCP_ENA_4_bit = 1 << 4,
UCP_ENA_5_bit = 1 << 5,
PS_UCP_Y_SCALE_NEG_bit = 1 << 13,
PS_UCP_MODE_mask = 0x03 << 14,
PS_UCP_MODE_shift = 14,
CLIP_DISABLE_bit = 1 << 16,
UCP_CULL_ONLY_ENA_bit = 1 << 17,
BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18,
DX_CLIP_SPACE_DEF_bit = 1 << 19,
DIS_CLIP_ERR_DETECT_bit = 1 << 20,
VTX_KILL_OR_bit = 1 << 21,
DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24,
VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25,
ZCLIP_NEAR_DISABLE_bit = 1 << 26,
ZCLIP_FAR_DISABLE_bit = 1 << 27,
PA_SU_SC_MODE_CNTL = 0x00028814,
CULL_FRONT_bit = 1 << 0,
CULL_BACK_bit = 1 << 1,
FACE_bit = 1 << 2,
POLY_MODE_mask = 0x03 << 3,
POLY_MODE_shift = 3,
X_DISABLE_POLY_MODE = 0x00,
X_DUAL_MODE = 0x01,
POLYMODE_FRONT_PTYPE_mask = 0x07 << 5,
POLYMODE_FRONT_PTYPE_shift = 5,
X_DRAW_POINTS = 0x00,
X_DRAW_LINES = 0x01,
X_DRAW_TRIANGLES = 0x02,
POLYMODE_BACK_PTYPE_mask = 0x07 << 8,
POLYMODE_BACK_PTYPE_shift = 8,
/* X_DRAW_POINTS = 0x00, */
/* X_DRAW_LINES = 0x01, */
/* X_DRAW_TRIANGLES = 0x02, */
POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11,
POLY_OFFSET_BACK_ENABLE_bit = 1 << 12,
POLY_OFFSET_PARA_ENABLE_bit = 1 << 13,
VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16,
PROVOKING_VTX_LAST_bit = 1 << 19,
PERSP_CORR_DIS_bit = 1 << 20,
MULTI_PRIM_IB_ENA_bit = 1 << 21,
PA_CL_VTE_CNTL = 0x00028818,
VPORT_X_SCALE_ENA_bit = 1 << 0,
VPORT_X_OFFSET_ENA_bit = 1 << 1,
VPORT_Y_SCALE_ENA_bit = 1 << 2,
VPORT_Y_OFFSET_ENA_bit = 1 << 3,
VPORT_Z_SCALE_ENA_bit = 1 << 4,
VPORT_Z_OFFSET_ENA_bit = 1 << 5,
VTX_XY_FMT_bit = 1 << 8,
VTX_Z_FMT_bit = 1 << 9,
VTX_W0_FMT_bit = 1 << 10,
PERFCOUNTER_REF_bit = 1 << 11,
PA_CL_VS_OUT_CNTL = 0x0002881c,
CLIP_DIST_ENA_0_bit = 1 << 0,
CLIP_DIST_ENA_1_bit = 1 << 1,
CLIP_DIST_ENA_2_bit = 1 << 2,
CLIP_DIST_ENA_3_bit = 1 << 3,
CLIP_DIST_ENA_4_bit = 1 << 4,
CLIP_DIST_ENA_5_bit = 1 << 5,
CLIP_DIST_ENA_6_bit = 1 << 6,
CLIP_DIST_ENA_7_bit = 1 << 7,
CULL_DIST_ENA_0_bit = 1 << 8,
CULL_DIST_ENA_1_bit = 1 << 9,
CULL_DIST_ENA_2_bit = 1 << 10,
CULL_DIST_ENA_3_bit = 1 << 11,
CULL_DIST_ENA_4_bit = 1 << 12,
CULL_DIST_ENA_5_bit = 1 << 13,
CULL_DIST_ENA_6_bit = 1 << 14,
CULL_DIST_ENA_7_bit = 1 << 15,
USE_VTX_POINT_SIZE_bit = 1 << 16,
USE_VTX_EDGE_FLAG_bit = 1 << 17,
USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18,
USE_VTX_VIEWPORT_INDX_bit = 1 << 19,
USE_VTX_KILL_FLAG_bit = 1 << 20,
VS_OUT_MISC_VEC_ENA_bit = 1 << 21,
VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22,
VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23,
PA_CL_NANINF_CNTL = 0x00028820,
VTE_XY_INF_DISCARD_bit = 1 << 0,
VTE_Z_INF_DISCARD_bit = 1 << 1,
VTE_W_INF_DISCARD_bit = 1 << 2,
VTE_0XNANINF_IS_0_bit = 1 << 3,
VTE_XY_NAN_RETAIN_bit = 1 << 4,
VTE_Z_NAN_RETAIN_bit = 1 << 5,
VTE_W_NAN_RETAIN_bit = 1 << 6,
VTE_W_RECIP_NAN_IS_0_bit = 1 << 7,
VS_XY_NAN_TO_INF_bit = 1 << 8,
VS_XY_INF_RETAIN_bit = 1 << 9,
VS_Z_NAN_TO_INF_bit = 1 << 10,
VS_Z_INF_RETAIN_bit = 1 << 11,
VS_W_NAN_TO_INF_bit = 1 << 12,
VS_W_INF_RETAIN_bit = 1 << 13,
VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14,
VTE_NO_OUTPUT_NEG_0_bit = 1 << 20,
SQ_PGM_START_PS = 0x00028840,
SQ_PGM_RESOURCES_PS = 0x00028850,
NUM_GPRS_mask = 0xff << 0,
NUM_GPRS_shift = 0,
STACK_SIZE_mask = 0xff << 8,
STACK_SIZE_shift = 8,
SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21,
FETCH_CACHE_LINES_mask = 0x07 << 24,
FETCH_CACHE_LINES_shift = 24,
UNCACHED_FIRST_INST_bit = 1 << 28,
CLAMP_CONSTS_bit = 1 << 31,
SQ_PGM_EXPORTS_PS = 0x00028854,
EXPORT_MODE_mask = 0x1f << 0,
EXPORT_MODE_shift = 0,
SQ_PGM_START_VS = 0x00028858,
SQ_PGM_RESOURCES_VS = 0x00028868,
/* NUM_GPRS_mask = 0xff << 0, */
/* NUM_GPRS_shift = 0, */
/* STACK_SIZE_mask = 0xff << 8, */
/* STACK_SIZE_shift = 8, */
SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21,
/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
/* FETCH_CACHE_LINES_shift = 24, */
/* UNCACHED_FIRST_INST_bit = 1 << 28, */
SQ_PGM_START_GS = 0x0002886c,
SQ_PGM_RESOURCES_GS = 0x0002887c,
/* NUM_GPRS_mask = 0xff << 0, */
/* NUM_GPRS_shift = 0, */
/* STACK_SIZE_mask = 0xff << 8, */
/* STACK_SIZE_shift = 8, */
SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21,
/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
/* FETCH_CACHE_LINES_shift = 24, */
/* UNCACHED_FIRST_INST_bit = 1 << 28, */
SQ_PGM_START_ES = 0x00028880,
SQ_PGM_RESOURCES_ES = 0x00028890,
/* NUM_GPRS_mask = 0xff << 0, */
/* NUM_GPRS_shift = 0, */
/* STACK_SIZE_mask = 0xff << 8, */
/* STACK_SIZE_shift = 8, */
SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21,
/* FETCH_CACHE_LINES_mask = 0x07 << 24, */
/* FETCH_CACHE_LINES_shift = 24, */
/* UNCACHED_FIRST_INST_bit = 1 << 28, */
SQ_PGM_START_FS = 0x00028894,
SQ_PGM_RESOURCES_FS = 0x000288a4,
/* NUM_GPRS_mask = 0xff << 0, */
/* NUM_GPRS_shift = 0, */
/* STACK_SIZE_mask = 0xff << 8, */
/* STACK_SIZE_shift = 8, */
SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21,
SQ_ESGS_RING_ITEMSIZE = 0x000288a8,
ITEMSIZE_mask = 0x7fff << 0,
ITEMSIZE_shift = 0,
SQ_GSVS_RING_ITEMSIZE = 0x000288ac,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_ESTMP_RING_ITEMSIZE = 0x000288b0,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_GSTMP_RING_ITEMSIZE = 0x000288b4,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_VSTMP_RING_ITEMSIZE = 0x000288b8,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_PSTMP_RING_ITEMSIZE = 0x000288bc,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_FBUF_RING_ITEMSIZE = 0x000288c0,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_REDUC_RING_ITEMSIZE = 0x000288c4,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_GS_VERT_ITEMSIZE = 0x000288c8,
/* ITEMSIZE_mask = 0x7fff << 0, */
/* ITEMSIZE_shift = 0, */
SQ_PGM_CF_OFFSET_PS = 0x000288cc,
PGM_CF_OFFSET_mask = 0xfffff << 0,
PGM_CF_OFFSET_shift = 0,
SQ_PGM_CF_OFFSET_VS = 0x000288d0,
/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
/* PGM_CF_OFFSET_shift = 0, */
SQ_PGM_CF_OFFSET_GS = 0x000288d4,
/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
/* PGM_CF_OFFSET_shift = 0, */
SQ_PGM_CF_OFFSET_ES = 0x000288d8,
/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
/* PGM_CF_OFFSET_shift = 0, */
SQ_PGM_CF_OFFSET_FS = 0x000288dc,
/* PGM_CF_OFFSET_mask = 0xfffff << 0, */
/* PGM_CF_OFFSET_shift = 0, */
SQ_VTX_SEMANTIC_CLEAR = 0x000288e0,
SQ_ALU_CONST_CACHE_PS_0 = 0x00028940,
SQ_ALU_CONST_CACHE_PS_0_num = 16,
SQ_ALU_CONST_CACHE_VS_0 = 0x00028980,
SQ_ALU_CONST_CACHE_VS_0_num = 16,
SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0,
SQ_ALU_CONST_CACHE_GS_0_num = 16,
PA_SU_POINT_SIZE = 0x00028a00,
PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0,
PA_SU_POINT_SIZE__HEIGHT_shift = 0,
PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16,
PA_SU_POINT_SIZE__WIDTH_shift = 16,
PA_SU_POINT_MINMAX = 0x00028a04,
MIN_SIZE_mask = 0xffff << 0,
MIN_SIZE_shift = 0,
MAX_SIZE_mask = 0xffff << 16,
MAX_SIZE_shift = 16,
PA_SU_LINE_CNTL = 0x00028a08,
PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0,
PA_SU_LINE_CNTL__WIDTH_shift = 0,
PA_SC_LINE_STIPPLE = 0x00028a0c,
LINE_PATTERN_mask = 0xffff << 0,
LINE_PATTERN_shift = 0,
REPEAT_COUNT_mask = 0xff << 16,
REPEAT_COUNT_shift = 16,
PATTERN_BIT_ORDER_bit = 1 << 28,
AUTO_RESET_CNTL_mask = 0x03 << 29,
AUTO_RESET_CNTL_shift = 29,
VGT_OUTPUT_PATH_CNTL = 0x00028a10,
PATH_SELECT_mask = 0x03 << 0,
PATH_SELECT_shift = 0,
VGT_OUTPATH_VTX_REUSE = 0x00,
VGT_OUTPATH_TESS_EN = 0x01,
VGT_OUTPATH_PASSTHRU = 0x02,
VGT_OUTPATH_GS_BLOCK = 0x03,
VGT_HOS_CNTL = 0x00028a14,
TESS_MODE_mask = 0x03 << 0,
TESS_MODE_shift = 0,
VGT_HOS_MAX_TESS_LEVEL = 0x00028a18,
VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c,
VGT_HOS_REUSE_DEPTH = 0x00028a20,
REUSE_DEPTH_mask = 0xff << 0,
REUSE_DEPTH_shift = 0,
VGT_GROUP_PRIM_TYPE = 0x00028a24,
VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0,
VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0,
VGT_GRP_3D_POINT = 0x00,
VGT_GRP_3D_LINE = 0x01,
VGT_GRP_3D_TRI = 0x02,
VGT_GRP_3D_RECT = 0x03,
VGT_GRP_3D_QUAD = 0x04,
VGT_GRP_2D_COPY_RECT_V0 = 0x05,
VGT_GRP_2D_COPY_RECT_V1 = 0x06,
VGT_GRP_2D_COPY_RECT_V2 = 0x07,
VGT_GRP_2D_COPY_RECT_V3 = 0x08,
VGT_GRP_2D_FILL_RECT = 0x09,
VGT_GRP_2D_LINE = 0x0a,
VGT_GRP_2D_TRI = 0x0b,
VGT_GRP_PRIM_INDEX_LINE = 0x0c,
VGT_GRP_PRIM_INDEX_TRI = 0x0d,
VGT_GRP_PRIM_INDEX_QUAD = 0x0e,
VGT_GRP_3D_LINE_ADJ = 0x0f,
VGT_GRP_3D_TRI_ADJ = 0x10,
RETAIN_ORDER_bit = 1 << 14,
RETAIN_QUADS_bit = 1 << 15,
PRIM_ORDER_mask = 0x07 << 16,
PRIM_ORDER_shift = 16,
VGT_GRP_LIST = 0x00,
VGT_GRP_STRIP = 0x01,
VGT_GRP_FAN = 0x02,
VGT_GRP_LOOP = 0x03,
VGT_GRP_POLYGON = 0x04,
VGT_GROUP_FIRST_DECR = 0x00028a28,
FIRST_DECR_mask = 0x0f << 0,
FIRST_DECR_shift = 0,
VGT_GROUP_DECR = 0x00028a2c,
DECR_mask = 0x0f << 0,
DECR_shift = 0,
VGT_GROUP_VECT_0_CNTL = 0x00028a30,
COMP_X_EN_bit = 1 << 0,
COMP_Y_EN_bit = 1 << 1,
COMP_Z_EN_bit = 1 << 2,
COMP_W_EN_bit = 1 << 3,
VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8,
VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8,
SHIFT_mask = 0xff << 16,
SHIFT_shift = 16,
VGT_GROUP_VECT_1_CNTL = 0x00028a34,
/* COMP_X_EN_bit = 1 << 0, */
/* COMP_Y_EN_bit = 1 << 1, */
/* COMP_Z_EN_bit = 1 << 2, */
/* COMP_W_EN_bit = 1 << 3, */
VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8,
VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8,
/* SHIFT_mask = 0xff << 16, */
/* SHIFT_shift = 16, */
VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38,
X_CONV_mask = 0x0f << 0,
X_CONV_shift = 0,
VGT_GRP_INDEX_16 = 0x00,
VGT_GRP_INDEX_32 = 0x01,
VGT_GRP_UINT_16 = 0x02,
VGT_GRP_UINT_32 = 0x03,
VGT_GRP_SINT_16 = 0x04,
VGT_GRP_SINT_32 = 0x05,
VGT_GRP_FLOAT_32 = 0x06,
VGT_GRP_AUTO_PRIM = 0x07,
VGT_GRP_FIX_1_23_TO_FLOAT = 0x08,
X_OFFSET_mask = 0x0f << 4,
X_OFFSET_shift = 4,
Y_CONV_mask = 0x0f << 8,
Y_CONV_shift = 8,
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
Y_OFFSET_mask = 0x0f << 12,
Y_OFFSET_shift = 12,
Z_CONV_mask = 0x0f << 16,
Z_CONV_shift = 16,
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
Z_OFFSET_mask = 0x0f << 20,
Z_OFFSET_shift = 20,
W_CONV_mask = 0x0f << 24,
W_CONV_shift = 24,
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
W_OFFSET_mask = 0x0f << 28,
W_OFFSET_shift = 28,
VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c,
/* X_CONV_mask = 0x0f << 0, */
/* X_CONV_shift = 0, */
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
/* X_OFFSET_mask = 0x0f << 4, */
/* X_OFFSET_shift = 4, */
/* Y_CONV_mask = 0x0f << 8, */
/* Y_CONV_shift = 8, */
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
/* Y_OFFSET_mask = 0x0f << 12, */
/* Y_OFFSET_shift = 12, */
/* Z_CONV_mask = 0x0f << 16, */
/* Z_CONV_shift = 16, */
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
/* Z_OFFSET_mask = 0x0f << 20, */
/* Z_OFFSET_shift = 20, */
/* W_CONV_mask = 0x0f << 24, */
/* W_CONV_shift = 24, */
/* VGT_GRP_INDEX_16 = 0x00, */
/* VGT_GRP_INDEX_32 = 0x01, */
/* VGT_GRP_UINT_16 = 0x02, */
/* VGT_GRP_UINT_32 = 0x03, */
/* VGT_GRP_SINT_16 = 0x04, */
/* VGT_GRP_SINT_32 = 0x05, */
/* VGT_GRP_FLOAT_32 = 0x06, */
/* VGT_GRP_AUTO_PRIM = 0x07, */
/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
/* W_OFFSET_mask = 0x0f << 28, */
/* W_OFFSET_shift = 28, */
VGT_GS_MODE = 0x00028a40,
MODE_mask = 0x03 << 0,
MODE_shift = 0,
GS_OFF = 0x00,
GS_SCENARIO_A = 0x01,
GS_SCENARIO_B = 0x02,
GS_SCENARIO_G = 0x03,
ES_PASSTHRU_bit = 1 << 2,
CUT_MODE_mask = 0x03 << 3,
CUT_MODE_shift = 3,
GS_CUT_1024 = 0x00,
GS_CUT_512 = 0x01,
GS_CUT_256 = 0x02,
GS_CUT_128 = 0x03,
PA_SC_MPASS_PS_CNTL = 0x00028a48,
MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0,
MPASS_PIX_VEC_PER_PASS_shift = 0,
MPASS_PS_ENA_bit = 1 << 31,
PA_SC_MODE_CNTL = 0x00028a4c,
MSAA_ENABLE_bit = 1 << 0,
CLIPRECT_ENABLE_bit = 1 << 1,
LINE_STIPPLE_ENABLE_bit = 1 << 2,
MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3,
WALK_ORDER_ENABLE_bit = 1 << 4,
HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5,
WALK_SIZE_bit = 1 << 6,
WALK_ALIGNMENT_bit = 1 << 7,
WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8,
TILE_COVER_NO_SCISSOR_bit = 1 << 9,
KILL_PIX_POST_HI_Z_bit = 1 << 10,
KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11,
MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12,
TILE_COVER_DISABLE_bit = 1 << 13,
FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14,
FORCE_EOV_TILE_ENABLE_bit = 1 << 15,
FORCE_EOV_REZ_ENABLE_bit = 1 << 16,
PS_ITER_SAMPLE_bit = 1 << 17,
VGT_ENHANCE = 0x00028a50,
VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0,
VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0,
X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00,
X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01,
X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02,
X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03,
MISC_mask = 0x3fffffff << 2,
MISC_shift = 2,
VGT_GS_OUT_PRIM_TYPE = 0x00028a6c,
OUTPRIM_TYPE_mask = 0x3f << 0,
OUTPRIM_TYPE_shift = 0,
POINTLIST = 0x00,
LINESTRIP = 0x01,
TRISTRIP = 0x02,
VGT_DMA_SIZE = 0x00028a74,
VGT_DMA_INDEX_TYPE = 0x00028a7c,
/* INDEX_TYPE_mask = 0x03 << 0, */
/* INDEX_TYPE_shift = 0, */
VGT_INDEX_16 = 0x00,
VGT_INDEX_32 = 0x01,
SWAP_MODE_mask = 0x03 << 2,
SWAP_MODE_shift = 2,
VGT_DMA_SWAP_NONE = 0x00,
VGT_DMA_SWAP_16_BIT = 0x01,
VGT_DMA_SWAP_32_BIT = 0x02,
VGT_DMA_SWAP_WORD = 0x03,
VGT_PRIMITIVEID_EN = 0x00028a84,
PRIMITIVEID_EN_bit = 1 << 0,
VGT_DMA_NUM_INSTANCES = 0x00028a88,
VGT_EVENT_INITIATOR = 0x00028a90,
EVENT_TYPE_mask = 0x3f << 0,
EVENT_TYPE_shift = 0,
CACHE_FLUSH_TS = 0x04,
CONTEXT_DONE = 0x05,
CACHE_FLUSH = 0x06,
VIZQUERY_START = 0x07,
VIZQUERY_END = 0x08,
SC_WAIT_WC = 0x09,
MPASS_PS_CP_REFETCH = 0x0a,
MPASS_PS_RST_START = 0x0b,
MPASS_PS_INCR_START = 0x0c,
RST_PIX_CNT = 0x0d,
RST_VTX_CNT = 0x0e,
VS_PARTIAL_FLUSH = 0x0f,
PS_PARTIAL_FLUSH = 0x10,
CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
ZPASS_DONE = 0x15,
CACHE_FLUSH_AND_INV_EVENT = 0x16,
PERFCOUNTER_START = 0x17,
PERFCOUNTER_STOP = 0x18,
PIPELINESTAT_START = 0x19,
PIPELINESTAT_STOP = 0x1a,
PERFCOUNTER_SAMPLE = 0x1b,
FLUSH_ES_OUTPUT = 0x1c,
FLUSH_GS_OUTPUT = 0x1d,
SAMPLE_PIPELINESTAT = 0x1e,
SO_VGTSTREAMOUT_FLUSH = 0x1f,
SAMPLE_STREAMOUTSTATS = 0x20,
RESET_VTX_CNT = 0x21,
BLOCK_CONTEXT_DONE = 0x22,
CR_CONTEXT_DONE = 0x23,
VGT_FLUSH = 0x24,
CR_DONE_TS = 0x25,
SQ_NON_EVENT = 0x26,
SC_SEND_DB_VPZ = 0x27,
BOTTOM_OF_PIPE_TS = 0x28,
DB_CACHE_FLUSH_AND_INV = 0x2a,
ADDRESS_HI_mask = 0xff << 19,
ADDRESS_HI_shift = 19,
EXTENDED_EVENT_bit = 1 << 27,
VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94,
RESET_EN_bit = 1 << 0,
VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0,
VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4,
VGT_STRMOUT_EN = 0x00028ab0,
STREAMOUT_bit = 1 << 0,
VGT_REUSE_OFF = 0x00028ab4,
REUSE_OFF_bit = 1 << 0,
VGT_VTX_CNT_EN = 0x00028ab8,
VTX_CNT_EN_bit = 1 << 0,
VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0,
VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4,
VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0,
VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0,
VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8,
VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc,
VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0,
VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4,
VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0,
VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0,
VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8,
VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec,
VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0,
VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4,
VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0,
VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0,
VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8,
VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc,
VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00,
VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04,
VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0,
VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0,
VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08,
VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c,
VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10,
VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14,
VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18,
VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c,
VGT_STRMOUT_BUFFER_EN = 0x00028b20,
BUFFER_0_EN_bit = 1 << 0,
BUFFER_1_EN_bit = 1 << 1,
BUFFER_2_EN_bit = 1 << 2,
BUFFER_3_EN_bit = 1 << 3,
VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28,
VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c,
VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30,
VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44,
VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0,
VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0,
VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48,
VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0,
VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0,
VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c,
VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0,
VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0,
VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50,
VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0,
VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0,
PA_SC_LINE_CNTL = 0x00028c00,
BRES_CNTL_mask = 0xff << 0,
BRES_CNTL_shift = 0,
USE_BRES_CNTL_bit = 1 << 8,
EXPAND_LINE_WIDTH_bit = 1 << 9,
LAST_PIXEL_bit = 1 << 10,
PA_SC_AA_CONFIG = 0x00028c04,
MSAA_NUM_SAMPLES_mask = 0x03 << 0,
MSAA_NUM_SAMPLES_shift = 0,
AA_MASK_CENTROID_DTMN_bit = 1 << 4,
MAX_SAMPLE_DIST_mask = 0x0f << 13,
MAX_SAMPLE_DIST_shift = 13,
PA_SU_VTX_CNTL = 0x00028c08,
PIX_CENTER_bit = 1 << 0,
PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1,
PA_SU_VTX_CNTL__ROUND_MODE_shift = 1,
X_TRUNCATE = 0x00,
X_ROUND = 0x01,
X_ROUND_TO_EVEN = 0x02,
X_ROUND_TO_ODD = 0x03,
QUANT_MODE_mask = 0x07 << 3,
QUANT_MODE_shift = 3,
X_1_16TH = 0x00,
X_1_8TH = 0x01,
X_1_4TH = 0x02,
X_1_2 = 0x03,
X_1 = 0x04,
X_1_256TH = 0x05,
PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c,
PA_CL_GB_VERT_DISC_ADJ = 0x00028c10,
PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14,
PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18,
PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c,
/* S0_X_mask = 0x0f << 0, */
/* S0_X_shift = 0, */
/* S0_Y_mask = 0x0f << 4, */
/* S0_Y_shift = 4, */
/* S1_X_mask = 0x0f << 8, */
/* S1_X_shift = 8, */
/* S1_Y_mask = 0x0f << 12, */
/* S1_Y_shift = 12, */
/* S2_X_mask = 0x0f << 16, */
/* S2_X_shift = 16, */
/* S2_Y_mask = 0x0f << 20, */
/* S2_Y_shift = 20, */
/* S3_X_mask = 0x0f << 24, */
/* S3_X_shift = 24, */
/* S3_Y_mask = 0x0f << 28, */
/* S3_Y_shift = 28, */
PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20,
/* S4_X_mask = 0x0f << 0, */
/* S4_X_shift = 0, */
/* S4_Y_mask = 0x0f << 4, */
/* S4_Y_shift = 4, */
/* S5_X_mask = 0x0f << 8, */
/* S5_X_shift = 8, */
/* S5_Y_mask = 0x0f << 12, */
/* S5_Y_shift = 12, */
/* S6_X_mask = 0x0f << 16, */
/* S6_X_shift = 16, */
/* S6_Y_mask = 0x0f << 20, */
/* S6_Y_shift = 20, */
/* S7_X_mask = 0x0f << 24, */
/* S7_X_shift = 24, */
/* S7_Y_mask = 0x0f << 28, */
/* S7_Y_shift = 28, */
CB_CLRCMP_CONTROL = 0x00028c30,
CLRCMP_FCN_SRC_mask = 0x07 << 0,
CLRCMP_FCN_SRC_shift = 0,
CLRCMP_DRAW_ALWAYS = 0x00,
CLRCMP_DRAW_NEVER = 0x01,
CLRCMP_DRAW_ON_NEQ = 0x04,
CLRCMP_DRAW_ON_EQ = 0x05,
CLRCMP_FCN_DST_mask = 0x07 << 8,
CLRCMP_FCN_DST_shift = 8,
/* CLRCMP_DRAW_ALWAYS = 0x00, */
/* CLRCMP_DRAW_NEVER = 0x01, */
/* CLRCMP_DRAW_ON_NEQ = 0x04, */
/* CLRCMP_DRAW_ON_EQ = 0x05, */
CLRCMP_FCN_SEL_mask = 0x03 << 24,
CLRCMP_FCN_SEL_shift = 24,
CLRCMP_SEL_DST = 0x00,
CLRCMP_SEL_SRC = 0x01,
CLRCMP_SEL_AND = 0x02,
CB_CLRCMP_SRC = 0x00028c34,
CB_CLRCMP_DST = 0x00028c38,
CB_CLRCMP_MSK = 0x00028c3c,
PA_SC_AA_MASK = 0x00028c48,
VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58,
VTX_REUSE_DEPTH_mask = 0xff << 0,
VTX_REUSE_DEPTH_shift = 0,
VGT_OUT_DEALLOC_CNTL = 0x00028c5c,
DEALLOC_DIST_mask = 0x7f << 0,
DEALLOC_DIST_shift = 0,
DB_RENDER_CONTROL = 0x00028d0c,
DEPTH_CLEAR_ENABLE_bit = 1 << 0,
STENCIL_CLEAR_ENABLE_bit = 1 << 1,
DEPTH_COPY_bit = 1 << 2,
STENCIL_COPY_bit = 1 << 3,
RESUMMARIZE_ENABLE_bit = 1 << 4,
STENCIL_COMPRESS_DISABLE_bit = 1 << 5,
DEPTH_COMPRESS_DISABLE_bit = 1 << 6,
COPY_CENTROID_bit = 1 << 7,
COPY_SAMPLE_mask = 0x07 << 8,
COPY_SAMPLE_shift = 8,
ZPASS_INCREMENT_DISABLE_bit = 1 << 11,
DB_RENDER_OVERRIDE = 0x00028d10,
FORCE_HIZ_ENABLE_mask = 0x03 << 0,
FORCE_HIZ_ENABLE_shift = 0,
FORCE_OFF = 0x00,
FORCE_ENABLE = 0x01,
FORCE_DISABLE = 0x02,
FORCE_RESERVED = 0x03,
FORCE_HIS_ENABLE0_mask = 0x03 << 2,
FORCE_HIS_ENABLE0_shift = 2,
/* FORCE_OFF = 0x00, */
/* FORCE_ENABLE = 0x01, */
/* FORCE_DISABLE = 0x02, */
/* FORCE_RESERVED = 0x03, */
FORCE_HIS_ENABLE1_mask = 0x03 << 4,
FORCE_HIS_ENABLE1_shift = 4,
/* FORCE_OFF = 0x00, */
/* FORCE_ENABLE = 0x01, */
/* FORCE_DISABLE = 0x02, */
/* FORCE_RESERVED = 0x03, */
FORCE_SHADER_Z_ORDER_bit = 1 << 6,
FAST_Z_DISABLE_bit = 1 << 7,
FAST_STENCIL_DISABLE_bit = 1 << 8,
NOOP_CULL_DISABLE_bit = 1 << 9,
FORCE_COLOR_KILL_bit = 1 << 10,
FORCE_Z_READ_bit = 1 << 11,
FORCE_STENCIL_READ_bit = 1 << 12,
FORCE_FULL_Z_RANGE_mask = 0x03 << 13,
FORCE_FULL_Z_RANGE_shift = 13,
/* FORCE_OFF = 0x00, */
/* FORCE_ENABLE = 0x01, */
/* FORCE_DISABLE = 0x02, */
/* FORCE_RESERVED = 0x03, */
FORCE_QC_SMASK_CONFLICT_bit = 1 << 15,
DISABLE_VIEWPORT_CLAMP_bit = 1 << 16,
IGNORE_SC_ZRANGE_bit = 1 << 17,
DB_HTILE_SURFACE = 0x00028d24,
HTILE_WIDTH_bit = 1 << 0,
HTILE_HEIGHT_bit = 1 << 1,
LINEAR_bit = 1 << 2,
FULL_CACHE_bit = 1 << 3,
HTILE_USES_PRELOAD_WIN_bit = 1 << 4,
PRELOAD_bit = 1 << 5,
PREFETCH_WIDTH_mask = 0x3f << 6,
PREFETCH_WIDTH_shift = 6,
PREFETCH_HEIGHT_mask = 0x3f << 12,
PREFETCH_HEIGHT_shift = 12,
DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c,
COMPAREFUNC1_mask = 0x07 << 0,
COMPAREFUNC1_shift = 0,
/* REF_NEVER = 0x00, */
/* REF_LESS = 0x01, */
/* REF_EQUAL = 0x02, */
/* REF_LEQUAL = 0x03, */
/* REF_GREATER = 0x04, */
/* REF_NOTEQUAL = 0x05, */
/* REF_GEQUAL = 0x06, */
/* REF_ALWAYS = 0x07, */
COMPAREVALUE1_mask = 0xff << 4,
COMPAREVALUE1_shift = 4,
COMPAREMASK1_mask = 0xff << 12,
COMPAREMASK1_shift = 12,
ENABLE1_bit = 1 << 24,
DB_PRELOAD_CONTROL = 0x00028d30,
START_X_mask = 0xff << 0,
START_X_shift = 0,
START_Y_mask = 0xff << 8,
START_Y_shift = 8,
MAX_X_mask = 0xff << 16,
MAX_X_shift = 16,
MAX_Y_mask = 0xff << 24,
MAX_Y_shift = 24,
DB_PREFETCH_LIMIT = 0x00028d34,
DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0,
DEPTH_HEIGHT_TILE_MAX_shift = 0,
PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8,
POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0,
POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0,
POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8,
PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc,
PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00,
PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04,
PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08,
PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c,
PA_CL_POINT_X_RAD = 0x00028e10,
PA_CL_POINT_Y_RAD = 0x00028e14,
PA_CL_POINT_SIZE = 0x00028e18,
PA_CL_POINT_CULL_RAD = 0x00028e1c,
PA_CL_UCP_0_X = 0x00028e20,
PA_CL_UCP_0_X_num = 6,
PA_CL_UCP_0_X_offset = 16,
PA_CL_UCP_0_Y = 0x00028e24,
PA_CL_UCP_0_Y_num = 6,
PA_CL_UCP_0_Y_offset = 16,
PA_CL_UCP_0_Z = 0x00028e28,
PA_CL_UCP_0_Z_num = 6,
PA_CL_UCP_0_Z_offset = 16,
SQ_ALU_CONSTANT0_0 = 0x00030000,
SQ_ALU_CONSTANT1_0 = 0x00030004,
SQ_ALU_CONSTANT2_0 = 0x00030008,
SQ_ALU_CONSTANT3_0 = 0x0003000c,
SQ_VTX_CONSTANT_WORD0_0 = 0x00038000,
SQ_TEX_RESOURCE_WORD0_0 = 0x00038000,
DIM_mask = 0x07 << 0,
DIM_shift = 0,
SQ_TEX_DIM_1D = 0x00,
SQ_TEX_DIM_2D = 0x01,
SQ_TEX_DIM_3D = 0x02,
SQ_TEX_DIM_CUBEMAP = 0x03,
SQ_TEX_DIM_1D_ARRAY = 0x04,
SQ_TEX_DIM_2D_ARRAY = 0x05,
SQ_TEX_DIM_2D_MSAA = 0x06,
SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07,
SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3,
SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3,
TILE_TYPE_bit = 1 << 7,
PITCH_mask = 0x7ff << 8,
PITCH_shift = 8,
TEX_WIDTH_mask = 0x1fff << 19,
TEX_WIDTH_shift = 19,
SQ_VTX_CONSTANT_WORD1_0 = 0x00038004,
SQ_TEX_RESOURCE_WORD1_0 = 0x00038004,
TEX_HEIGHT_mask = 0x1fff << 0,
TEX_HEIGHT_shift = 0,
TEX_DEPTH_mask = 0x1fff << 13,
TEX_DEPTH_shift = 13,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26,
SQ_VTX_CONSTANT_WORD2_0 = 0x00038008,
BASE_ADDRESS_HI_mask = 0xff << 0,
BASE_ADDRESS_HI_shift = 0,
SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8,
SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8,
SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20,
SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26,
SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26,
/* SQ_NUM_FORMAT_NORM = 0x00, */
/* SQ_NUM_FORMAT_INT = 0x01, */
/* SQ_NUM_FORMAT_SCALED = 0x02, */
SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28,
SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29,
SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30,
SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30,
/* SQ_ENDIAN_NONE = 0x00, */
/* SQ_ENDIAN_8IN16 = 0x01, */
/* SQ_ENDIAN_8IN32 = 0x02, */
SQ_TEX_RESOURCE_WORD2_0 = 0x00038008,
SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c,
MEM_REQUEST_SIZE_mask = 0x03 << 0,
MEM_REQUEST_SIZE_shift = 0,
SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c,
SQ_TEX_RESOURCE_WORD4_0 = 0x00038010,
FORMAT_COMP_X_mask = 0x03 << 0,
FORMAT_COMP_X_shift = 0,
SQ_FORMAT_COMP_UNSIGNED = 0x00,
SQ_FORMAT_COMP_SIGNED = 0x01,
SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02,
FORMAT_COMP_Y_mask = 0x03 << 2,
FORMAT_COMP_Y_shift = 2,
/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
/* SQ_FORMAT_COMP_SIGNED = 0x01, */
/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
FORMAT_COMP_Z_mask = 0x03 << 4,
FORMAT_COMP_Z_shift = 4,
/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
/* SQ_FORMAT_COMP_SIGNED = 0x01, */
/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
FORMAT_COMP_W_mask = 0x03 << 6,
FORMAT_COMP_W_shift = 6,
/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
/* SQ_FORMAT_COMP_SIGNED = 0x01, */
/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8,
SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8,
/* SQ_NUM_FORMAT_NORM = 0x00, */
/* SQ_NUM_FORMAT_INT = 0x01, */
/* SQ_NUM_FORMAT_SCALED = 0x02, */
SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10,
SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11,
SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12,
SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12,
/* SQ_ENDIAN_NONE = 0x00, */
/* SQ_ENDIAN_8IN16 = 0x01, */
/* SQ_ENDIAN_8IN32 = 0x02, */
REQUEST_SIZE_mask = 0x03 << 14,
REQUEST_SIZE_shift = 14,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25,
/* SQ_SEL_X = 0x00, */
/* SQ_SEL_Y = 0x01, */
/* SQ_SEL_Z = 0x02, */
/* SQ_SEL_W = 0x03, */
/* SQ_SEL_0 = 0x04, */
/* SQ_SEL_1 = 0x05, */
BASE_LEVEL_mask = 0x0f << 28,
BASE_LEVEL_shift = 28,
SQ_TEX_RESOURCE_WORD5_0 = 0x00038014,
LAST_LEVEL_mask = 0x0f << 0,
LAST_LEVEL_shift = 0,
BASE_ARRAY_mask = 0x1fff << 4,
BASE_ARRAY_shift = 4,
LAST_ARRAY_mask = 0x1fff << 17,
LAST_ARRAY_shift = 17,
SQ_TEX_RESOURCE_WORD6_0 = 0x00038018,
MPEG_CLAMP_mask = 0x03 << 0,
MPEG_CLAMP_shift = 0,
SQ_TEX_MPEG_CLAMP_OFF = 0x00,
SQ_TEX_MPEG_9 = 0x01,
SQ_TEX_MPEG_10 = 0x02,
PERF_MODULATION_mask = 0x07 << 5,
PERF_MODULATION_shift = 5,
INTERLACED_bit = 1 << 8,
SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30,
SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30,
SQ_TEX_VTX_INVALID_TEXTURE = 0x00,
SQ_TEX_VTX_INVALID_BUFFER = 0x01,
SQ_TEX_VTX_VALID_TEXTURE = 0x02,
SQ_TEX_VTX_VALID_BUFFER = 0x03,
SQ_VTX_CONSTANT_WORD6_0 = 0x00038018,
SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30,
SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30,
/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */
/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */
/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */
/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */
SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000,
SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0,
SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0,
SQ_TEX_WRAP = 0x00,
SQ_TEX_MIRROR = 0x01,
SQ_TEX_CLAMP_LAST_TEXEL = 0x02,
SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03,
SQ_TEX_CLAMP_HALF_BORDER = 0x04,
SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05,
SQ_TEX_CLAMP_BORDER = 0x06,
SQ_TEX_MIRROR_ONCE_BORDER = 0x07,
CLAMP_Y_mask = 0x07 << 3,
CLAMP_Y_shift = 3,
/* SQ_TEX_WRAP = 0x00, */
/* SQ_TEX_MIRROR = 0x01, */
/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
/* SQ_TEX_CLAMP_BORDER = 0x06, */
/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
CLAMP_Z_mask = 0x07 << 6,
CLAMP_Z_shift = 6,
/* SQ_TEX_WRAP = 0x00, */
/* SQ_TEX_MIRROR = 0x01, */
/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
/* SQ_TEX_CLAMP_BORDER = 0x06, */
/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
XY_MAG_FILTER_mask = 0x07 << 9,
XY_MAG_FILTER_shift = 9,
SQ_TEX_XY_FILTER_POINT = 0x00,
SQ_TEX_XY_FILTER_BILINEAR = 0x01,
SQ_TEX_XY_FILTER_BICUBIC = 0x02,
XY_MIN_FILTER_mask = 0x07 << 12,
XY_MIN_FILTER_shift = 12,
/* SQ_TEX_XY_FILTER_POINT = 0x00, */
/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */
/* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */
Z_FILTER_mask = 0x03 << 15,
Z_FILTER_shift = 15,
SQ_TEX_Z_FILTER_NONE = 0x00,
SQ_TEX_Z_FILTER_POINT = 0x01,
SQ_TEX_Z_FILTER_LINEAR = 0x02,
MIP_FILTER_mask = 0x03 << 17,
MIP_FILTER_shift = 17,
/* SQ_TEX_Z_FILTER_NONE = 0x00, */
/* SQ_TEX_Z_FILTER_POINT = 0x01, */
/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */
BORDER_COLOR_TYPE_mask = 0x03 << 22,
BORDER_COLOR_TYPE_shift = 22,
SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00,
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01,
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02,
SQ_TEX_BORDER_COLOR_REGISTER = 0x03,
POINT_SAMPLING_CLAMP_bit = 1 << 24,
TEX_ARRAY_OVERRIDE_bit = 1 << 25,
DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26,
DEPTH_COMPARE_FUNCTION_shift = 26,
SQ_TEX_DEPTH_COMPARE_NEVER = 0x00,
SQ_TEX_DEPTH_COMPARE_LESS = 0x01,
SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02,
SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03,
SQ_TEX_DEPTH_COMPARE_GREATER = 0x04,
SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05,
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06,
SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07,
CHROMA_KEY_mask = 0x03 << 29,
CHROMA_KEY_shift = 29,
SQ_TEX_CHROMA_KEY_DISABLED = 0x00,
SQ_TEX_CHROMA_KEY_KILL = 0x01,
SQ_TEX_CHROMA_KEY_BLEND = 0x02,
LOD_USES_MINOR_AXIS_bit = 1 << 31,
SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004,
MIN_LOD_mask = 0x3ff << 0,
MIN_LOD_shift = 0,
MAX_LOD_mask = 0x3ff << 10,
MAX_LOD_shift = 10,
SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20,
SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20,
SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008,
LOD_BIAS_SEC_mask = 0xfff << 0,
LOD_BIAS_SEC_shift = 0,
MC_COORD_TRUNCATE_bit = 1 << 12,
SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13,
HIGH_PRECISION_FILTER_bit = 1 << 14,
PERF_MIP_mask = 0x07 << 15,
PERF_MIP_shift = 15,
PERF_Z_mask = 0x03 << 18,
PERF_Z_shift = 18,
FETCH_4_bit = 1 << 26,
SAMPLE_IS_PCF_bit = 1 << 27,
SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
SQ_VTX_BASE_VTX_LOC = 0x0003cff0,
SQ_VTX_START_INST_LOC = 0x0003cff4,
SQ_LOOP_CONST_DX10_0 = 0x0003e200,
SQ_LOOP_CONST_0 = 0x0003e200,
SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0,
SQ_LOOP_CONST_0__COUNT_shift = 0,
INIT_mask = 0xfff << 12,
INIT_shift = 12,
INC_mask = 0xff << 24,
INC_shift = 24,
SQ_BOOL_CONST_0 = 0x0003e380,
SQ_BOOL_CONST_0_num = 3,
 
} ;
 
#endif /* _AUTOREGS */
 
/drivers/video/drm/radeon/r600_reg_r6xx.h
0,0 → 1,504
/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
 
#ifndef _R600_REG_R6xx_H_
#define _R600_REG_R6xx_H_
 
/*
* Registers for R6xx chips that are not documented yet
*/
 
enum {
 
MM_INDEX = 0x0000,
MM_DATA = 0x0004,
 
SRBM_STATUS = 0x0e50,
RLC_RQ_PENDING_bit = 1 << 3,
RCU_RQ_PENDING_bit = 1 << 4,
GRBM_RQ_PENDING_bit = 1 << 5,
HI_RQ_PENDING_bit = 1 << 6,
IO_EXTERN_SIGNAL_bit = 1 << 7,
VMC_BUSY_bit = 1 << 8,
MCB_BUSY_bit = 1 << 9,
MCDZ_BUSY_bit = 1 << 10,
MCDY_BUSY_bit = 1 << 11,
MCDX_BUSY_bit = 1 << 12,
MCDW_BUSY_bit = 1 << 13,
SEM_BUSY_bit = 1 << 14,
SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
PDMA_BUSY_bit = 1 << 16,
IH_BUSY_bit = 1 << 17,
CSC_BUSY_bit = 1 << 20,
CMC7_BUSY_bit = 1 << 21,
CMC6_BUSY_bit = 1 << 22,
CMC5_BUSY_bit = 1 << 23,
CMC4_BUSY_bit = 1 << 24,
CMC3_BUSY_bit = 1 << 25,
CMC2_BUSY_bit = 1 << 26,
CMC1_BUSY_bit = 1 << 27,
CMC0_BUSY_bit = 1 << 28,
BIF_BUSY_bit = 1 << 29,
IDCT_BUSY_bit = 1 << 30,
 
SRBM_READ_ERROR = 0x0e98,
READ_ADDRESS_mask = 0xffff << 2,
READ_ADDRESS_shift = 2,
READ_REQUESTER_HI_bit = 1 << 24,
READ_REQUESTER_GRBM_bit = 1 << 25,
READ_REQUESTER_RCU_bit = 1 << 26,
READ_REQUESTER_RLC_bit = 1 << 27,
READ_ERROR_bit = 1 << 31,
 
SRBM_INT_STATUS = 0x0ea4,
RDERR_INT_STAT_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SRBM_INT_ACK = 0x0ea8,
RDERR_INT_ACK_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
 
/* R6XX_MC_VM_FB_LOCATION = 0x2180, */
 
VENDOR_DEVICE_ID = 0x4000,
 
HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480,
 
/* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */
/* D1GRPH_PITCH = 0x6120, */
/* D1GRPH_Y_END = 0x6138, */
 
GRBM_STATUS = 0x8010,
R600_CMDFIFO_AVAIL_mask = 0x1f << 0,
R700_CMDFIFO_AVAIL_mask = 0xf << 0,
CMDFIFO_AVAIL_shift = 0,
SRBM_RQ_PENDING_bit = 1 << 5,
CP_RQ_PENDING_bit = 1 << 6,
CF_RQ_PENDING_bit = 1 << 7,
PF_RQ_PENDING_bit = 1 << 8,
GRBM_EE_BUSY_bit = 1 << 10,
GRBM_STATUS__VC_BUSY_bit = 1 << 11,
DB03_CLEAN_bit = 1 << 12,
CB03_CLEAN_bit = 1 << 13,
VGT_BUSY_NO_DMA_bit = 1 << 16,
GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
TA03_BUSY_bit = 1 << 18,
GRBM_STATUS__TC_BUSY_bit = 1 << 19,
SX_BUSY_bit = 1 << 20,
SH_BUSY_bit = 1 << 21,
SPI03_BUSY_bit = 1 << 22,
SMX_BUSY_bit = 1 << 23,
SC_BUSY_bit = 1 << 24,
PA_BUSY_bit = 1 << 25,
DB03_BUSY_bit = 1 << 26,
CR_BUSY_bit = 1 << 27,
CP_COHERENCY_BUSY_bit = 1 << 28,
GRBM_STATUS__CP_BUSY_bit = 1 << 29,
CB03_BUSY_bit = 1 << 30,
GUI_ACTIVE_bit = 1 << 31,
GRBM_STATUS2 = 0x8014,
CR_CLEAN_bit = 1 << 0,
SMX_CLEAN_bit = 1 << 1,
SPI0_BUSY_bit = 1 << 8,
SPI1_BUSY_bit = 1 << 9,
SPI2_BUSY_bit = 1 << 10,
SPI3_BUSY_bit = 1 << 11,
TA0_BUSY_bit = 1 << 12,
TA1_BUSY_bit = 1 << 13,
TA2_BUSY_bit = 1 << 14,
TA3_BUSY_bit = 1 << 15,
DB0_BUSY_bit = 1 << 16,
DB1_BUSY_bit = 1 << 17,
DB2_BUSY_bit = 1 << 18,
DB3_BUSY_bit = 1 << 19,
CB0_BUSY_bit = 1 << 20,
CB1_BUSY_bit = 1 << 21,
CB2_BUSY_bit = 1 << 22,
CB3_BUSY_bit = 1 << 23,
GRBM_SOFT_RESET = 0x8020,
SOFT_RESET_CP_bit = 1 << 0,
SOFT_RESET_CB_bit = 1 << 1,
SOFT_RESET_CR_bit = 1 << 2,
SOFT_RESET_DB_bit = 1 << 3,
SOFT_RESET_PA_bit = 1 << 5,
SOFT_RESET_SC_bit = 1 << 6,
SOFT_RESET_SMX_bit = 1 << 7,
SOFT_RESET_SPI_bit = 1 << 8,
SOFT_RESET_SH_bit = 1 << 9,
SOFT_RESET_SX_bit = 1 << 10,
SOFT_RESET_TC_bit = 1 << 11,
SOFT_RESET_TA_bit = 1 << 12,
SOFT_RESET_VC_bit = 1 << 13,
SOFT_RESET_VGT_bit = 1 << 14,
SOFT_RESET_GRBM_GCA_bit = 1 << 15,
 
WAIT_UNTIL = 0x8040,
WAIT_CP_DMA_IDLE_bit = 1 << 8,
WAIT_CMDFIFO_bit = 1 << 10,
WAIT_2D_IDLE_bit = 1 << 14,
WAIT_3D_IDLE_bit = 1 << 15,
WAIT_2D_IDLECLEAN_bit = 1 << 16,
WAIT_3D_IDLECLEAN_bit = 1 << 17,
WAIT_EXTERN_SIG_bit = 1 << 19,
CMDFIFO_ENTRIES_mask = 0x1f << 20,
CMDFIFO_ENTRIES_shift = 20,
 
GRBM_READ_ERROR = 0x8058,
/* READ_ADDRESS_mask = 0xffff << 2, */
/* READ_ADDRESS_shift = 2, */
READ_REQUESTER_SRBM_bit = 1 << 28,
READ_REQUESTER_CP_bit = 1 << 29,
READ_REQUESTER_WU_POLL_bit = 1 << 30,
/* READ_ERROR_bit = 1 << 31, */
 
SCRATCH_REG0 = 0x8500,
SCRATCH_REG1 = 0x8504,
SCRATCH_REG2 = 0x8508,
SCRATCH_REG3 = 0x850c,
SCRATCH_REG4 = 0x8510,
SCRATCH_REG5 = 0x8514,
SCRATCH_REG6 = 0x8518,
SCRATCH_REG7 = 0x851c,
SCRATCH_UMSK = 0x8540,
SCRATCH_ADDR = 0x8544,
 
CP_COHER_CNTL = 0x85f0,
DEST_BASE_0_ENA_bit = 1 << 0,
DEST_BASE_1_ENA_bit = 1 << 1,
SO0_DEST_BASE_ENA_bit = 1 << 2,
SO1_DEST_BASE_ENA_bit = 1 << 3,
SO2_DEST_BASE_ENA_bit = 1 << 4,
SO3_DEST_BASE_ENA_bit = 1 << 5,
CB0_DEST_BASE_ENA_bit = 1 << 6,
CB1_DEST_BASE_ENA_bit = 1 << 7,
CB2_DEST_BASE_ENA_bit = 1 << 8,
CB3_DEST_BASE_ENA_bit = 1 << 9,
CB4_DEST_BASE_ENA_bit = 1 << 10,
CB5_DEST_BASE_ENA_bit = 1 << 11,
CB6_DEST_BASE_ENA_bit = 1 << 12,
CB7_DEST_BASE_ENA_bit = 1 << 13,
DB_DEST_BASE_ENA_bit = 1 << 14,
CR_DEST_BASE_ENA_bit = 1 << 15,
TC_ACTION_ENA_bit = 1 << 23,
VC_ACTION_ENA_bit = 1 << 24,
CB_ACTION_ENA_bit = 1 << 25,
DB_ACTION_ENA_bit = 1 << 26,
SH_ACTION_ENA_bit = 1 << 27,
SMX_ACTION_ENA_bit = 1 << 28,
CR0_ACTION_ENA_bit = 1 << 29,
CR1_ACTION_ENA_bit = 1 << 30,
CR2_ACTION_ENA_bit = 1 << 31,
CP_COHER_SIZE = 0x85f4,
CP_COHER_BASE = 0x85f8,
CP_COHER_STATUS = 0x85fc,
MATCHING_GFX_CNTX_mask = 0xff << 0,
MATCHING_GFX_CNTX_shift = 0,
MATCHING_CR_CNTX_mask = 0xffff << 8,
MATCHING_CR_CNTX_shift = 8,
STATUS_bit = 1 << 31,
 
CP_STALLED_STAT1 = 0x8674,
RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
CP_STALLED_STAT2 = 0x8678,
PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
CP_BUSY_STAT = 0x867c,
REG_BUS_FIFO_BUSY_bit = 1 << 0,
RING_FETCHING_DATA_bit = 1 << 1,
INDR1_FETCHING_DATA_bit = 1 << 2,
INDR2_FETCHING_DATA_bit = 1 << 3,
STATE_FETCHING_DATA_bit = 1 << 4,
PRED_FETCHING_DATA_bit = 1 << 5,
COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
PFP_PARSING_PACKETS_bit = 1 << 7,
ME_PARSING_PACKETS_bit = 1 << 8,
RCIU_PFP_BUSY_bit = 1 << 9,
RCIU_ME_BUSY_bit = 1 << 10,
OUTSTANDING_READ_TAGS_bit = 1 << 11,
SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
SEM_FAILED_AND_HOLDING_bit = 1 << 13,
SEM_POLLING_FOR_PASS_bit = 1 << 14,
_3D_BUSY_bit = 1 << 15,
_2D_BUSY_bit = 1 << 16,
CP_STAT = 0x8680,
CSF_RING_BUSY_bit = 1 << 0,
CSF_WPTR_POLL_BUSY_bit = 1 << 1,
CSF_INDIRECT1_BUSY_bit = 1 << 2,
CSF_INDIRECT2_BUSY_bit = 1 << 3,
CSF_STATE_BUSY_bit = 1 << 4,
CSF_PREDICATE_BUSY_bit = 1 << 5,
CSF_BUSY_bit = 1 << 6,
MIU_RDREQ_BUSY_bit = 1 << 7,
MIU_WRREQ_BUSY_bit = 1 << 8,
ROQ_RING_BUSY_bit = 1 << 9,
ROQ_INDIRECT1_BUSY_bit = 1 << 10,
ROQ_INDIRECT2_BUSY_bit = 1 << 11,
ROQ_STATE_BUSY_bit = 1 << 12,
ROQ_PREDICATE_BUSY_bit = 1 << 13,
ROQ_ALIGN_BUSY_bit = 1 << 14,
PFP_BUSY_bit = 1 << 15,
MEQ_BUSY_bit = 1 << 16,
ME_BUSY_bit = 1 << 17,
QUERY_BUSY_bit = 1 << 18,
SEMAPHORE_BUSY_bit = 1 << 19,
INTERRUPT_BUSY_bit = 1 << 20,
SURFACE_SYNC_BUSY_bit = 1 << 21,
DMA_BUSY_bit = 1 << 22,
RCIU_BUSY_bit = 1 << 23,
CP_STAT__CP_BUSY_bit = 1 << 31,
 
CP_ME_CNTL = 0x86d8,
ME_STATMUX_mask = 0xff << 0,
ME_STATMUX_shift = 0,
ME_HALT_bit = 1 << 28,
CP_ME_STATUS = 0x86dc,
 
CP_RB_RPTR = 0x8700,
RB_RPTR_mask = 0xfffff << 0,
RB_RPTR_shift = 0,
CP_RB_WPTR_DELAY = 0x8704,
PRE_WRITE_TIMER_mask = 0xfffffff << 0,
PRE_WRITE_TIMER_shift = 0,
PRE_WRITE_LIMIT_mask = 0x0f << 28,
PRE_WRITE_LIMIT_shift = 28,
 
CP_ROQ_RB_STAT = 0x8780,
ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
ROQ_RPTR_PRIMARY_shift = 0,
ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
ROQ_WPTR_PRIMARY_shift = 16,
CP_ROQ_IB1_STAT = 0x8784,
ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT1_shift = 0,
ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT1_shift = 16,
CP_ROQ_IB2_STAT = 0x8788,
ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT2_shift = 0,
ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT2_shift = 16,
 
CP_MEQ_STAT = 0x8794,
MEQ_RPTR_mask = 0x3ff << 0,
MEQ_RPTR_shift = 0,
MEQ_WPTR_mask = 0x3ff << 16,
MEQ_WPTR_shift = 16,
 
CC_GC_SHADER_PIPE_CONFIG = 0x8950,
INACTIVE_QD_PIPES_mask = 0xff << 8,
INACTIVE_QD_PIPES_shift = 8,
R6XX_MAX_QD_PIPES = 8,
INACTIVE_SIMDS_mask = 0xff << 16,
INACTIVE_SIMDS_shift = 16,
R6XX_MAX_SIMDS = 8,
GC_USER_SHADER_PIPE_CONFIG = 0x8954,
 
VC_ENHANCE = 0x9714,
DB_DEBUG = 0x9830,
PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
 
DB_WATERMARKS = 0x00009838,
DEPTH_FREE_mask = 0x1f << 0,
DEPTH_FREE_shift = 0,
DEPTH_FLUSH_mask = 0x3f << 5,
DEPTH_FLUSH_shift = 5,
FORCE_SUMMARIZE_mask = 0x0f << 11,
FORCE_SUMMARIZE_shift = 11,
DEPTH_PENDING_FREE_mask = 0x1f << 15,
DEPTH_PENDING_FREE_shift = 15,
DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
DEPTH_CACHELINE_FREE_shift = 20,
EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
LATE_Z_PANIC_DISABLE_bit = 1 << 26,
RE_Z_PANIC_DISABLE_bit = 1 << 27,
DB_EXTRA_DEBUG_mask = 0x0f << 28,
DB_EXTRA_DEBUG_shift = 28,
 
CP_RB_BASE = 0xc100,
CP_RB_CNTL = 0xc104,
RB_BUFSZ_mask = 0x3f << 0,
CP_RB_WPTR = 0xc114,
RB_WPTR_mask = 0xfffff << 0,
RB_WPTR_shift = 0,
CP_RB_RPTR_WR = 0xc108,
RB_RPTR_WR_mask = 0xfffff << 0,
RB_RPTR_WR_shift = 0,
 
CP_INT_STATUS = 0xc128,
DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SEM_SIGNAL_INT_STAT_bit = 1 << 18,
CNTX_BUSY_INT_STAT_bit = 1 << 19,
CNTX_EMPTY_INT_STAT_bit = 1 << 20,
WAITMEM_SEM_INT_STAT_bit = 1 << 21,
PRIV_INSTR_INT_STAT_bit = 1 << 22,
PRIV_REG_INT_STAT_bit = 1 << 23,
OPCODE_ERROR_INT_STAT_bit = 1 << 24,
SCRATCH_INT_STAT_bit = 1 << 25,
TIME_STAMP_INT_STAT_bit = 1 << 26,
RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
DMA_INT_STAT_bit = 1 << 28,
IB2_INT_STAT_bit = 1 << 29,
IB1_INT_STAT_bit = 1 << 30,
RB_INT_STAT_bit = 1 << 31,
 
/* SX_ALPHA_TEST_CONTROL = 0x00028410, */
ALPHA_FUNC__REF_NEVER = 0,
ALPHA_FUNC__REF_ALWAYS = 7,
/* DB_SHADER_CONTROL = 0x0002880c, */
Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
/* PA_SU_SC_MODE_CNTL = 0x00028814, */
/* POLY_MODE_mask = 0x03 << 3, */
POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
/* POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, */
POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
/* DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, */
DB_ALPHA_TO_MASK = 0x00028d44,
ALPHA_TO_MASK_ENABLE = 1 << 0,
ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET0_shift = 8,
ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET1_shift = 10,
ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET2_shift = 12,
ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET3_shift = 14,
 
/* SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, */
/* SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, */
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
FMT_1 = 37, FMT_GB_GR=39,
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
FMT_32_32_32_FLOAT=48,
 
/* High level register file lengths */
SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
SQ_ALU_CONSTANT_ps_num = 256,
SQ_ALU_CONSTANT_vs_num = 256,
SQ_ALU_CONSTANT_all_num = 512,
SQ_ALU_CONSTANT_offset = 16,
SQ_ALU_CONSTANT_ps = 0,
SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_TEX_RESOURCE_ps_num = 160,
SQ_TEX_RESOURCE_vs_num = 160,
SQ_TEX_RESOURCE_fs_num = 16,
SQ_TEX_RESOURCE_gs_num = 160,
SQ_TEX_RESOURCE_all_num = 496,
SQ_TEX_RESOURCE_offset = 28,
SQ_TEX_RESOURCE_ps = 0,
SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_VTX_RESOURCE_ps_num = 160,
SQ_VTX_RESOURCE_vs_num = 160,
SQ_VTX_RESOURCE_fs_num = 16,
SQ_VTX_RESOURCE_gs_num = 160,
SQ_VTX_RESOURCE_all_num = 496,
SQ_VTX_RESOURCE_offset = 28,
SQ_VTX_RESOURCE_ps = 0,
SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
SQ_TEX_SAMPLER_WORD_ps_num = 18,
SQ_TEX_SAMPLER_WORD_vs_num = 18,
SQ_TEX_SAMPLER_WORD_gs_num = 18,
SQ_TEX_SAMPLER_WORD_all_num = 54,
SQ_TEX_SAMPLER_WORD_offset = 12,
SQ_TEX_SAMPLER_WORD_ps = 0,
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
SQ_LOOP_CONST_ps_num = 32,
SQ_LOOP_CONST_vs_num = 32,
SQ_LOOP_CONST_gs_num = 32,
SQ_LOOP_CONST_all_num = 96,
SQ_LOOP_CONST_offset = 4,
SQ_LOOP_CONST_ps = 0,
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */
SQ_BOOL_CONST_ps_num = 1,
SQ_BOOL_CONST_vs_num = 1,
SQ_BOOL_CONST_gs_num = 1,
SQ_BOOL_CONST_all_num = 3,
SQ_BOOL_CONST_offset = 4,
SQ_BOOL_CONST_ps = 0,
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num
};
 
 
#endif
/drivers/video/drm/radeon/radeon.h
159,6 → 159,7
* symbol;
*/
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
/* RADEON_IB_POOL_SIZE must be a power of 2 */
#define RADEON_IB_POOL_SIZE 16
#define RADEON_DEBUGFS_MAX_NUM_FILES 32
#define RADEONFB_CONN_LIMIT 4
427,11 → 428,12
*/
struct radeon_ib {
struct list_head list;
unsigned long idx;
unsigned idx;
uint64_t gpu_addr;
struct radeon_fence *fence;
uint32_t *ptr;
uint32_t length_dw;
bool free;
};
 
/*
441,10 → 443,9
struct radeon_ib_pool {
// struct mutex mutex;
struct radeon_bo *robj;
struct list_head scheduled_ibs;
struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
bool ready;
DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
unsigned head_id;
};
 
struct radeon_cp {
/drivers/video/drm/radeon/radeon_atombios.c
206,6 → 206,15
*connector_type = DRM_MODE_CONNECTOR_DVID;
}
 
/* Asrock RS600 board lists the DVI port as HDMI */
if ((dev->pdev->device == 0x7941) &&
(dev->pdev->subsystem_vendor == 0x1849) &&
(dev->pdev->subsystem_device == 0x7941)) {
if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
*connector_type = DRM_MODE_CONNECTOR_DVID;
}
 
/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
if ((dev->pdev->device == 0x7941) &&
(dev->pdev->subsystem_vendor == 0x147b) &&
/drivers/video/drm/radeon/radeon_connectors.c
780,7 → 780,7
* connected and the DVI port disconnected. If the edid doesn't
* say HDMI, vice versa.
*/
if (radeon_connector->shared_ddc && connector_status_connected) {
if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
struct drm_device *dev = connector->dev;
struct drm_connector *list_connector;
struct radeon_connector *list_radeon_connector;
1060,8 → 1060,7
return;
}
if (radeon_connector->ddc_bus && i2c_bus->valid) {
if (memcmp(&radeon_connector->ddc_bus->rec, i2c_bus,
sizeof(struct radeon_i2c_bus_rec)) == 0) {
if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
radeon_connector->shared_ddc = true;
shared_ddc = true;
}
/drivers/video/drm/radeon/radeon_device.c
34,6 → 34,7
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "display.h"
 
#include <drm/drm_pciids.h>
 
50,6 → 51,7
int radeon_vram_limit = 0;
int radeon_audio = 0;
 
extern display_t *rdisplay;
 
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
int init_display(struct radeon_device *rdev, videomode_t *mode);
57,6 → 59,7
 
int get_modes(videomode_t *mode, int *count);
int set_user_mode(videomode_t *mode);
int r100_2D_test(struct radeon_device *rdev);
 
 
/* Legacy VGA regions */
957,6 → 960,8
 
u32_t drvEntry(int action, char *cmdline)
{
struct radeon_device *rdev = NULL;
 
struct pci_device_id *ent;
 
int err;
998,6 → 1003,14
 
err = drm_get_dev(&device.pci_dev, ent);
 
rdev = rdisplay->ddev->dev_private;
 
if( (rdev->asic == &r600_asic) ||
(rdev->asic == &rv770_asic))
r600_2D_test(rdev);
else
r100_2D_test(rdev);
 
err = RegService("DISPLAY", display_handler);
 
if( err != 0)
/drivers/video/drm/radeon/radeon_gart.c
109,9 → 109,6
radeon_bo_unreserve(rdev->gart.table.vram.robj);
rdev->gart.table_addr = gpu_addr;
return r;
 
dbgprintf("alloc gart vram: gpu_base %x lin_addr %x\n",
rdev->gart.table_addr, rdev->gart.table.vram.ptr);
}
 
void radeon_gart_table_vram_free(struct radeon_device *rdev)
/drivers/video/drm/radeon/radeon_object.h
144,8 → 144,8
struct list_head *head);
extern int radeon_bo_list_reserve(struct list_head *head);
extern void radeon_bo_list_unreserve(struct list_head *head);
extern int radeon_bo_list_validate(struct list_head *head, void *fence);
extern void radeon_bo_list_unvalidate(struct list_head *head, void *fence);
extern int radeon_bo_list_validate(struct list_head *head);
extern void radeon_bo_list_fence(struct list_head *head, void *fence);
extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
struct vm_area_struct *vma);
extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
/drivers/video/drm/radeon/radeon_ring.c
44,69 → 44,56
{
struct radeon_fence *fence;
struct radeon_ib *nib;
unsigned long i;
int r = 0;
int r = 0, i, c;
 
*ib = NULL;
r = radeon_fence_create(rdev, &fence);
if (r) {
DRM_ERROR("failed to create fence for new IB\n");
dev_err(rdev->dev, "failed to create fence for new IB\n");
return r;
}
mutex_lock(&rdev->ib_pool.mutex);
i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
if (i < RADEON_IB_POOL_SIZE) {
set_bit(i, rdev->ib_pool.alloc_bm);
rdev->ib_pool.ibs[i].length_dw = 0;
*ib = &rdev->ib_pool.ibs[i];
mutex_unlock(&rdev->ib_pool.mutex);
goto out;
for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
i &= (RADEON_IB_POOL_SIZE - 1);
if (rdev->ib_pool.ibs[i].free) {
nib = &rdev->ib_pool.ibs[i];
break;
}
if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
/* we go do nothings here */
mutex_unlock(&rdev->ib_pool.mutex);
DRM_ERROR("all IB allocated none scheduled.\n");
r = -EINVAL;
goto out;
}
/* get the first ib on the scheduled list */
nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
struct radeon_ib, list);
if (nib->fence == NULL) {
/* we go do nothings here */
if (nib == NULL) {
/* This should never happen, it means we allocated all
* IB and haven't scheduled one yet, return EBUSY to
* userspace hoping that on ioctl recall we get better
* luck
*/
dev_err(rdev->dev, "no free indirect buffer !\n");
mutex_unlock(&rdev->ib_pool.mutex);
DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
r = -EINVAL;
goto out;
radeon_fence_unref(&fence);
return -EBUSY;
}
rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
nib->free = false;
if (nib->fence) {
mutex_unlock(&rdev->ib_pool.mutex);
 
r = radeon_fence_wait(nib->fence, false);
if (r) {
DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
(unsigned long)nib->gpu_addr, nib->length_dw);
DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
goto out;
dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
mutex_lock(&rdev->ib_pool.mutex);
nib->free = true;
mutex_unlock(&rdev->ib_pool.mutex);
radeon_fence_unref(&fence);
return r;
}
mutex_lock(&rdev->ib_pool.mutex);
}
radeon_fence_unref(&nib->fence);
 
nib->fence = fence;
nib->length_dw = 0;
 
/* scheduled list is accessed here */
mutex_lock(&rdev->ib_pool.mutex);
list_del(&nib->list);
INIT_LIST_HEAD(&nib->list);
mutex_unlock(&rdev->ib_pool.mutex);
 
*ib = nib;
out:
if (r) {
radeon_fence_unref(&fence);
} else {
(*ib)->fence = fence;
return 0;
}
return r;
}
 
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
{
116,22 → 103,13
if (tmp == NULL) {
return;
}
if (!tmp->fence->emited)
radeon_fence_unref(&tmp->fence);
mutex_lock(&rdev->ib_pool.mutex);
if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
/* IB is scheduled & not signaled don't do anythings */
tmp->free = true;
mutex_unlock(&rdev->ib_pool.mutex);
return;
}
list_del(&tmp->list);
INIT_LIST_HEAD(&tmp->list);
if (tmp->fence)
radeon_fence_unref(&tmp->fence);
 
tmp->length_dw = 0;
clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
mutex_unlock(&rdev->ib_pool.mutex);
}
 
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
{
int r = 0;
138,7 → 116,7
 
if (!ib->length_dw || !rdev->cp.ready) {
/* TODO: Nothings in the ib we should report. */
DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
return -EINVAL;
}
 
151,7 → 129,8
radeon_ring_ib_execute(rdev, ib);
radeon_fence_emit(rdev, ib->fence);
mutex_lock(&rdev->ib_pool.mutex);
list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
/* once scheduled IB is considered free and protected by the fence */
ib->free = true;
mutex_unlock(&rdev->ib_pool.mutex);
radeon_ring_unlock_commit(rdev);
return 0;
168,7 → 147,6
if (rdev->ib_pool.robj)
return 0;
/* Allocate 1M object buffer */
INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
true, RADEON_GEM_DOMAIN_GTT,
&rdev->ib_pool.robj);
199,9 → 177,9
rdev->ib_pool.ibs[i].ptr = ptr + offset;
rdev->ib_pool.ibs[i].idx = i;
rdev->ib_pool.ibs[i].length_dw = 0;
INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
rdev->ib_pool.ibs[i].free = true;
}
bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
rdev->ib_pool.head_id = 0;
rdev->ib_pool.ready = true;
DRM_INFO("radeon: ib pool ready.\n");
if (radeon_debugfs_ib_init(rdev)) {
218,7 → 196,6
return;
}
mutex_lock(&rdev->ib_pool.mutex);
bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
if (rdev->ib_pool.robj) {
r = radeon_bo_reserve(rdev->ib_pool.robj, false);
if (likely(r == 0)) {
372,7 → 349,7
if (ib == NULL) {
return 0;
}
seq_printf(m, "IB %04lu\n", ib->idx);
seq_printf(m, "IB %04u\n", ib->idx);
seq_printf(m, "IB fence %p\n", ib->fence);
seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
for (i = 0; i < ib->length_dw; i++) {
/drivers/video/drm/radeon/rdisplay.c
7,6 → 7,9
#include "radeon_object.h"
#include "display.h"
 
#include "r100d.h"
 
 
display_t *rdisplay;
 
static cursor_t* __stdcall select_cursor(cursor_t *cursor);
267,3 → 270,2146
kfree(info);
}
 
#define PACKET3_PAINT_MULTI 0x9A
# define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define R5XX_GMC_WR_MSK_DIS (1 << 30)
# define R5XX_ROP3_P 0x00f00000
 
#define R5XX_SC_TOP_LEFT 0x16ec
#define R5XX_SC_BOTTOM_RIGHT 0x16f0
# define R5XX_SC_SIGN_MASK_LO 0x8000
# define R5XX_SC_SIGN_MASK_HI 0x80000000
 
#define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
 
 
int r100_2D_test(struct radeon_device *rdev)
{
 
uint32_t pitch;
uint32_t offset;
 
int r;
 
ENTER();
 
pitch = (1024*4)/64;
offset = rdev->mc.vram_location;
 
r = radeon_ring_lock(rdev, 16);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
return r;
}
radeon_ring_write(rdev, PACKET0(R5XX_SC_TOP_LEFT, 0));
radeon_ring_write(rdev, 0);
 
radeon_ring_write(rdev, PACKET0(R5XX_SC_BOTTOM_RIGHT, 0));
radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX |
RADEON_DEFAULT_SC_BOTTOM_MAX);
 
radeon_ring_write(rdev, PACKET0(R5XX_DEFAULT_SC_BOTTOM_RIGHT, 0));
radeon_ring_write(rdev, RADEON_DEFAULT_SC_RIGHT_MAX |
RADEON_DEFAULT_SC_BOTTOM_MAX);
 
radeon_ring_write(rdev, PACKET3(PACKET3_PAINT_MULTI, 4));
radeon_ring_write(rdev, RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
RADEON_GMC_DST_32BPP |
RADEON_GMC_SRC_DATATYPE_COLOR |
R5XX_GMC_CLR_CMP_CNTL_DIS |
R5XX_GMC_WR_MSK_DIS |
R5XX_ROP3_P);
 
radeon_ring_write(rdev, (pitch<<22)|(offset>>10));
radeon_ring_write(rdev, 0x0000FF00);
radeon_ring_write(rdev, (64<<16)|64);
radeon_ring_write(rdev, (128<<16)|128);
 
radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_DMA_GUI_IDLE);
 
radeon_ring_unlock_commit(rdev);
 
LEAVE();
return r;
}
 
 
#include "r600_reg_auto_r6xx.h"
#include "r600_reg_r6xx.h"
#include "r600d.h"
 
const u32 r6xx_default_state[] =
{
0xc0002400,
0x00000000,
0xc0012800,
0x80000000,
0x80000000,
0xc0004600,
0x00000016,
0xc0016800,
0x00000010,
0x00028000,
0xc0016800,
0x00000010,
0x00008000,
0xc0016800,
0x00000542,
0x07000003,
0xc0016800,
0x000005c5,
0x00000000,
0xc0016800,
0x00000363,
0x00000000,
0xc0016800,
0x0000060c,
0x82000000,
0xc0016800,
0x0000060e,
0x01020204,
0xc0016f00,
0x00000000,
0x00000000,
0xc0016f00,
0x00000001,
0x00000000,
0xc0096900,
0x0000022a,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0016900,
0x00000004,
0x00000000,
0xc0016900,
0x0000000a,
0x00000000,
0xc0016900,
0x0000000b,
0x00000000,
0xc0016900,
0x0000010c,
0x00000000,
0xc0016900,
0x0000010d,
0x00000000,
0xc0016900,
0x00000200,
0x00000000,
0xc0016900,
0x00000343,
0x00000060,
0xc0016900,
0x00000344,
0x00000040,
0xc0016900,
0x00000351,
0x0000aa00,
0xc0016900,
0x00000104,
0x00000000,
0xc0016900,
0x0000010e,
0x00000000,
0xc0046900,
0x00000105,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0036900,
0x00000109,
0x00000000,
0x00000000,
0x00000000,
0xc0046900,
0x0000030c,
0x01000000,
0x00000000,
0x00000000,
0x00000000,
0xc0046900,
0x00000048,
0x3f800000,
0x00000000,
0x3f800000,
0x3f800000,
0xc0016900,
0x0000008e,
0x0000000f,
0xc0016900,
0x00000080,
0x00000000,
0xc0016900,
0x00000083,
0x0000ffff,
0xc0016900,
0x00000084,
0x00000000,
0xc0016900,
0x00000085,
0x20002000,
0xc0016900,
0x00000086,
0x00000000,
0xc0016900,
0x00000087,
0x20002000,
0xc0016900,
0x00000088,
0x00000000,
0xc0016900,
0x00000089,
0x20002000,
0xc0016900,
0x0000008a,
0x00000000,
0xc0016900,
0x0000008b,
0x20002000,
0xc0016900,
0x0000008c,
0x00000000,
0xc0016900,
0x00000094,
0x80000000,
0xc0016900,
0x00000095,
0x20002000,
0xc0026900,
0x000000b4,
0x00000000,
0x3f800000,
0xc0016900,
0x00000096,
0x80000000,
0xc0016900,
0x00000097,
0x20002000,
0xc0026900,
0x000000b6,
0x00000000,
0x3f800000,
0xc0016900,
0x00000098,
0x80000000,
0xc0016900,
0x00000099,
0x20002000,
0xc0026900,
0x000000b8,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009a,
0x80000000,
0xc0016900,
0x0000009b,
0x20002000,
0xc0026900,
0x000000ba,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009c,
0x80000000,
0xc0016900,
0x0000009d,
0x20002000,
0xc0026900,
0x000000bc,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009e,
0x80000000,
0xc0016900,
0x0000009f,
0x20002000,
0xc0026900,
0x000000be,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a0,
0x80000000,
0xc0016900,
0x000000a1,
0x20002000,
0xc0026900,
0x000000c0,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a2,
0x80000000,
0xc0016900,
0x000000a3,
0x20002000,
0xc0026900,
0x000000c2,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a4,
0x80000000,
0xc0016900,
0x000000a5,
0x20002000,
0xc0026900,
0x000000c4,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a6,
0x80000000,
0xc0016900,
0x000000a7,
0x20002000,
0xc0026900,
0x000000c6,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a8,
0x80000000,
0xc0016900,
0x000000a9,
0x20002000,
0xc0026900,
0x000000c8,
0x00000000,
0x3f800000,
0xc0016900,
0x000000aa,
0x80000000,
0xc0016900,
0x000000ab,
0x20002000,
0xc0026900,
0x000000ca,
0x00000000,
0x3f800000,
0xc0016900,
0x000000ac,
0x80000000,
0xc0016900,
0x000000ad,
0x20002000,
0xc0026900,
0x000000cc,
0x00000000,
0x3f800000,
0xc0016900,
0x000000ae,
0x80000000,
0xc0016900,
0x000000af,
0x20002000,
0xc0026900,
0x000000ce,
0x00000000,
0x3f800000,
0xc0016900,
0x000000b0,
0x80000000,
0xc0016900,
0x000000b1,
0x20002000,
0xc0026900,
0x000000d0,
0x00000000,
0x3f800000,
0xc0016900,
0x000000b2,
0x80000000,
0xc0016900,
0x000000b3,
0x20002000,
0xc0026900,
0x000000d2,
0x00000000,
0x3f800000,
0xc0016900,
0x00000293,
0x00004010,
0xc0016900,
0x00000300,
0x00000000,
0xc0016900,
0x00000301,
0x00000000,
0xc0016900,
0x00000312,
0xffffffff,
0xc0016900,
0x00000307,
0x00000000,
0xc0016900,
0x00000308,
0x00000000,
0xc0016900,
0x00000283,
0x00000000,
0xc0016900,
0x00000292,
0x00000000,
0xc0066900,
0x0000010f,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0016900,
0x00000206,
0x00000000,
0xc0016900,
0x00000207,
0x00000000,
0xc0016900,
0x00000208,
0x00000000,
0xc0046900,
0x00000303,
0x3f800000,
0x3f800000,
0x3f800000,
0x3f800000,
0xc0016900,
0x00000205,
0x00000004,
0xc0016900,
0x00000280,
0x00000000,
0xc0016900,
0x00000281,
0x00000000,
0xc0016900,
0x0000037e,
0x00000000,
0xc0016900,
0x00000382,
0x00000000,
0xc0016900,
0x00000380,
0x00000000,
0xc0016900,
0x00000383,
0x00000000,
0xc0016900,
0x00000381,
0x00000000,
0xc0016900,
0x00000282,
0x00000008,
0xc0016900,
0x00000302,
0x0000002d,
0xc0016900,
0x0000037f,
0x00000000,
0xc0016900,
0x000001b2,
0x00000000,
0xc0016900,
0x000001b6,
0x00000000,
0xc0016900,
0x000001b7,
0x00000000,
0xc0016900,
0x000001b8,
0x00000000,
0xc0016900,
0x000001b9,
0x00000000,
0xc0016900,
0x00000225,
0x00000000,
0xc0016900,
0x00000229,
0x00000000,
0xc0016900,
0x00000237,
0x00000000,
0xc0016900,
0x00000100,
0x00000800,
0xc0016900,
0x00000101,
0x00000000,
0xc0016900,
0x00000102,
0x00000000,
0xc0016900,
0x000002a8,
0x00000000,
0xc0016900,
0x000002a9,
0x00000000,
0xc0016900,
0x00000103,
0x00000000,
0xc0016900,
0x00000284,
0x00000000,
0xc0016900,
0x00000290,
0x00000000,
0xc0016900,
0x00000285,
0x00000000,
0xc0016900,
0x00000286,
0x00000000,
0xc0016900,
0x00000287,
0x00000000,
0xc0016900,
0x00000288,
0x00000000,
0xc0016900,
0x00000289,
0x00000000,
0xc0016900,
0x0000028a,
0x00000000,
0xc0016900,
0x0000028b,
0x00000000,
0xc0016900,
0x0000028c,
0x00000000,
0xc0016900,
0x0000028d,
0x00000000,
0xc0016900,
0x0000028e,
0x00000000,
0xc0016900,
0x0000028f,
0x00000000,
0xc0016900,
0x000002a1,
0x00000000,
0xc0016900,
0x000002a5,
0x00000000,
0xc0016900,
0x000002ac,
0x00000000,
0xc0016900,
0x000002ad,
0x00000000,
0xc0016900,
0x000002ae,
0x00000000,
0xc0016900,
0x000002c8,
0x00000000,
0xc0016900,
0x00000206,
0x00000100,
0xc0016900,
0x00000204,
0x00010000,
0xc0036e00,
0x00000000,
0x00000012,
0x00000000,
0x00000000,
0xc0016900,
0x0000008f,
0x0000000f,
0xc0016900,
0x000001e8,
0x00000001,
0xc0016900,
0x00000202,
0x00cc0000,
0xc0016900,
0x00000205,
0x00000244,
0xc0016900,
0x00000203,
0x00000210,
0xc0016900,
0x000001b1,
0x00000000,
0xc0016900,
0x00000185,
0x00000000,
0xc0016900,
0x000001b3,
0x00000001,
0xc0016900,
0x000001b4,
0x00000000,
0xc0016900,
0x00000191,
0x00000b00,
0xc0016900,
0x000001b5,
0x00000000,
};
 
 
 
const u32 r7xx_default_state[] =
{
0xc0012800,
0x80000000,
0x80000000,
0xc0004600,
0x00000016,
0xc0016800,
0x00000010,
0x00028000,
0xc0016800,
0x00000010,
0x00008000,
0xc0016800,
0x00000542,
0x07000002,
0xc0016800,
0x000005c5,
0x00000000,
0xc0016800,
0x00000363,
0x00004000,
0xc0016800,
0x0000060c,
0x00000000,
0xc0016800,
0x0000060e,
0x00420204,
0xc0016f00,
0x00000000,
0x00000000,
0xc0016f00,
0x00000001,
0x00000000,
0xc0096900,
0x0000022a,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0016900,
0x00000004,
0x00000000,
0xc0016900,
0x0000000a,
0x00000000,
0xc0016900,
0x0000000b,
0x00000000,
0xc0016900,
0x0000010c,
0x00000000,
0xc0016900,
0x0000010d,
0x00000000,
0xc0016900,
0x00000200,
0x00000000,
0xc0016900,
0x00000343,
0x00000060,
0xc0016900,
0x00000344,
0x00000000,
0xc0016900,
0x00000351,
0x0000aa00,
0xc0016900,
0x00000104,
0x00000000,
0xc0016900,
0x0000010e,
0x00000000,
0xc0046900,
0x00000105,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0046900,
0x0000030c,
0x01000000,
0x00000000,
0x00000000,
0x00000000,
0xc0016900,
0x0000008e,
0x0000000f,
0xc0016900,
0x00000080,
0x00000000,
0xc0016900,
0x00000083,
0x0000ffff,
0xc0016900,
0x00000084,
0x00000000,
0xc0016900,
0x00000085,
0x20002000,
0xc0016900,
0x00000086,
0x00000000,
0xc0016900,
0x00000087,
0x20002000,
0xc0016900,
0x00000088,
0x00000000,
0xc0016900,
0x00000089,
0x20002000,
0xc0016900,
0x0000008a,
0x00000000,
0xc0016900,
0x0000008b,
0x20002000,
0xc0016900,
0x0000008c,
0xaaaaaaaa,
0xc0016900,
0x00000094,
0x80000000,
0xc0016900,
0x00000095,
0x20002000,
0xc0026900,
0x000000b4,
0x00000000,
0x3f800000,
0xc0016900,
0x00000096,
0x80000000,
0xc0016900,
0x00000097,
0x20002000,
0xc0026900,
0x000000b6,
0x00000000,
0x3f800000,
0xc0016900,
0x00000098,
0x80000000,
0xc0016900,
0x00000099,
0x20002000,
0xc0026900,
0x000000b8,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009a,
0x80000000,
0xc0016900,
0x0000009b,
0x20002000,
0xc0026900,
0x000000ba,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009c,
0x80000000,
0xc0016900,
0x0000009d,
0x20002000,
0xc0026900,
0x000000bc,
0x00000000,
0x3f800000,
0xc0016900,
0x0000009e,
0x80000000,
0xc0016900,
0x0000009f,
0x20002000,
0xc0026900,
0x000000be,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a0,
0x80000000,
0xc0016900,
0x000000a1,
0x20002000,
0xc0026900,
0x000000c0,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a2,
0x80000000,
0xc0016900,
0x000000a3,
0x20002000,
0xc0026900,
0x000000c2,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a4,
0x80000000,
0xc0016900,
0x000000a5,
0x20002000,
0xc0026900,
0x000000c4,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a6,
0x80000000,
0xc0016900,
0x000000a7,
0x20002000,
0xc0026900,
0x000000c6,
0x00000000,
0x3f800000,
0xc0016900,
0x000000a8,
0x80000000,
0xc0016900,
0x000000a9,
0x20002000,
0xc0026900,
0x000000c8,
0x00000000,
0x3f800000,
0xc0016900,
0x000000aa,
0x80000000,
0xc0016900,
0x000000ab,
0x20002000,
0xc0026900,
0x000000ca,
0x00000000,
0x3f800000,
0xc0016900,
0x000000ac,
0x80000000,
0xc0016900,
0x000000ad,
0x20002000,
0xc0026900,
0x000000cc,
0x00000000,
0x3f800000,
0xc0016900,
0x000000ae,
0x80000000,
0xc0016900,
0x000000af,
0x20002000,
0xc0026900,
0x000000ce,
0x00000000,
0x3f800000,
0xc0016900,
0x000000b0,
0x80000000,
0xc0016900,
0x000000b1,
0x20002000,
0xc0026900,
0x000000d0,
0x00000000,
0x3f800000,
0xc0016900,
0x000000b2,
0x80000000,
0xc0016900,
0x000000b3,
0x20002000,
0xc0026900,
0x000000d2,
0x00000000,
0x3f800000,
0xc0016900,
0x00000293,
0x00514000,
0xc0016900,
0x00000300,
0x00000000,
0xc0016900,
0x00000301,
0x00000000,
0xc0016900,
0x00000312,
0xffffffff,
0xc0016900,
0x00000307,
0x00000000,
0xc0016900,
0x00000308,
0x00000000,
0xc0016900,
0x00000283,
0x00000000,
0xc0016900,
0x00000292,
0x00000000,
0xc0066900,
0x0000010f,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xc0016900,
0x00000206,
0x00000000,
0xc0016900,
0x00000207,
0x00000000,
0xc0016900,
0x00000208,
0x00000000,
0xc0046900,
0x00000303,
0x3f800000,
0x3f800000,
0x3f800000,
0x3f800000,
0xc0016900,
0x00000205,
0x00000004,
0xc0016900,
0x00000280,
0x00000000,
0xc0016900,
0x00000281,
0x00000000,
0xc0016900,
0x0000037e,
0x00000000,
0xc0016900,
0x00000382,
0x00000000,
0xc0016900,
0x00000380,
0x00000000,
0xc0016900,
0x00000383,
0x00000000,
0xc0016900,
0x00000381,
0x00000000,
0xc0016900,
0x00000282,
0x00000008,
0xc0016900,
0x00000302,
0x0000002d,
0xc0016900,
0x0000037f,
0x00000000,
0xc0016900,
0x000001b2,
0x00000001,
0xc0016900,
0x000001b6,
0x00000000,
0xc0016900,
0x000001b7,
0x00000000,
0xc0016900,
0x000001b8,
0x00000000,
0xc0016900,
0x000001b9,
0x00000000,
0xc0016900,
0x00000225,
0x00000000,
0xc0016900,
0x00000229,
0x00000000,
0xc0016900,
0x00000237,
0x00000000,
0xc0016900,
0x00000100,
0x00000800,
0xc0016900,
0x00000101,
0x00000000,
0xc0016900,
0x00000102,
0x00000000,
0xc0016900,
0x000002a8,
0x00000000,
0xc0016900,
0x000002a9,
0x00000000,
0xc0016900,
0x00000103,
0x00000000,
0xc0016900,
0x00000284,
0x00000000,
0xc0016900,
0x00000290,
0x00000000,
0xc0016900,
0x00000285,
0x00000000,
0xc0016900,
0x00000286,
0x00000000,
0xc0016900,
0x00000287,
0x00000000,
0xc0016900,
0x00000288,
0x00000000,
0xc0016900,
0x00000289,
0x00000000,
0xc0016900,
0x0000028a,
0x00000000,
0xc0016900,
0x0000028b,
0x00000000,
0xc0016900,
0x0000028c,
0x00000000,
0xc0016900,
0x0000028d,
0x00000000,
0xc0016900,
0x0000028e,
0x00000000,
0xc0016900,
0x0000028f,
0x00000000,
0xc0016900,
0x000002a1,
0x00000000,
0xc0016900,
0x000002a5,
0x00000000,
0xc0016900,
0x000002ac,
0x00000000,
0xc0016900,
0x000002ad,
0x00000000,
0xc0016900,
0x000002ae,
0x00000000,
0xc0016900,
0x000002c8,
0x00000000,
0xc0016900,
0x00000206,
0x00000100,
0xc0016900,
0x00000204,
0x00010000,
0xc0036e00,
0x00000000,
0x00000012,
0x00000000,
0x00000000,
0xc0016900,
0x0000008f,
0x0000000f,
0xc0016900,
0x000001e8,
0x00000001,
0xc0016900,
0x00000202,
0x00cc0000,
0xc0016900,
0x00000205,
0x00000244,
0xc0016900,
0x00000203,
0x00000210,
0xc0016900,
0x000001b1,
0x00000000,
0xc0016900,
0x00000185,
0x00000000,
0xc0016900,
0x000001b3,
0x00000001,
0xc0016900,
0x000001b4,
0x00000000,
0xc0016900,
0x00000191,
0x00000b00,
0xc0016900,
0x000001b5,
0x00000000,
};
 
const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
 
 
int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader);
int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader);
 
#define COLOR_8_8_8_8 0x1a
 
/* emits 21 on rv770+, 23 on r600 */
static void
set_render_target(struct radeon_device *rdev, int format,
int w, int h, u64 gpu_addr)
{
u32 cb_color_info;
int pitch, slice;
 
h = (h + 7) & ~7;
if (h < 8)
h = 8;
 
cb_color_info = ((format << 2) | (1 << 27));
pitch = (w / 8) - 1;
slice = ((w * h) / 64) - 1;
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, gpu_addr >> 8);
 
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
radeon_ring_write(rdev, 2 << 0);
}
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, cb_color_info);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
}
 
 
/* emits 5dw */
static void
cp_set_surface_sync(struct radeon_device *rdev,
u32 sync_type, u32 size,
u64 mc_addr)
{
u32 cp_coher_size;
 
if (size == 0xffffffff)
cp_coher_size = 0xffffffff;
else
cp_coher_size = ((size + 255) >> 8);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
radeon_ring_write(rdev, sync_type);
radeon_ring_write(rdev, cp_coher_size);
radeon_ring_write(rdev, mc_addr >> 8);
radeon_ring_write(rdev, 10); /* poll interval */
}
 
/* emits 14 */
static void
set_default_state(struct radeon_device *rdev,
u64 state_gpu_addr, u32 state_len)
{
u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
u64 gpu_addr;
int dwords;
 
switch (rdev->family) {
case CHIP_R600:
num_ps_gprs = 192;
num_vs_gprs = 56;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 136;
num_vs_threads = 48;
num_gs_threads = 4;
num_es_threads = 4;
num_ps_stack_entries = 128;
num_vs_stack_entries = 128;
num_gs_stack_entries = 0;
num_es_stack_entries = 0;
break;
case CHIP_RV630:
case CHIP_RV635:
num_ps_gprs = 84;
num_vs_gprs = 36;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 144;
num_vs_threads = 40;
num_gs_threads = 4;
num_es_threads = 4;
num_ps_stack_entries = 40;
num_vs_stack_entries = 40;
num_gs_stack_entries = 32;
num_es_stack_entries = 16;
break;
case CHIP_RV610:
case CHIP_RV620:
case CHIP_RS780:
case CHIP_RS880:
default:
num_ps_gprs = 84;
num_vs_gprs = 36;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 136;
num_vs_threads = 48;
num_gs_threads = 4;
num_es_threads = 4;
num_ps_stack_entries = 40;
num_vs_stack_entries = 40;
num_gs_stack_entries = 32;
num_es_stack_entries = 16;
break;
case CHIP_RV670:
num_ps_gprs = 144;
num_vs_gprs = 40;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 136;
num_vs_threads = 48;
num_gs_threads = 4;
num_es_threads = 4;
num_ps_stack_entries = 40;
num_vs_stack_entries = 40;
num_gs_stack_entries = 32;
num_es_stack_entries = 16;
break;
case CHIP_RV770:
num_ps_gprs = 192;
num_vs_gprs = 56;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 188;
num_vs_threads = 60;
num_gs_threads = 0;
num_es_threads = 0;
num_ps_stack_entries = 256;
num_vs_stack_entries = 256;
num_gs_stack_entries = 0;
num_es_stack_entries = 0;
break;
case CHIP_RV730:
case CHIP_RV740:
num_ps_gprs = 84;
num_vs_gprs = 36;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 188;
num_vs_threads = 60;
num_gs_threads = 0;
num_es_threads = 0;
num_ps_stack_entries = 128;
num_vs_stack_entries = 128;
num_gs_stack_entries = 0;
num_es_stack_entries = 0;
break;
case CHIP_RV710:
num_ps_gprs = 192;
num_vs_gprs = 56;
num_temp_gprs = 4;
num_gs_gprs = 0;
num_es_gprs = 0;
num_ps_threads = 144;
num_vs_threads = 48;
num_gs_threads = 0;
num_es_threads = 0;
num_ps_stack_entries = 128;
num_vs_stack_entries = 128;
num_gs_stack_entries = 0;
num_es_stack_entries = 0;
break;
}
 
if ((rdev->family == CHIP_RV610) ||
(rdev->family == CHIP_RV620) ||
(rdev->family == CHIP_RS780) ||
(rdev->family == CHIP_RS880) ||
(rdev->family == CHIP_RV710))
sq_config = 0;
else
sq_config = VC_ENABLE;
 
sq_config |= (DX9_CONSTS |
ALU_INST_PREFER_VECTOR |
PS_PRIO(0) |
VS_PRIO(1) |
GS_PRIO(2) |
ES_PRIO(3));
 
sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
NUM_VS_GPRS(num_vs_gprs) |
NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
NUM_ES_GPRS(num_es_gprs));
sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
NUM_VS_THREADS(num_vs_threads) |
NUM_GS_THREADS(num_gs_threads) |
NUM_ES_THREADS(num_es_threads));
sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
/* emit an IB pointing at default state */
dwords = (state_len + 0xf) & ~0xf;
gpu_addr = state_gpu_addr;
 
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
radeon_ring_write(rdev, dwords);
 
radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
/* SQ config */
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
radeon_ring_write(rdev, sq_config);
radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
radeon_ring_write(rdev, sq_thread_resource_mgmt);
radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
}
 
/* emits 12 */
static void
set_scissors(struct radeon_device *rdev, int x1, int y1,
int x2, int y2)
{
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
}
 
static void
draw_auto(struct radeon_device *rdev)
{
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
radeon_ring_write(rdev, DI_PT_RECTLIST);
 
radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
 
radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
radeon_ring_write(rdev, 1);
 
radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
radeon_ring_write(rdev, 3);
radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 
}
 
/* ALU clause insts */
#define SRC0_SEL(x) (x)
#define SRC1_SEL(x) (x)
#define SRC2_SEL(x) (x)
/* src[0-2]_sel */
/* 0-127 GPR */
/* 128-159 kcache constants bank 0 */
/* 160-191 kcache constants bank 1 */
/* 248-255 special SQ_ALU_SRC_* (0, 1, etc.) */
 
#define SRC0_REL(x) (x)
#define SRC1_REL(x) (x)
#define SRC2_REL(x) (x)
/* elem */
#define SRC0_ELEM(x) (x)
#define SRC1_ELEM(x) (x)
#define SRC2_ELEM(x) (x)
#define ELEM_X 0
#define ELEM_Y 1
#define ELEM_Z 2
#define ELEM_W 3
/* neg */
#define SRC0_NEG(x) (x)
#define SRC1_NEG(x) (x)
#define SRC2_NEG(x) (x)
/* im */
#define INDEX_MODE(x) (x) /* SQ_INDEX_* */
/* ps */
#define PRED_SEL(x) (x) /* SQ_PRED_SEL_* */
/* last */
#define LAST(x) (x)
/* abs */
#define SRC0_ABS(x) (x)
#define SRC1_ABS(x) (x)
/* uem */
#define UPDATE_EXECUTE_MASK(x) (x)
/* up */
#define UPDATE_PRED(x) (x)
/* wm */
#define WRITE_MASK(x) (x)
/* fm */
#define FOG_MERGE(x) (x)
/* omod */
#define OMOD(x) (x) /* SQ_ALU_OMOD_* */
/* alu inst */
#define ALU_INST(x) (x) /* SQ_ALU_INST_* */
/*bs */
#define BANK_SWIZZLE(x) (x) /* SQ_ALU_VEC_* */
#define DST_GPR(x) (x)
#define DST_REL(x) (x)
#define DST_ELEM(x) (x)
#define CLAMP(x) (x)
 
#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
(((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
((im) << 26) | ((ps) << 29) | ((last) << 31))
 
/* R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more) */
#define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
(((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \
((dr) << 28) | ((de) << 29) | ((clamp) << 31))
 
#define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
(((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
((dr) << 28) | ((de) << 29) | ((clamp) << 31))
 
/* This is a general chipset macro, but due to selection by chipid typically not usable in static arrays */
/* Fog is NOT USED on R7xx, even if specified. */
#define ALU_DWORD1_OP2(chipid, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
((chipid) < CHIP_RV770 ? \
R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))
 
#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
(((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
((de) << 29) | ((clamp) << 31))
 
/* CF insts */
/* addr */
#define ADDR(x) (x)
/* pc */
#define POP_COUNT(x) (x)
/* const */
#define CF_CONST(x) (x)
/* cond */
#define COND(x) (x) /* SQ_COND_* */
/* count */
#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
/*r7xx */
#define COUNT_3(x) (x)
/* call count */
#define CALL_COUNT(x) (x)
/* eop */
#define END_OF_PROGRAM(x) (x)
/* vpm */
#define VALID_PIXEL_MODE(x) (x)
/* cf inst */
#define CF_INST(x) (x) /* SQ_CF_INST_* */
 
/* wqm */
#define WHOLE_QUAD_MODE(x) (x)
/* barrier */
#define BARRIER(x) (x)
/*kb0 */
#define KCACHE_BANK0(x) (x)
/*kb1 */
#define KCACHE_BANK1(x) (x)
/* km0/1 */
#define KCACHE_MODE0(x) (x)
#define KCACHE_MODE1(x) (x) /* SQ_CF_KCACHE_* */
/* */
#define KCACHE_ADDR0(x) (x)
#define KCACHE_ADDR1(x) (x)
/* uw */
#define USES_WATERFALL(x) (x)
 
#define ARRAY_BASE(x) (x)
/* export pixel */
#define CF_PIXEL_MRT0 0
#define CF_PIXEL_MRT1 1
#define CF_PIXEL_MRT2 2
#define CF_PIXEL_MRT3 3
#define CF_PIXEL_MRT4 4
#define CF_PIXEL_MRT5 5
#define CF_PIXEL_MRT6 6
#define CF_PIXEL_MRT7 7
/* *_FOG: r6xx only */
#define CF_PIXEL_MRT0_FOG 16
#define CF_PIXEL_MRT1_FOG 17
#define CF_PIXEL_MRT2_FOG 18
#define CF_PIXEL_MRT3_FOG 19
#define CF_PIXEL_MRT4_FOG 20
#define CF_PIXEL_MRT5_FOG 21
#define CF_PIXEL_MRT6_FOG 22
#define CF_PIXEL_MRT7_FOG 23
#define CF_PIXEL_Z 61
/* export pos */
#define CF_POS0 60
#define CF_POS1 61
#define CF_POS2 62
#define CF_POS3 63
/* export param */
/* 0...31 */
#define TYPE(x) (x) /* SQ_EXPORT_* */
#if 0
/* type export */
#define SQ_EXPORT_PIXEL 0
#define SQ_EXPORT_POS 1
#define SQ_EXPORT_PARAM 2
/* reserved 3 */
/* type mem */
#define SQ_EXPORT_WRITE 0
#define SQ_EXPORT_WRITE_IND 1
#define SQ_EXPORT_WRITE_ACK 2
#define SQ_EXPORT_WRITE_IND_ACK 3
#endif
 
#define RW_GPR(x) (x)
#define RW_REL(x) (x)
#define ABSOLUTE 0
#define RELATIVE 1
#define INDEX_GPR(x) (x)
#define ELEM_SIZE(x) (x ? (x - 1) : 0)
#define COMP_MASK(x) (x)
#define R6xx_ELEM_LOOP(x) (x)
#define BURST_COUNT(x) (x ? (x - 1) : 0)
 
/* swiz */
#define SRC_SEL_X(x) (x) /* SQ_SEL_* each */
#define SRC_SEL_Y(x) (x)
#define SRC_SEL_Z(x) (x)
#define SRC_SEL_W(x) (x)
 
#define CF_DWORD0(addr) (addr)
/* R7xx has another entry (COUNT3), but that is only used for adding a bit to count. */
/* We allow one more bit for count in the argument of the macro on R7xx instead. */
/* R6xx: [0,7] R7xx: [1,16] */
#define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \
(((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \
((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))
 
#define CF_ALU_DWORD0(addr, kb0, kb1, km0) (((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30))
#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \
(((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31))
 
#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
(((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \
((es) << 30))
/* R7xx apparently doesn't have the ELEM_LOOP entry any more */
/* We still expose it, but ELEM_LOOP is explicitely R6xx now. */
/* TODO: is this just forgotten in the docs, or really not available any more? */
#define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \
(((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \
((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31))
#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \
(((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \
((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \
((wqm) << 30) | ((b) << 31))
 
/* VTX clause insts */
/* vxt insts */
#define VTX_INST(x) (x) /* SQ_VTX_INST_* */
 
/* fetch type */
#define FETCH_TYPE(x) (x) /* SQ_VTX_FETCH_* */
 
#define FETCH_WHOLE_QUAD(x) (x)
#define BUFFER_ID(x) (x)
#define SRC_GPR(x) (x)
#define SRC_REL(x) (x)
#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
 
#define SEMANTIC_ID(x) (x)
#define DST_SEL_X(x) (x)
#define DST_SEL_Y(x) (x)
#define DST_SEL_Z(x) (x)
#define DST_SEL_W(x) (x)
#define USE_CONST_FIELDS(x) (x)
#define DATA_FORMAT(x) (x)
/* num format */
#define NUM_FORMAT_ALL(x) (x) /* SQ_NUM_FORMAT_* */
/* format comp */
#define FORMAT_COMP_ALL(x) (x) /* SQ_FORMAT_COMP_* */
/* sma */
#define SRF_MODE_ALL(x) (x)
#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
#define SRF_MODE_NO_ZERO 1
#define OFFSET(x) (x)
/* endian swap */
#define ENDIAN_SWAP(x) (x) /* SQ_ENDIAN_* */
#define CONST_BUF_NO_STRIDE(x) (x)
/* mf */
#define MEGA_FETCH(x) (x)
 
#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
(((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26))
#define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
(((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))
#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
(((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31))
#define VTX_DWORD2(offset, es, cbns, mf) \
(((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19))
#define VTX_DWORD_PAD 0x00000000
 
 
int R600_solid_vs(struct radeon_device *rdev, uint32_t* shader)
{
int i=0;
 
/* 0 */
shader[i++] = CF_DWORD0(ADDR(4));
shader[i++] = CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
I_COUNT(1),
CALL_COUNT(0),
END_OF_PROGRAM(0),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_VTX),
WHOLE_QUAD_MODE(0),
BARRIER(1));
/* 1 */
shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
TYPE(SQ_EXPORT_POS),
RW_GPR(1),
RW_REL(ABSOLUTE),
INDEX_GPR(0),
ELEM_SIZE(0));
shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
SRC_SEL_Y(SQ_SEL_Y),
SRC_SEL_Z(SQ_SEL_Z),
SRC_SEL_W(SQ_SEL_W),
R6xx_ELEM_LOOP(0),
BURST_COUNT(1),
END_OF_PROGRAM(0),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_EXPORT_DONE),
WHOLE_QUAD_MODE(0),
BARRIER(1));
/* 2 - always export a param whether it's used or not */
shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
TYPE(SQ_EXPORT_PARAM),
RW_GPR(0),
RW_REL(ABSOLUTE),
INDEX_GPR(0),
ELEM_SIZE(0));
shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
SRC_SEL_Y(SQ_SEL_Y),
SRC_SEL_Z(SQ_SEL_Z),
SRC_SEL_W(SQ_SEL_W),
R6xx_ELEM_LOOP(0),
BURST_COUNT(0),
END_OF_PROGRAM(1),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_EXPORT_DONE),
WHOLE_QUAD_MODE(0),
BARRIER(0));
/* 3 - padding */
shader[i++] = 0x00000000;
shader[i++] = 0x00000000;
/* 4/5 */
shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA),
FETCH_WHOLE_QUAD(0),
BUFFER_ID(0),
SRC_GPR(0),
SRC_REL(ABSOLUTE),
SRC_SEL_X(SQ_SEL_X),
MEGA_FETCH_COUNT(8));
shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
DST_REL(0),
DST_SEL_X(SQ_SEL_X),
DST_SEL_Y(SQ_SEL_Y),
DST_SEL_Z(SQ_SEL_0),
DST_SEL_W(SQ_SEL_1),
USE_CONST_FIELDS(0),
DATA_FORMAT(FMT_32_32_FLOAT), /* xxx */
NUM_FORMAT_ALL(SQ_NUM_FORMAT_NORM), /* xxx */
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), /* xxx */
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
ENDIAN_SWAP(ENDIAN_NONE),
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
 
return i;
}
 
int R600_solid_ps(struct radeon_device *rdev, uint32_t* shader)
{
int i=0;
 
/* 0 */
shader[i++] = CF_ALU_DWORD0(ADDR(2),
KCACHE_BANK0(0),
KCACHE_BANK1(0),
KCACHE_MODE0(SQ_CF_KCACHE_NOP));
shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
KCACHE_ADDR0(0),
KCACHE_ADDR1(0),
I_COUNT(4),
USES_WATERFALL(0),
CF_INST(SQ_CF_INST_ALU),
WHOLE_QUAD_MODE(0),
BARRIER(1));
/* 1 */
shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
TYPE(SQ_EXPORT_PIXEL),
RW_GPR(0),
RW_REL(ABSOLUTE),
INDEX_GPR(0),
ELEM_SIZE(1));
shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
SRC_SEL_Y(SQ_SEL_Y),
SRC_SEL_Z(SQ_SEL_Z),
SRC_SEL_W(SQ_SEL_W),
R6xx_ELEM_LOOP(0),
BURST_COUNT(1),
END_OF_PROGRAM(1),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_EXPORT_DONE),
WHOLE_QUAD_MODE(0),
BARRIER(1));
 
/* 2 */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_X),
SRC0_NEG(0),
SRC1_SEL(0),
SRC1_REL(ABSOLUTE),
SRC1_ELEM(ELEM_X),
SRC1_NEG(0),
INDEX_MODE(SQ_INDEX_AR_X),
PRED_SEL(SQ_PRED_SEL_OFF),
LAST(0));
shader[i++] = ALU_DWORD1_OP2(rdev->family,
SRC0_ABS(0),
SRC1_ABS(0),
UPDATE_EXECUTE_MASK(0),
UPDATE_PRED(0),
WRITE_MASK(1),
FOG_MERGE(0),
OMOD(SQ_ALU_OMOD_OFF),
ALU_INST(SQ_OP2_INST_MOV),
BANK_SWIZZLE(SQ_ALU_VEC_012),
DST_GPR(0),
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_X),
CLAMP(1));
/* 3 */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Y),
SRC0_NEG(0),
SRC1_SEL(0),
SRC1_REL(ABSOLUTE),
SRC1_ELEM(ELEM_Y),
SRC1_NEG(0),
INDEX_MODE(SQ_INDEX_AR_X),
PRED_SEL(SQ_PRED_SEL_OFF),
LAST(0));
shader[i++] = ALU_DWORD1_OP2(rdev->family,
SRC0_ABS(0),
SRC1_ABS(0),
UPDATE_EXECUTE_MASK(0),
UPDATE_PRED(0),
WRITE_MASK(1),
FOG_MERGE(0),
OMOD(SQ_ALU_OMOD_OFF),
ALU_INST(SQ_OP2_INST_MOV),
BANK_SWIZZLE(SQ_ALU_VEC_012),
DST_GPR(0),
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Y),
CLAMP(1));
/* 4 */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_Z),
SRC0_NEG(0),
SRC1_SEL(0),
SRC1_REL(ABSOLUTE),
SRC1_ELEM(ELEM_Z),
SRC1_NEG(0),
INDEX_MODE(SQ_INDEX_AR_X),
PRED_SEL(SQ_PRED_SEL_OFF),
LAST(0));
shader[i++] = ALU_DWORD1_OP2(rdev->family,
SRC0_ABS(0),
SRC1_ABS(0),
UPDATE_EXECUTE_MASK(0),
UPDATE_PRED(0),
WRITE_MASK(1),
FOG_MERGE(0),
OMOD(SQ_ALU_OMOD_OFF),
ALU_INST(SQ_OP2_INST_MOV),
BANK_SWIZZLE(SQ_ALU_VEC_012),
DST_GPR(0),
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_Z),
CLAMP(1));
/* 5 */
shader[i++] = ALU_DWORD0(SRC0_SEL(256),
SRC0_REL(ABSOLUTE),
SRC0_ELEM(ELEM_W),
SRC0_NEG(0),
SRC1_SEL(0),
SRC1_REL(ABSOLUTE),
SRC1_ELEM(ELEM_W),
SRC1_NEG(0),
INDEX_MODE(SQ_INDEX_AR_X),
PRED_SEL(SQ_PRED_SEL_OFF),
LAST(1));
shader[i++] = ALU_DWORD1_OP2(rdev->family,
SRC0_ABS(0),
SRC1_ABS(0),
UPDATE_EXECUTE_MASK(0),
UPDATE_PRED(0),
WRITE_MASK(1),
FOG_MERGE(0),
OMOD(SQ_ALU_OMOD_OFF),
ALU_INST(SQ_OP2_INST_MOV),
BANK_SWIZZLE(SQ_ALU_VEC_012),
DST_GPR(0),
DST_REL(ABSOLUTE),
DST_ELEM(ELEM_W),
CLAMP(1));
 
return i;
}
 
static inline void
memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
__memcpy((void __force *)dst, src, count);
}
 
#define EFLOAT(val) \
do { \
union { float f; uint32_t d; } a; \
a.f = (val); \
radeon_ring_write(rdev, a.d); \
} while (0)
 
int r600_2D_test(struct radeon_device *rdev)
{
uint32_t ps_shader[16];
uint32_t vs_shader[16];
 
u32 packet2s[16];
int num_packet2s = 0;
 
uint32_t pitch;
uint32_t offset;
 
int state_len;
int dwords;
u32 obj_size;
 
u32 state_offset = 0;
u64 state_gpu_addr = 0;
 
u32 vs_offset;
u32 ps_offset;
u32 vb_offset;
 
int vs_size;
int ps_size;
 
float *vb;
void *ptr;
 
struct radeon_bo *state_obj;
 
int r;
 
ENTER();
 
pitch = (1024*4)/64;
offset = rdev->mc.vram_location;
 
ps_size = R600_solid_ps(rdev, ps_shader);
vs_size = R600_solid_vs(rdev, vs_shader);
 
if (rdev->family >= CHIP_RV770)
state_len = r7xx_default_size;
else
state_len = r6xx_default_size;
 
dwords = state_len;
 
while (dwords & 0xf) {
packet2s[num_packet2s++] = PACKET2(0);
dwords++;
}
 
obj_size = dwords * 4;
obj_size = ALIGN(obj_size, 256);
 
vs_offset = obj_size;
obj_size += vs_size * 4;
obj_size = ALIGN(obj_size, 256);
 
ps_offset = obj_size;
obj_size += ps_size * 4;
obj_size = ALIGN(obj_size, 256);
 
vb_offset = obj_size;
obj_size += 32*4;
obj_size = ALIGN(obj_size, 256);
 
r = radeon_bo_create(rdev, NULL, obj_size, true, RADEON_GEM_DOMAIN_VRAM,
&state_obj);
if (r) {
DRM_ERROR("r600 failed to allocate state buffer\n");
return r;
}
 
DRM_DEBUG("r6xx state allocated bo %08x vs %08x ps %08x\n",
obj_size, vs_offset, ps_offset);
 
r = radeon_bo_pin(state_obj, RADEON_GEM_DOMAIN_VRAM,
&state_gpu_addr);
if (r) {
DRM_ERROR("failed to pin state object %d\n", r);
return r;
};
 
r = radeon_bo_kmap(state_obj, &ptr);
if (r) {
DRM_ERROR("failed to map state object %d\n", r);
return r;
};
 
if (rdev->family >= CHIP_RV770)
memcpy_toio(ptr + state_offset,
r7xx_default_state, state_len * 4);
else
memcpy_toio(ptr + state_offset,
r6xx_default_state, state_len * 4);
 
if (num_packet2s)
memcpy_toio(ptr + state_offset + (state_len * 4),
packet2s, num_packet2s * 4);
 
memcpy(ptr + vs_offset, vs_shader, vs_size * 4);
memcpy(ptr + ps_offset, ps_shader, ps_size * 4);
 
 
vb = (float*)(ptr + vb_offset);
 
vb[0] = (float)64;
vb[1] = (float)64;
 
vb[2] = (float)64;
vb[3] = (float)(64+128);
 
vb[4] = (float)(64+128);
vb[5] = (float)(64+128);
 
int vb_index = 3;
int vb_size = vb_index * 8;
int vtx_num_entries = vb_size / 4;
 
// radeon_bo_kunmap(state_obj);
 
r = radeon_ring_lock(rdev, 1024);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
return r;
}
 
set_default_state(rdev, state_gpu_addr, state_len);
 
 
u64 gpu_addr;
u32 sq_pgm_resources;
 
/* setup shader regs */
 
/* VS */
 
sq_pgm_resources = (2 << 0);
gpu_addr = state_gpu_addr + vs_offset;
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, gpu_addr >> 8);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, sq_pgm_resources);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
 
/* PS */
 
sq_pgm_resources = (1 << 0);
gpu_addr = state_gpu_addr + ps_offset;
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, gpu_addr >> 8);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 2);
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
radeon_ring_write(rdev, 0);
 
gpu_addr = state_gpu_addr + vs_offset;
cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 
 
set_render_target(rdev, COLOR_8_8_8_8, 1024, 768, /* FIXME */
rdev->mc.vram_location);
 
set_scissors(rdev, 0, 0, 1024, 768);
 
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_ALU_CONST, 4));
radeon_ring_write(rdev, (SQ_ALU_CONSTANT0_0 - PACKET3_SET_ALU_CONST_OFFSET) >> 2);
EFLOAT(0.0f); /* r */
EFLOAT(1.0f); /* g */
EFLOAT(0.0f); /* b */
EFLOAT(1.0f); /* a */
 
u32 sq_vtx_constant_word2;
 
gpu_addr = state_gpu_addr + vb_offset;
 
sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (8 << 8));
 
radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
radeon_ring_write(rdev, 0x460);
radeon_ring_write(rdev, gpu_addr & 0xffffffff); /* 0: BASE_ADDRESS */
radeon_ring_write(rdev, (vtx_num_entries << 2) - 1); /* 1: SIZE */
radeon_ring_write(rdev, sq_vtx_constant_word2); /* 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN */
radeon_ring_write(rdev, 1 << 0); /* 3: MEM_REQUEST_SIZE ?!? */
radeon_ring_write(rdev, 0);
radeon_ring_write(rdev, 0);
radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 
if ((rdev->family == CHIP_RV610) ||
(rdev->family == CHIP_RV620) ||
(rdev->family == CHIP_RS780) ||
(rdev->family == CHIP_RS880) ||
(rdev->family == CHIP_RV710))
cp_set_surface_sync(rdev,
PACKET3_TC_ACTION_ENA, 24, gpu_addr);
else
cp_set_surface_sync(rdev,
PACKET3_VC_ACTION_ENA, 24, gpu_addr);
 
draw_auto(rdev);
 
cp_set_surface_sync(rdev, PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
1024*4*512, offset);
 
radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
/* wait for 3D idle clean */
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
 
radeon_ring_unlock_commit(rdev);
 
r600_ring_test(rdev);
 
LEAVE();
return r;
}
/drivers/video/drm/radeon/rv515.c
487,7 → 487,6
return r;
}
/* Enable IRQ */
// rdev->irq.sw_int = true;
// rs600_irq_set(rdev);
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */