| 76,6 → 76,9 |
|---|
| # define RADEON_ROP3_S 0x00cc0000 |
| # define RADEON_ROP3_P 0x00f00000 |
| |
| #define RADEON_CP_PACKET0 0x00000000 |
| #define RADEON_CP_PACKET1 0x40000000 |
| #define RADEON_CP_PACKET2 0x80000000 |
| #define RADEON_CP_PACKET3 0xC0000000 |
| |
| # define RADEON_CNTL_PAINT 0x00009100 |
| 84,6 → 87,15 |
|---|
| # define RADEON_CNTL_PAINT_POLYLINE 0x00009500 |
| # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
| |
| #define CP_PACKET0(reg, n) \ |
| (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
| |
| #define CP_PACKET1(reg0, reg1) \ |
| (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
| |
| #define CP_PACKET2() \ |
| (RADEON_CP_PACKET2) |
| |
| #define CP_PACKET3( pkt, n ) \ |
| (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
| |
| 92,10 → 104,18 |
|---|
| write = rhd.ring_wp; \ |
| } while (0) |
| |
| #define ADVANCE_RING() |
| |
| #define OUT_RING( x ) do { \ |
| ring[write++] = (x); \ |
| } while (0) |
| |
| #define OUT_RING_REG(reg, val) \ |
| do { \ |
| OUT_RING(CP_PACKET0(reg, 0)); \ |
| OUT_RING(val); \ |
| } while (0) |
| |
| #define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
| |
| #define COMMIT_RING() do { \ |