132,16 → 132,39 |
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movzx ecx, bus |
movzx edx, dev |
stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND |
stdcall PciRead16, ecx ,edx, PCI_REG_COMMAND |
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or al, PCI_BIT_MASTER ;or PCI_BIT_PIO |
; and al, not PCI_BIT_MMIO |
stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax |
or al, PCI_BIT_MASTER or PCI_BIT_PIO |
and al, not PCI_BIT_MMIO |
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;; TODO: try to switch to PIO, and check if PIO works or not.. |
; or al, PCI_BIT_MASTER or PCI_BIT_MMIO |
; and al, not PCI_BIT_PIO |
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stdcall PciWrite16, ecx, edx, PCI_REG_COMMAND, eax |
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} |
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; .Latency: |
;*******Get current latency setting************************ |
; mov al, 1 ;read a byte |
; mov bh, [pci_dev] |
; mov ah, [pci_bus] |
; mov bl, 0x0D ;from Lantency Timer Register |
; call pci_read_reg |
;******see if its aat least 64 clocks******** |
; cmp ax,64 |
; jge PCNET_adjust_pci_device_Done |
;******Set latency to 32 clocks******* |
; mov cx, 64 ;value to write |
; mov bh, [pci_dev] |
; mov al, 1 ;write a byte |
; mov ah, [pci_bus] |
; mov bl, 0x0D ;to Lantency Timer Register |
; call pci_write_reg |
;******Check latency setting*********** |
; .Done: |
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struc IOCTL { |
.handle dd ? |
.io_code dd ? |
191,6 → 214,8 |
.packets_tx dd ? ; |
.packets_rx dd ? ; |
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; .hwcksum dd ? |
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.end: |
} |
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