/kernel/branches/Kolibri-A/trunk/bus/HT.INC |
---|
7,14 → 7,17 |
;; ;; |
;; AMD HyperTransport bus control ;; |
;; ;; |
;; art_zh <artem@jerdev.co.uk> ;; |
;; art_zh <kolibri@jerdev.co.uk> ;; |
;; ;; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
$Revision: 1554 $ |
NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access |
NB_MISC_DATA equ 0xF0000064 |
PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access |
HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access |
;============================================================================= |
; |
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets |
44,6 → 47,10 |
align 4 |
;------------------------------------------ |
; params: al = nbconfig register# |
; ebx = register content |
; |
rs7xx_nbconfig_write_pci: |
and eax, 0x0FC ; leave register# only |
or eax, 0x80000000 ; bdf = 0:0.0 |
56,6 → 63,138 |
;*************************************************************************** |
; Function |
; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that |
; makes pcie config address space visible |
; ----------------------- |
; in: nothing out: nothing destroys: eax ebx edx |
; |
;*************************************************************************** |
align 4 |
rs7xx_unlock_bar3: |
mov eax, NB_MISC_INDEX |
mov ebx, 0x080 ; reg#0; write-enable |
call rs7xx_nbconfig_write_pci ; set index |
mov eax, NB_MISC_DATA |
call rs7xx_nbconfig_read_pci ; read data |
mov ebx, eax |
and ebx, 0xFFFFFFF7 ; clear bit3 |
mov eax, NB_MISC_DATA |
call rs7xx_nbconfig_write_pci ; write it back |
mov eax, NB_MISC_INDEX |
xor ebx, ebx ; reg#0; write-locked |
call rs7xx_nbconfig_write_pci ; set index |
ret |
;-------------------------------------------------------------- |
align 4 |
rs780_read_misc: |
; in: eax(al) - reg# out: eax = NBMISCIND data |
push edx |
mov edx, NB_MISC_INDEX |
and eax, 0x07F |
mov [edx], eax |
add dl, 4 |
mov eax, [edx] |
pop edx |
ret |
;------------------------------------------- |
align 4 |
rs780_write_misc: |
; in: eax(al) - reg# ebx = NBMISCIND data |
push edx |
mov edx, NB_MISC_INDEX |
and eax, 0x07F |
or eax, 0x080 ; set WE |
mov [edx], eax |
add dl, 4 |
mov [edx], ebx |
sub dl, 4 |
xor eax, eax |
mov [edx], eax ; safety last |
pop edx |
ret |
;------------------------------------------------------------- |
align 4 |
rs780_read_pcieind: |
; in: ah = bridge#, al = reg# out: eax = PCIEIND data |
push edx |
xor edx, edx |
mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
shl edx, 15 ; device# |
add edx, PCIEIND_INDEX ; full bdf-address |
and eax, 0x30FF |
or al, al |
jnz @f |
shl eax, 4 ; set bits 17..16 for a Core bridge |
@@: |
mov [edx], eax |
add dl, 4 |
mov eax, [edx] |
pop edx |
ret |
;------------------------------------------- |
align 4 |
rs780_write_pcieind: |
; in: ah = bridge#, al = reg#, ebx = PCIEIND data |
push edx |
xor edx, edx |
mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB |
and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge |
shl edx, 15 ; device# |
add edx, PCIEIND_INDEX ; full bdf-address |
and eax, 0x30FF |
or al, al |
jnz @f |
shl eax, 4 ; set bits 17..16 for a Core bridge |
@@: |
mov [edx], eax |
add dl, 4 |
mov [edx], ebx |
sub dl, 4 |
xor eax, eax |
mov [edx], eax ; safety last |
pop edx |
ret |
;------------------------------------------------ |
align 4 |
rs780_read_htiu: |
; in: al = reg# | out: eax = HTIU data |
;------------------------------------------------ |
push edx |
mov edx, HTIU_NB_INDEX |
and eax, 0x07F |
mov [edx], eax |
add dl, 4 |
mov eax, [edx] |
pop edx |
ret |
;------------------------------------------------ |
align 4 |
rs780_write_htiu: |
; in: al = reg#; ebx = data |
;------------------------------------------------ |
push edx |
mov edx, HTIU_NB_INDEX |
and eax, 0x07F |
or eax, 0x100 |
mov [edx], eax |
add dl, 4 |
mov [edx], ebx |
sub dl, 4 |
xor eax, eax |
mov [edx], eax |
pop edx |
ret |
;*************************************************************************** |
; Function |
; rs7xx_pcie_init: |
; |
; Description |
66,6 → 205,7 |
align 4 |
rs7xx_pcie_init: |
call rs7xx_unlock_bar3 |
mov al, 0x7C ; NB_IOC_CFG_CNTL |
call rs7xx_nbconfig_read_pci |
mov ebx, eax |
120,7 → 260,6 |
xor dx, dx ; PDEs counter |
@@: |
mov dword[ebx], eax ; map 4 buses |
invlpg [ecx] ; next PgDir entry |
add bx, 4 ; new PDE |
add eax, 0x400000 ; +4M phys. |
add ecx, 0x400000 ; +4M lin. |
128,6 → 267,8 |
jnc .pcie_cfg_mapped |
inc dl |
jmp @b |
mov eax, cr3 |
mov cr3, eax ; flush TLB |
.pcie_cfg_mapped: |
mov esi, boot_pcie_ok |
call boot_log |
135,13 → 276,11 |
.rs7xx_pcie_fail: |
mov esi, boot_rs7xx_fail |
call boot_log |
ret |
jmp $ |
.rs7xx_pcie_blocked: |
mov esi, boot_rs7xx_blkd |
call boot_log |
call pci_ext_config |
jmp .addr_found |
ret |
jmp $ |
/kernel/branches/Kolibri-A/trunk/bus/SB/SB710.ASM |
---|
0,0 → 1,131 |
$Revision: 1598 $ |
SMBUS_PCIE_ADDR equ 0xF00A0000 ; bdf0:20.0 = SB7xx SMBus PCI Config Registers |
LPC_PCIE_ADDR equ 0xF00A3000 ; bdf0:20.3 = SB7xx LPC ISA bridge Config Registers |
SB_SIO_INDEX equ 0x2e |
;--------------------------------------------------------------------- |
align 4 |
smbus_read_pciconfig: |
; in: dl = reg# | out: eax = data |
mov ebx, SMBUS_PCIE_ADDR |
and edx, 0x0FC |
mov eax, dword [ebx+edx] |
ret |
;------------------------------------------------ |
align 4 |
smbus_write_pciconfig: |
; in: dl = reg#; eax = data |
mov ebx, SMBUS_PCIE_ADDR |
and edx, 0x0FC |
mov dword [ebx+edx], eax |
ret |
;-------------------------------------------------------------------- |
align 4 |
lpc_read_pciconfig: |
; in: dl = reg# | out: eax = data |
mov ebx, LPC_PCIE_ADDR |
and edx, 0x0FC |
mov eax, dword [ebx+edx] |
ret |
;------------------------------------------------ |
align 4 |
lpc_write_pciconfig: |
; in: dl = reg#; eax = data |
mov ebx, LPC_PCIE_ADDR |
and edx, 0x0FC |
mov dword [ebx+edx], eax |
ret |
;-------------------------------------------------------------------- |
align 4 |
read_sio_cfg: |
; in: al = reg# | out: al = data |
mov dx, SB_SIO_INDEX |
out dx, al |
inc dl |
in al, dx |
ret |
;------------------------------------------------ |
align 4 |
write_sio_cfg: |
; in: al = reg#; ah = data |
;------------------------------------------------ |
mov dx, SB_SIO_INDEX |
out dx, al |
inc dl |
xchg al, ah |
out dx, al |
xchg al, ah |
ret |
;------------------------------------------------ |
align 4 |
enter_sio_cfg_mode: |
; the magic sequence to unlock the port |
;------------------------------------------------ |
mov dx, SB_SIO_INDEX |
mov eax, 0x55550187 ; low byte first |
out dx, al |
shr eax, 8 |
out dx, al |
shr eax, 8 |
out dx, al |
shr eax, 8 |
out dx, al |
ret |
;----------------------------------------------------------------------- |
; ATTENTION: the functions assume that RESET# signals use pins 84 and 34 |
; of IT8712F SuperIO chip. These signals may be (and will be!) different |
; for every particular motherboard and SIO. Please refer to your m/board |
; documentation to define the correct pins and GPIO lines! |
; |
; Note this example DOES NOT PRETEND to be 100% correct implementation |
; of PCIe hotplug techniques !! |
;----------------------------------------------------------------------- |
align 4 |
init_pcie_slot_control: |
;------------------------------------------------ |
call enter_sio_cfg_mode |
mov ax, 0x0707 ; LDN = 07 |
call write_sio_cfg |
mov al, 0x25 |
call read_sio_cfg ; ah = reg25h (Multy-function pin selector) |
or ah, 3 ; set bits 0, 1 (GPIO) |
call write_sio_cfg |
mov al, 0x2A |
call read_sio_cfg ; ah = reg2Ah (Extended fn pin selector) |
or ah, 3 ; set bits 0, 1 (GPIO) |
call write_sio_cfg |
mov al, 0xB8 |
call read_sio_cfg ; ah = regB8h (internal pull-up enable) |
or ah, 3 ; set bits 0, 1 |
call write_sio_cfg |
mov al, 0xC0 |
call read_sio_cfg ; ah = regC0h (simple IO enable) |
or ah, 3 ; set bits 0, 1 |
call write_sio_cfg |
mov ax, 0x0202 ; Lock SIO config ports |
call write_sio_cfg |
ret |
align 4 |
reset_pcie_slot: |
;------------------------------------------------ |
call enter_sio_cfg_mode |
mov ax, 0x0707 ; LDN = 07 |
call write_sio_cfg |
mov al, 0xB0 |
call read_sio_cfg ; ah = regB0h (Pin polarity) |
and ah, 0xFC ; invert bits 0, 1 |
call write_sio_cfg |
or ah, 3 ; restore bits 0, 1 |
call write_sio_cfg |
mov ax, 0x0202 ; Lock SIO config ports |
call write_sio_cfg |
ret |
/kernel/branches/Kolibri-A/trunk/bus/SB |
---|
Property changes: |
Added: tsvn:logminsize |
+5 |
\ No newline at end of property |
/kernel/branches/Kolibri-A/trunk/bus/pci/PCIe.inc |
---|
94,3 → 94,14 |
call boot_log |
ret ; <<<<<<<<< FAILURE >>>>>>>>> |
;-------------------------------------------------------------------------- |
; this routine is platform-specific and used to change some BIOS settengs |
; pcie_init_gfx |
; sets the GPP mode of GFX bus |
; this option disables external graphics |
pcie_init_gfx: |
ret |
/kernel/branches/Kolibri-A/trunk/bus/pci/pci32.inc |
---|
1,6 → 1,6 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
;; ;; |
;; Copyright (C) KolibriOS team 2004-2010. All rights reserved. ;; |
;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;; |
;; Distributed under terms of the GNU General Public License ;; |
;; ;; |
;; ;; |
8,11 → 8,13 |
;; ;; |
;; 32 bit PCI driver code ;; |
;; ;; |
;; Version 0.4 February 2nd, 2010 ;; |
;; Version 0.3 April 9, 2007 ;; |
;; Version 0.2 December 21st, 2002 ;; |
;; ;; |
;; Author: Victor Prodan, victorprodan@yahoo.com ;; |
;; Mihailov Ilia, ghost.nsk@gmail.com ;; |
;; Artem Jerdev, kolibri@jerdev.co.uk ;; |
;; Credits: ;; |
;; Ralf Brown ;; |
;; Mike Hibbett, mikeh@oceanfree.net ;; |
30,116 → 32,64 |
; Description |
; entry point for system PCI calls |
;*************************************************************************** |
mmio_pci_addr equ 0x400 ; set actual PCI address here to activate user-MMIO |
mmio_pci_addr dw 0x400 ; default PCI device bdf-address |
iglobal |
align 4 |
f62call: |
dd pci_api.0 |
dd pci_api.1 |
dd pci_api.2 |
dd pci_api.not_support ;3 |
dd pci_read_reg ;4 byte |
dd pci_read_reg ;5 word |
dd pci_read_reg ;6 dword |
dd pci_api.not_support ;7 |
dd pci_write_reg ;8 byte |
dd pci_write_reg ;9 word |
dd pci_write_reg ;10 dword |
if defined mmio_pci_addr |
dd pci_mmio_init ;11 |
dd pci_mmio_map ;12 |
dd pci_mmio_unmap ;13 |
end if |
f62_rcall: |
dd pci_read_reg.0 ;4 byte |
dd pci_read_reg.1 ;5 word |
dd pci_read_reg.2 ;6 dword |
f62_rcall2: |
dd pci_read_reg_2.0 ;4 byte |
dd pci_read_reg_2.1 ;5 word |
dd pci_read_reg_2.2 ;6 dword |
f62_wcall: |
dd pci_write_reg.0 ;4 byte |
dd pci_write_reg.1 ;5 word |
dd pci_write_reg.2 ;6 dword |
f62_wcall2: |
dd pci_write_reg_2.0 ;4 byte |
dd pci_write_reg_2.1 ;5 word |
dd pci_write_reg_2.2 ;6 dword |
endg |
pci_api: |
align 4 |
pci_api: |
movzx eax,bl |
cmp [pci_access_enabled],1 |
jne .no_pci_access_for_applications |
jne no_pci_access_for_applications |
if defined mmio_pci_addr |
cmp eax, 13 |
jb .not_support |
else |
cmp eax, 10 |
jb .not_support |
end if |
call dword [f62call+eax*4] |
mov dword [esp+32],eax |
ret |
; or al,al |
; jnz pci_fn_1 |
or al,al |
jnz pci_fn_1 |
; PCI function 0: get pci version (AH.AL) |
.0: |
movzx eax, word [BOOT_VAR+0x9022] |
ret |
;pci_fn_1: |
; cmp al,1 |
; jnz pci_fn_2 |
pci_fn_1: |
cmp al,1 |
jnz pci_fn_2 |
; PCI function 1: get last bus in AL |
.1: |
movzx eax, byte [BOOT_VAR+0x9021] |
mov al,[BOOT_VAR+0x9021] |
ret |
;pci_fn_2: |
; cmp al,2 |
; jne pci_fn_3 |
pci_fn_2: |
cmp al,2 |
jne pci_fn_3 |
; PCI function 2: get pci access mechanism |
.2: |
movzx eax, byte [BOOT_VAR+0x9020] |
mov al,[BOOT_VAR+0x9020] |
ret |
;pci_fn_3: |
pci_fn_3: |
; cmp al,4 |
; jz pci_read_reg ;byte |
; cmp al,5 |
; jz pci_read_reg ;word |
; cmp al,6 |
; jz pci_read_reg ;dword |
cmp al,4 |
jz pci_read_reg ;byte |
cmp al,5 |
jz pci_read_reg ;word |
cmp al,6 |
jz pci_read_reg ;dword |
; cmp al,8 |
; jz pci_write_reg ;byte |
; cmp al,9 |
; jz pci_write_reg ;word |
; cmp al,10 |
; jz pci_write_reg ;dword |
cmp al,8 |
jz pci_write_reg ;byte |
cmp al,9 |
jz pci_write_reg ;word |
cmp al,10 |
jz pci_write_reg ;dword |
;if defined mmio_pci_addr |
; cmp al,11 ; user-level MMIO functions |
; jz pci_mmio_init |
; cmp al,12 |
; jz pci_mmio_map |
; cmp al,13 |
; jz pci_mmio_unmap |
;end if |
cmp al,11 ; user-level MMIO functions |
jz pci_mmio_init |
cmp al,12 |
jz pci_mmio_map |
cmp al,13 |
jz pci_mmio_unmap |
.not_support: |
.no_pci_access_for_applications: |
no_pci_access_for_applications: |
or eax,-1 |
ret |
;*************************************************************************** |
148,20 → 98,20 |
; |
; Description |
; creates a command dword for use with the PCI bus |
; bus # in bh;ah |
; device+func in ch;bh (dddddfff) |
; register in cl;bl |
; bus # in ah |
; device+func in bh (dddddfff) |
; register in bl |
; |
; command dword returned in ebx;eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 ) |
; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 ) |
;*************************************************************************** |
align 4 |
pci_make_config_cmd: |
shl ebx,8;eax,8 ; move bus to bits 16-23 |
mov bx,cx;ax,bx ; combine all |
and ebx,0xffffff;eax,0xffffff |
or ebx,0x80000000;eax,0x80000000 |
shl eax,8 ; move bus to bits 16-23 |
mov ax,bx ; combine all |
and eax,0xffffff |
or eax,0x80000000 |
ret |
;*************************************************************************** |
178,16 → 128,12 |
align 4 |
pci_read_reg: |
cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use? |
je pci_read_reg_2 |
; mechanism 1 |
; push esi ; save register size into ESI |
mov esi,ebx;eax |
push esi ; save register size into ESI |
mov esi,eax |
and esi,3 |
call pci_make_config_cmd |
mov eax,ebx;ebx,eax |
mov ebx,eax |
; get current state |
mov dx,0xcf8 |
in eax, dx |
201,25 → 147,24 |
and bl,3 |
or dl,bl ; add to port address first 2 bits of register address |
; or esi,esi |
; jz pci_read_byte1 |
; cmp esi,1 |
; jz pci_read_word1 |
; cmp esi,2 |
; jz pci_read_dword1 |
; jmp pci_fin_read1 |
jmp dword [f62_rcall+esi*4] |
or esi,esi |
jz pci_read_byte1 |
cmp esi,1 |
jz pci_read_word1 |
cmp esi,2 |
jz pci_read_dword1 |
jmp pci_fin_read1 |
.0: |
pci_read_byte1: |
in al,dx |
jmp .pci_fin_read1 |
.1: |
jmp pci_fin_read1 |
pci_read_word1: |
in ax,dx |
jmp .pci_fin_read1 |
.2: |
jmp pci_fin_read1 |
pci_read_dword1: |
in eax,dx |
; jmp pci_fin_read1 |
.pci_fin_read1: |
jmp pci_fin_read1 |
pci_fin_read1: |
; restore configuration control |
xchg eax,[esp] |
mov dx,0xcf8 |
226,77 → 171,15 |
out dx,eax |
pop eax |
;pop esi |
pop esi |
ret |
pci_read_reg_2: |
test ch,128;bh,128 ;mech#2 only supports 16 devices per bus |
jnz pci_api.not_support |
; push esi ; save register size into ESI |
mov esi,ebx;eax |
and esi,3 |
push ebx;eax |
mov eax,ebx |
;store current state of config space |
mov dx,0xcf8 |
in al,dx |
mov ah,al |
mov dl,0xfa |
in al,dx |
xchg eax,[esp] |
; out 0xcfa,bus |
mov al,ah |
out dx,al |
; out 0xcf8,0x80 |
mov dl,0xf8 |
mov al,0x80 |
out dx,al |
; compute addr |
shr ch,3;bh,3 ; func is ignored in mechanism 2 |
or ch,0xc0;bh,0xc0 |
mov dx,cx;bx |
; or esi,esi |
; jz pci_read_byte2 |
; cmp esi,1 |
; jz pci_read_word2 |
; cmp esi,2 |
; jz pci_read_dword2 |
; jmp pci_fin_read2 |
jmp dword [f62_rcall2+esi*4] |
.0: |
in al,dx |
jmp .pci_fin_read2 |
.1: |
in ax,dx |
jmp .pci_fin_read2 |
.2: |
in eax,dx |
; jmp pci_fin_read2 |
.pci_fin_read2: |
; restore configuration space |
xchg eax,[esp] |
mov dx,0xcfa |
out dx,al |
mov dl,0xf8 |
mov al,ah |
out dx,al |
pop eax |
; pop esi |
pci_read_reg_err: |
xor eax,eax |
dec eax |
ret |
;pci_read_reg_err: |
; or dword [esp+32],-1 |
; ret |
;*************************************************************************** |
; Function |
; pci_write_reg: |
312,17 → 195,12 |
align 4 |
pci_write_reg: |
cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use? |
je pci_write_reg_2 |
push esi ; save register size into ESI |
mov esi,eax |
and esi,3 |
; mechanism 1 |
; push esi ; save register size into ESI |
mov esi,ebx;eax |
and esi,3 ;not need |
call pci_make_config_cmd |
mov eax,ebx;ebx,eax |
mov ecx,edx ;cross registers |
mov ebx,eax |
; get current state into ecx |
mov dx,0xcf8 |
in eax, dx |
337,24 → 215,24 |
or dl,bl |
mov eax,ecx |
; or esi,esi |
; jz pci_write_byte1 |
; cmp esi,1 |
; jz pci_write_word1 |
; cmp esi,2 |
; jz pci_write_dword1 |
; jmp pci_fin_write1 |
jmp dword [f62_wcall+esi*4] |
.0: |
or esi,esi |
jz pci_write_byte1 |
cmp esi,1 |
jz pci_write_word1 |
cmp esi,2 |
jz pci_write_dword1 |
jmp pci_fin_write1 |
pci_write_byte1: |
out dx,al |
jmp .pci_fin_write1 |
.1: |
jmp pci_fin_write1 |
pci_write_word1: |
out dx,ax |
jmp .pci_fin_write1 |
.2: |
jmp pci_fin_write1 |
pci_write_dword1: |
out dx,eax |
.pci_fin_write1: |
jmp pci_fin_write1 |
pci_fin_write1: |
; restore configuration control |
pop eax |
mov dl,0xf8 |
361,97 → 239,32 |
out dx,eax |
xor eax,eax |
;pop esi |
pop esi |
ret |
pci_write_reg_2: |
test ch,128;bh,128 ;mech#2 only supports 16 devices per bus |
jnz pci_api.not_support |
; push esi ; save register size into ESI |
mov esi,eax |
and esi,3 ;not need |
push eax |
mov ecx,edx ;cross registers |
;store current state of config space |
mov dx,0xcf8 |
in al,dx |
mov ah,al |
mov dl,0xfa |
in al,dx |
xchg eax,[esp] |
; out 0xcfa,bus |
mov al,ah |
out dx,al |
; out 0xcf8,0x80 |
mov dl,0xf8 |
mov al,0x80 |
out dx,al |
; compute addr |
shr bh,3 ; func is ignored in mechanism 2 |
or bh,0xc0 |
mov dx,bx |
; write register |
mov eax,ecx |
; or esi,esi |
; jz pci_write_byte2 |
; cmp esi,1 |
; jz pci_write_word2 |
; cmp esi,2 |
; jz pci_write_dword2 |
; jmp pci_fin_write2 |
jmp dword [f62_wcall2+esi*4] |
.0: |
out dx,al |
jmp .pci_fin_write2 |
.1: |
out dx,ax |
jmp .pci_fin_write2 |
.2: |
out dx,eax |
.pci_fin_write2: |
; restore configuration space |
pop eax |
mov dx,0xcfa |
out dx,al |
mov dl,0xf8 |
mov al,ah |
out dx,al |
pci_write_reg_err: |
xor eax,eax |
;pop esi |
dec eax |
ret |
;pci_write_reg_err: |
; xor eax,eax |
; dec eax |
; ret |
if defined mmio_pci_addr ; must be set above |
;*************************************************************************** |
; Function |
; pci_mmio_init |
; |
; Description |
; IN: cx = device's PCI bus address (bbbbbbbbdddddfff) |
; Returns eax = user heap space available (bytes) |
; IN: bx = device's PCI bus address (bbbbbbbbdddddfff) |
; Returns eax = phys. address of user-accessible DMA block |
; Error codes |
; eax = -1 : PCI user access blocked, |
; eax = -2 : device not registered for uMMIO service |
; eax = -3 : user heap initialization failure |
;*************************************************************************** |
pci_mmio_init: |
cmp cx, mmio_pci_addr |
jz @f |
mov eax,-2 |
ret |
@@: |
mov [mmio_pci_addr],bx |
call init_heap ; (if not initialized yet) |
or eax,eax |
jz @f |
mov eax, [UserDMAaddr] |
ret |
@@: |
mov eax,-3 |
465,10 → 278,9 |
; Description |
; maps a block of PCI memory to user-accessible linear address |
; |
; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only! |
; The target device address should be set in kernel var mmio_pci_addr |
; |
; IN: ah = BAR#; |
; IN: ah = BAR#; or |
; IN: ah = 0xDA for DMA-mapping requests; |
; IN: ebx = block size (bytes); |
; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages); |
; |
484,17 → 296,21 |
;*************************************************************************** |
pci_mmio_map: |
;cross |
mov eax,ebx |
mov ebx,ecx |
mov ecx,edx |
;;;;;;;;;;;;;;;;;;; |
and edx,0x0ffff |
cmp ah, 0xDA |
jz .dma_map |
cmp ah,6 |
jc .bar_0_5 |
jb .bar_0_5 |
jz .bar_rom |
mov eax,-2 |
ret |
.dma_map: |
push ecx |
mov ecx,ebx |
mov eax,[UserDMAaddr] |
jmp .allocate_block |
.bar_rom: |
mov ah, 8 ; bar6 = Expansion ROM base address |
.bar_0_5: |
506,7 → 322,7 |
shl bl, 1 |
shl bl, 1 |
add bl, 0x10 ; now bl = BAR offset in PCI config. space |
mov ax, mmio_pci_addr |
mov ax, [mmio_pci_addr] |
mov bh, al ; bh = dddddfff |
mov al, 2 ; al : DW to read |
call pci_read_reg |
523,7 → 339,9 |
pop ecx ; ecx = block size, bytes (expanded to whole page) |
mov ebx, ecx ; user_alloc destroys eax, ecx, edx, but saves ebx |
and eax, 0xFFFFFFF0 |
push eax ; store MMIO physical address + keep 2DWords in the stack |
.allocate_block: |
push eax ; store MMIO physical address + keep the stack 2x4b deep |
stdcall user_alloc, ecx |
or eax, eax |
jnz mmio_map_over |
542,9 → 360,7 |
pop edx ; edx = MMIO shift (pages) |
shl edx, 12 ; edx = MMIO shift (bytes) |
add eax, edx ; eax = uMMIO physical address |
or eax, PG_SHARED |
or eax, PG_UW |
or eax, PG_NOCACHE |
or eax, (PG_SHARED+PG_UW+PG_NOCACHE) |
mov edi, ebx |
call commit_pages |
mov eax, edi |
566,11 → 382,9 |
;*************************************************************************** |
pci_mmio_unmap: |
stdcall user_free, ecx;ebx |
stdcall user_free, ebx |
ret |
end if |
;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= |
uglobal |
align 4 |
/kernel/branches/Kolibri-A/trunk/core/memory.inc |
---|
337,41 → 337,36 |
align 4 |
proc init_LFB |
locals |
pg_count dd ? |
endl |
cmp dword [LFBAddress], -1 |
jne @f |
mov [BOOT_VAR+0x901c],byte 2 |
stdcall alloc_pages, (0x280000 / 4096) |
push eax |
call alloc_page |
stdcall map_page_table, LFB_BASE, eax |
pop eax |
or eax, PG_UW |
mov ebx, LFB_BASE |
mov ecx, 0x280000 / 4096 |
call commit_pages |
mov [LFBAddress], dword LFB_BASE |
ret |
@@: |
test [SCR_MODE],word 0100000000000000b |
jnz @f |
mov [BOOT_VAR+0x901c],byte 2 |
ret |
@@: |
; cmp dword [LFBAddress], -1 |
; jne @f |
; |
; mov esi, boot_framebuf |
; call boot_log |
; |
; mov [BOOT_VAR+0x901c],byte 2 |
; stdcall alloc_pages, (0x280000 / 4096) |
; |
; push eax |
; call alloc_page |
; stdcall map_page_table, LFB_BASE, eax |
; pop eax |
; or eax, PG_UW |
; mov ebx, LFB_BASE |
; mov ecx, 0x280000 / 4096 |
; call commit_pages |
; mov [LFBAddress], dword LFB_BASE |
; ret |
;@@: |
call init_mtrr |
mov edx, LFB_BASE |
mov esi, [LFBAddress] |
mov edi, 0x00C00000 |
mov edi, 0x00C00000 ; 12Mb |
mov dword [exp_lfb+4], edx |
shr edi, 12 |
mov [pg_count], edi |
shr edi, 10 |
shr edi, 12 ; C00 |
; mov [pg_count], edi |
shr edi, 10 ; 3 |
or esi, PG_GLOBAL+PG_LARGE+PG_UW |
mov edx, sys_pgdir+(LFB_BASE shr 20) |
389,16 → 384,11 |
endp |
align 4 |
proc init_userDMA |
init_userDMA: |
stdcall alloc_pages, 4096 ; 16M <<<<<<<<<<+++++++++++++++++++++++++++++++++ |
add eax, 0x007FFFF0 |
add eax, 0x007FFFF0 ; terrible mess, sorry ... |
and eax, 0xFF800000 ; align at 8M boundary |
mov [UserDMAaddr], eax |
; or eax, PG_UW + PG_NOCACHE |
; mov ebx, USER_DMA_BUFFER |
; mov ecx, 2048 ; 8M, to be sure |
; call commit_pages |
; mov eax, [UserDMAaddr] |
or eax, PG_LARGE + PG_UW + PG_NOCACHE |
mov ebx, sys_pgdir + (USER_DMA_BUFFER shr 20) |
mov [ebx], eax |
405,8 → 395,9 |
add ebx, 4 |
add eax, 0x00400000 |
mov [ebx], eax |
mov eax, cr3 ;flush TLB |
mov cr3, eax |
ret |
endp |
align 4 |
proc new_mem_resize stdcall, new_size:dword |
/kernel/branches/Kolibri-A/trunk/core/syscall.inc |
---|
99,7 → 99,7 |
dd 0 |
dd 0 |
dd 0 |
dd 0;sys_pci ; 62-PCI functions |
dd sys_pci ; 62-PCI functions |
dd sys_msg_board ; 63-System message board |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
170,7 → 170,7 |
dd undefined_syscall ; 59-reserved |
dd sys_IPC ; 60-Inter Process Communication |
dd sys_gs ; 61-Direct graphics access |
dd pci_api;cross_order ; 62-PCI functions |
dd cross_order ; 62-PCI functions |
dd cross_order ; 63-System message board |
dd sys_resize_app_memory ; 64-Resize application memory usage |
dd sys_putimage_palette ; 65-PutImagePalette |
/kernel/branches/Kolibri-A/trunk/kernel.asm |
---|
4253,13 → 4253,13 |
;align 4 ; PCI functions |
; |
;sys_pci: |
; |
; call pci_api |
; mov [esp+36],eax |
; ret |
sys_pci: |
call pci_api |
mov [esp+36],eax |
ret |
align 4 ; system functions |
syscall_setpixel: ; SetPixel |