| 12,7 → 12,7 |
|---|
| ;; ;; |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| |
| $Revision: 1463 $ |
| $Revision: 1554 $ |
| |
| ;*************************************************************************** |
| ; Function |
| 31,13 → 31,14 |
|---|
| align 4 |
| mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
| mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
| mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space |
| PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes |
| mmio_pcie_cfg_pdes dw 1 ; number of PDEs to map the space |
| PCIe_bus_range dw 2 ; the Bus range: power-of-2 Megabytes |
| |
| |
| align 4 |
| pci_ext_config: |
| mov ebx, [mmio_pcie_cfg_addr] |
| mov eax, [mmio_pcie_cfg_addr] |
| mov ebx, eax |
| or ebx,ebx |
| jz @f |
| or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
| 45,7 → 46,7 |
|---|
| add ebx, 0x0FFFFC |
| cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
| ja .pcie_failed |
| jmp .pcie_cfg_mapped |
| ret ; return the address forced |
| @@: |
| mov ebx, [cpu_vendor] |
| cmp ebx, dword [AMD_str] |
| 75,21 → 76,12 |
|---|
| shl eax, 8 |
| test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
| jnz .no_pcie_cfg |
| mov [mmio_pcie_cfg_addr], eax |
| ; add eax, 0x000FFFFC |
| ; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
| ; ja .no_pcie_cfg |
| |
| ; -- it looks like a true PCIe config space; |
| |
| .pcie_cfg_mapped: |
| |
| mov esi, boot_pcie_ok |
| call boot_log |
| ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
| |
| .no_pcie_cfg: |
| |
| xor eax, eax |
| mov [mmio_pcie_cfg_addr], eax |
| mov [mmio_pcie_cfg_lim], eax |
| 96,6 → 88,7 |
|---|
| add bl, 12 |
| cmp bl, 0xC0 ; MMIO regs lay below this offset |
| jb .check_HT_mmio |
| |
| .pcie_failed: |
| mov esi, boot_pcie_fail |
| call boot_log |