/drivers/video/drm/includes/linux/fb.h |
---|
640,12 → 640,6 |
/* perform fb specific mmap */ |
// int (*fb_mmap)(struct fb_info *info, struct vm_area_struct *vma); |
/* save current hardware state */ |
void (*fb_save_state)(struct fb_info *info); |
/* restore saved state */ |
void (*fb_restore_state)(struct fb_info *info); |
/* get capability given var */ |
void (*fb_get_caps)(struct fb_info *info, struct fb_blit_caps *caps, |
struct fb_var_screeninfo *var); |
/drivers/video/drm/radeon/radeon_device.c |
---|
213,8 → 213,6 |
{ |
uint32_t reg; |
ENTER(); |
/* first check CRTCs */ |
if (ASIC_IS_AVIVO(rdev)) { |
reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
415,8 → 413,6 |
{ |
int r; |
ENTER(); |
r = radeon_static_clocks_init(rdev->ddev); |
if (r) { |
return r; |
561,8 → 557,6 |
int r; |
int dma_bits; |
ENTER(); |
DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
rdev->shutdown = false; |
rdev->ddev = ddev; |
901,7 → 895,7 |
return 0; |
}; |
} |
dbgprintf("Radeon RC06 cmdline %s\n", cmdline); |
dbgprintf("Radeon RC07 cmdline %s\n", cmdline); |
enum_pci_devices(); |
/drivers/video/drm/radeon/radeon_gart.c |
---|
77,8 → 77,6 |
{ |
int r; |
ENTER(); |
if (rdev->gart.table.vram.robj == NULL) { |
r = radeon_object_create(rdev, NULL, |
rdev->gart.table_size, |
214,17 → 212,11 |
} |
mb(); |
radeon_gart_tlb_flush(rdev); |
LEAVE(); |
return 0; |
} |
int radeon_gart_init(struct radeon_device *rdev) |
{ |
ENTER(); |
if (rdev->gart.pages) { |
return 0; |
} |
/drivers/video/drm/radeon/radeon_legacy_crtc.c |
---|
453,6 → 453,8 |
// radeon_object_get_tiling_flags(obj->driver_private, |
// &tiling_flags, NULL); |
tiling_flags = 0; |
if (tiling_flags & RADEON_TILING_MICRO) |
DRM_ERROR("trying to scanout microtiled buffer\n"); |
530,10 → 532,10 |
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
if (old_fb && old_fb != crtc->fb) { |
radeon_fb = to_radeon_framebuffer(old_fb); |
// if (old_fb && old_fb != crtc->fb) { |
// radeon_fb = to_radeon_framebuffer(old_fb); |
// radeon_gem_object_unpin(radeon_fb->obj); |
} |
// } |
/* Bytes per pixel may have changed */ |
radeon_bandwidth_update(rdev); |
/drivers/video/drm/radeon/radeon_object.c |
---|
53,7 → 53,7 |
ENTER(); |
r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT, |
((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT)); |
((rdev->mc.real_vram_size - 0x800000) >> PAGE_SHIFT)); |
if (r) { |
DRM_ERROR("Failed initializing VRAM heap.\n"); |
return r; |
/drivers/video/drm/radeon/rdisplay.c |
---|
143,7 → 143,7 |
uint32_t gpu_addr; |
WREG32(RADEON_CUR_HORZ_VERT_OFF, |
(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16))); |
(RADEON_CUR_LOCK | (hot_x << 16) | hot_y )); |
WREG32(RADEON_CUR_HORZ_VERT_POSN, |
(RADEON_CUR_LOCK | (x << 16) | y)); |
/drivers/video/drm/radeon/rdisplay_kms.c |
---|
82,7 → 82,7 |
if (ASIC_IS_AVIVO(rdev)) |
WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
else { |
radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; |
radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_location; |
/* offset is from DISP(2)_BASE_ADDRESS */ |
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
} |
148,7 → 148,7 |
y *= 2; |
WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, |
(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16))); |
(RADEON_CUR_LOCK | (hot_x << 16) | hot_y )); |
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, |
(RADEON_CUR_LOCK | (x << 16) | y)); |