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Regard whitespace Rev 3480 → Rev 3482

/drivers/video/drm/i915/i915_dma.c
1339,6 → 1339,7
ret = -ENOMEM;
goto out_mtrrfree;
}
system_wq = dev_priv->wq;
 
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev);
/drivers/video/drm/i915/i915_drv.c
64,7 → 64,7
"Override lid status (0=autodetect, 1=autodetect disabled [default], "
"-1=force lid closed, -2=force lid open)");
 
unsigned int i915_powersave __read_mostly = 0;
unsigned int i915_powersave __read_mostly = 1;
module_param_named(powersave, i915_powersave, int, 0600);
MODULE_PARM_DESC(powersave,
"Enable powersavings, fbc, downclocking, etc. (default: true)");
74,7 → 74,7
MODULE_PARM_DESC(semaphores,
"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
 
int i915_enable_rc6 __read_mostly = 0;
int i915_enable_rc6 __read_mostly = -1;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
MODULE_PARM_DESC(i915_enable_rc6,
"Enable power-saving render C-state 6. "
83,7 → 83,7
"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
"default: -1 (use per-chip default)");
 
int i915_enable_fbc __read_mostly = 0;
int i915_enable_fbc __read_mostly = -1;
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
MODULE_PARM_DESC(i915_enable_fbc,
"Enable frame buffer compression for power savings "
136,6 → 136,10
"Enable Haswell and ValleyView Support. "
"(default: false)");
 
int i915_disable_power_well __read_mostly = 0;
module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
MODULE_PARM_DESC(disable_power_well,
"Disable the power well when possible (default: false)");
 
#define PCI_VENDOR_ID_INTEL 0x8086
 
502,9 → 506,9
/* Don't use MTRRs here; the Xserver or userspace app should
* deal with them for Intel hardware.
*/
// .driver_features =
// DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
// DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
.driver_features =
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_MODESET,
// .load = i915_driver_load,
// .unload = i915_driver_unload,
.open = i915_driver_open,
/drivers/video/drm/i915/i915_gem.c
267,9 → 267,6
trace_i915_gem_object_create(obj);
 
*handle_p = handle;
 
// printf("%s obj %p handle %d\n", __FUNCTION__, obj, handle);
 
return 0;
}
 
694,8 → 691,6
out_unpin:
i915_gem_object_unpin(obj);
out:
printf("% s ret = %d\n", __FUNCTION__, ret);
 
return ret;
}
 
1949,7 → 1944,8
}
if (was_empty) {
queue_delayed_work(dev_priv->wq,
&dev_priv->mm.retire_work, HZ);
&dev_priv->mm.retire_work,
round_jiffies_up_relative(HZ));
intel_mark_busy(dev_priv->dev);
}
}
2135,7 → 2131,8
 
/* Come back later if the device is busy... */
if (!mutex_trylock(&dev->struct_mutex)) {
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
round_jiffies_up_relative(HZ));
return;
}
 
2153,7 → 2150,8
}
 
if (!dev_priv->mm.suspended && !idle)
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
round_jiffies_up_relative(HZ));
if (idle)
intel_mark_idle(dev);
 
/drivers/video/drm/i915/intel_crt.c
252,8 → 252,6
u32 adpa;
bool ret;
 
ENTER();
 
/* The first time through, trigger an explicit detection cycle */
if (crt->force_hotplug_required) {
bool turn_off_dac = HAS_PCH_SPLIT(dev);
288,8 → 286,6
ret = false;
DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 
LEAVE();
 
return ret;
}
 
302,8 → 298,6
bool ret;
u32 save_adpa;
 
ENTER();
 
save_adpa = adpa = I915_READ(crt->adpa_reg);
DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 
329,8 → 323,6
/* FIXME: debug force function and remove */
ret = true;
 
LEAVE();
 
return ret;
}
 
350,8 → 342,6
bool ret = false;
int i, tries = 0;
 
ENTER();
 
if (HAS_PCH_SPLIT(dev))
return intel_ironlake_crt_detect_hotplug(connector);
 
390,8 → 380,6
/* and put the bits back */
I915_WRITE(PORT_HOTPLUG_EN, orig);
 
LEAVE();
 
return ret;
}
 
400,8 → 388,6
{
struct edid *edid;
 
ENTER();
 
edid = drm_get_edid(connector, i2c);
 
if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
411,8 → 397,6
intel_gmbus_force_bit(i2c, false);
}
 
LEAVE();
 
return edid;
}
 
/drivers/video/drm/i915/intel_display.c
8237,6 → 8237,9
struct drm_mode_object *drmmode_obj;
struct intel_crtc *crtc;
 
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -ENODEV;
 
drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
DRM_MODE_OBJECT_CRTC);
 
8760,9 → 8763,9
 
intel_init_clock_gating(dev);
 
// mutex_lock(&dev->struct_mutex);
// intel_enable_gt_powersave(dev);
// mutex_unlock(&dev->struct_mutex);
mutex_lock(&dev->struct_mutex);
intel_enable_gt_powersave(dev);
mutex_unlock(&dev->struct_mutex);
}
 
void intel_modeset_init(struct drm_device *dev)
/drivers/video/drm/i915/intel_dp.c
1147,13 → 1147,13
 
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
// struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
// struct intel_dp, panel_vdd_work);
// struct drm_device *dev = intel_dp_to_dev(intel_dp);
//
// mutex_lock(&dev->mode_config.mutex);
// ironlake_panel_vdd_off_sync(intel_dp);
// mutex_unlock(&dev->mode_config.mutex);
struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
struct intel_dp, panel_vdd_work);
struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
mutex_lock(&dev->mode_config.mutex);
ironlake_panel_vdd_off_sync(intel_dp);
mutex_unlock(&dev->mode_config.mutex);
}
 
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1174,8 → 1174,8
* time from now (relative to the power down delay)
* to keep the panel power up across a sequence of operations
*/
// schedule_delayed_work(&intel_dp->panel_vdd_work,
// msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
schedule_delayed_work(&intel_dp->panel_vdd_work,
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
}
}
 
/drivers/video/drm/i915/intel_drv.h
33,6 → 33,8
#include <drm/drm_fb_helper.h>
#include <drm/drm_dp_helper.h>
 
#define KBUILD_MODNAME "i915.dll"
 
#define cpu_relax() asm volatile("rep; nop")
 
#define _wait_for(COND, MS, W) ({ \
/drivers/video/drm/i915/intel_panel.c
194,7 → 194,7
/* XXX add code here to query mode clock or hardware clock
* and program max PWM appropriately.
*/
printk("fixme: max PWM is zero\n");
pr_warn_once("fixme: max PWM is zero\n");
return 1;
}
 
/drivers/video/drm/i915/intel_pm.c
282,7 → 282,6
return dev_priv->display.fbc_enabled(dev);
}
 
#if 0
static void intel_fbc_work_fn(struct work_struct *__work)
{
struct intel_fbc_work *work =
323,9 → 322,9
* dev_priv->fbc_work, so we can perform the cancellation
* entirely asynchronously.
*/
if (cancel_delayed_work(&dev_priv->fbc_work->work))
// if (cancel_delayed_work(&dev_priv->fbc_work->work))
/* tasklet was killed before being run, clean up */
kfree(dev_priv->fbc_work);
// kfree(dev_priv->fbc_work);
 
/* Mark the work as no longer wanted so that if it does
* wake-up (because the work was already running and waiting
334,7 → 333,6
*/
dev_priv->fbc_work = NULL;
}
#endif
 
void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
342,9 → 340,9
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
// if (!dev_priv->display.enable_fbc)
if (!dev_priv->display.enable_fbc)
return;
#if 0
 
intel_cancel_fbc_work(dev_priv);
 
work = kzalloc(sizeof *work, GFP_KERNEL);
374,8 → 372,6
* waiting synchronously upon the vblank.
*/
schedule_delayed_work(&work->work, msecs_to_jiffies(50));
#endif
 
}
 
void intel_disable_fbc(struct drm_device *dev)
382,12 → 378,12
{
struct drm_i915_private *dev_priv = dev->dev_private;
 
// intel_cancel_fbc_work(dev_priv);
intel_cancel_fbc_work(dev_priv);
 
// if (!dev_priv->display.disable_fbc)
// return;
if (!dev_priv->display.disable_fbc)
return;
 
// dev_priv->display.disable_fbc(dev);
dev_priv->display.disable_fbc(dev);
dev_priv->cfb_plane = -1;
}
 
420,6 → 416,8
struct drm_i915_gem_object *obj;
int enable_fbc;
 
ENTER();
 
if (!i915_powersave)
return;
 
550,6 → 548,8
}
 
intel_enable_fbc(crtc, 500);
LEAVE();
 
return;
 
out_disable:
559,6 → 559,7
intel_disable_fbc(dev);
}
i915_gem_stolen_cleanup_compression(dev);
LEAVE();
}
 
static void i915_pineview_get_mem_freq(struct drm_device *dev)
2411,7 → 2412,7
I915_READ(0x112e0);
dev_priv->ips.last_time1 = jiffies_to_msecs(GetTimerTicks());
dev_priv->ips.last_count2 = I915_READ(0x112f4);
// getrawmonotonic(&dev_priv->ips.last_time2);
getrawmonotonic(&dev_priv->ips.last_time2);
 
spin_unlock_irq(&mchdev_lock);
}
2690,7 → 2691,6
gen6_gt_force_wake_put(dev_priv);
}
 
#if 0
static void gen6_update_ring_freq(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
2737,7 → 2737,6
ia_freq | gpu_freq);
}
}
#endif
 
void ironlake_teardown_rc6(struct drm_device *dev)
{
3466,11 → 3465,30
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
} else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
// cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
mutex_lock(&dev_priv->rps.hw_lock);
gen6_disable_rps(dev);
mutex_unlock(&dev_priv->rps.hw_lock);
}
}
 
static void intel_gen6_powersave_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
rps.delayed_resume_work.work);
struct drm_device *dev = dev_priv->dev;
 
ENTER();
 
mutex_lock(&dev_priv->rps.hw_lock);
gen6_enable_rps(dev);
gen6_update_ring_freq(dev);
mutex_unlock(&dev_priv->rps.hw_lock);
 
LEAVE();
}
 
void intel_enable_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
3485,8 → 3503,8
* done at any specific time, so do this out of our fast path
* to make resume and init faster.
*/
// schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
// round_jiffies_up_relative(HZ));
schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
round_jiffies_up_relative(HZ));
}
}
 
4089,6 → 4107,9
if (!IS_HASWELL(dev))
return;
 
if (!i915_disable_power_well && !enable)
return;
 
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
is_enabled = tmp & HSW_PWR_WELL_STATE;
enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4468,6 → 4489,8
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
}
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
intel_gen6_powersave_work);
}
 
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
/drivers/video/drm/i915/intel_sdvo.c
37,15 → 37,6
#include "i915_drv.h"
#include "intel_sdvo_regs.h"
 
unsigned int hweight16(unsigned int w)
{
unsigned int res = w - ((w >> 1) & 0x5555);
res = (res & 0x3333) + ((res >> 2) & 0x3333);
res = (res + (res >> 4)) & 0x0F0F;
return (res + (res >> 8)) & 0x00FF;
}
 
 
#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
/drivers/video/drm/i915/intel_sprite.c
594,6 → 594,8
struct intel_plane *intel_plane;
int ret = 0;
 
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -ENODEV;
 
/* Make sure we don't try to enable both src & dest simultaneously */
if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
625,6 → 627,8
struct intel_plane *intel_plane;
int ret = 0;
 
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return -ENODEV;
 
drm_modeset_lock_all(dev);
 
/drivers/video/drm/i915/kms_display.c
836,119 → 836,15
 
 
 
void __stdcall run_workqueue(struct workqueue_struct *cwq)
{
unsigned long irqflags;
 
// dbgprintf("wq: %x head %x, next %x\n",
// cwq, &cwq->worklist, cwq->worklist.next);
 
spin_lock_irqsave(&cwq->lock, irqflags);
 
while (!list_empty(&cwq->worklist))
{
struct work_struct *work = list_entry(cwq->worklist.next,
struct work_struct, entry);
work_func_t f = work->func;
list_del_init(cwq->worklist.next);
// dbgprintf("head %x, next %x\n",
// &cwq->worklist, cwq->worklist.next);
 
spin_unlock_irqrestore(&cwq->lock, irqflags);
f(work);
spin_lock_irqsave(&cwq->lock, irqflags);
}
 
spin_unlock_irqrestore(&cwq->lock, irqflags);
}
 
 
static inline
int __queue_work(struct workqueue_struct *wq,
struct work_struct *work)
{
unsigned long flags;
 
// dbgprintf("wq: %x, work: %x\n",
// wq, work );
 
if(!list_empty(&work->entry))
return 0;
 
spin_lock_irqsave(&wq->lock, flags);
 
if(list_empty(&wq->worklist))
TimerHs(0,0, run_workqueue, wq);
 
list_add_tail(&work->entry, &wq->worklist);
 
spin_unlock_irqrestore(&wq->lock, flags);
// dbgprintf("wq: %x head %x, next %x\n",
// wq, &wq->worklist, wq->worklist.next);
 
return 1;
};
 
bool queue_work(struct workqueue_struct *wq, struct work_struct *work)
{
return __queue_work(wq, work);
}
 
 
void __stdcall delayed_work_timer_fn(unsigned long __data)
{
struct delayed_work *dwork = (struct delayed_work *)__data;
struct workqueue_struct *wq = dwork->work.data;
 
// dbgprintf("wq: %x, work: %x\n",
// wq, &dwork->work );
 
__queue_work(wq, &dwork->work);
}
 
 
int queue_delayed_work_on(struct workqueue_struct *wq,
struct delayed_work *dwork, unsigned long delay)
{
struct work_struct *work = &dwork->work;
 
work->data = wq;
TimerHs(0,0, delayed_work_timer_fn, dwork);
return 1;
}
 
int queue_delayed_work(struct workqueue_struct *wq,
struct delayed_work *dwork, unsigned long delay)
{
u32 flags;
 
// dbgprintf("wq: %x, work: %x\n",
// wq, &dwork->work );
 
if (delay == 0)
return __queue_work(wq, &dwork->work);
 
return queue_delayed_work_on(wq, dwork, delay);
}
 
 
struct workqueue_struct *alloc_workqueue(const char *fmt,
unsigned int flags,
int max_active)
{
struct workqueue_struct *wq;
 
wq = kzalloc(sizeof(*wq),0);
if (!wq)
goto err;
 
INIT_LIST_HEAD(&wq->worklist);
 
return wq;
err:
return NULL;
}
 
#define NSEC_PER_SEC 1000000000L
 
void getrawmonotonic(struct timespec *ts)
1028,7 → 924,21
return 1;
}
 
unsigned int hweight16(unsigned int w)
{
unsigned int res = w - ((w >> 1) & 0x5555);
res = (res & 0x3333) + ((res >> 2) & 0x3333);
res = (res + (res >> 4)) & 0x0F0F;
return (res + (res >> 8)) & 0x00FF;
}
 
 
unsigned long round_jiffies_up_relative(unsigned long j)
{
unsigned long j0 = GetTimerTicks();
 
/* Use j0 because jiffies might change while we run */
return round_jiffies_common(j + j0, true) - j0;
}
 
 
/drivers/video/drm/i915/main.c
53,7 → 53,10
 
static char log[256];
 
struct workqueue_struct *system_wq;
 
int x86_clflush_size;
unsigned int tsc_khz;
 
int i915_modeset = 1;
 
102,17 → 105,14
if( err != 0)
dbgprintf("Set DISPLAY handler\n");
 
struct drm_i915_private *dev_priv = main_device->dev_private;
 
run_workqueue(dev_priv->wq);
 
return err;
};
 
//int __declspec(dllexport) DllMain(int, char*) __attribute__ ((weak, alias ("drvEntry")));
 
//int __declspec(dllexport) DllMain( int hinstDLL, int fdwReason, void *lpReserved )
//{
//
// return 1;
//}
 
#define CURRENT_API 0x0200 /* 2.00 */
#define COMPATIBLE_API 0x0100 /* 1.00 */
 
394,6 → 394,8
{
x86_clflush_size = ((misc >> 8) & 0xff) * 8;
}
 
tsc_khz = (unsigned int)(GetCpuFreq()/1000);
}