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/* |
* Copyright 2013 Advanced Micro Devices, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in |
* all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
*/ |
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#ifndef SMU7_DISCRETE_H |
#define SMU7_DISCRETE_H |
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#include "smu7.h" |
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#pragma pack(push, 1) |
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#define SMU7_DTE_ITERATIONS 5 |
#define SMU7_DTE_SOURCES 3 |
#define SMU7_DTE_SINKS 1 |
#define SMU7_NUM_CPU_TES 0 |
#define SMU7_NUM_GPU_TES 1 |
#define SMU7_NUM_NON_TES 2 |
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struct SMU7_SoftRegisters |
{ |
uint32_t RefClockFrequency; |
uint32_t PmTimerP; |
uint32_t FeatureEnables; |
uint32_t PreVBlankGap; |
uint32_t VBlankTimeout; |
uint32_t TrainTimeGap; |
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uint32_t MvddSwitchTime; |
uint32_t LongestAcpiTrainTime; |
uint32_t AcpiDelay; |
uint32_t G5TrainTime; |
uint32_t DelayMpllPwron; |
uint32_t VoltageChangeTimeout; |
uint32_t HandshakeDisables; |
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uint8_t DisplayPhy1Config; |
uint8_t DisplayPhy2Config; |
uint8_t DisplayPhy3Config; |
uint8_t DisplayPhy4Config; |
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uint8_t DisplayPhy5Config; |
uint8_t DisplayPhy6Config; |
uint8_t DisplayPhy7Config; |
uint8_t DisplayPhy8Config; |
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uint32_t AverageGraphicsA; |
uint32_t AverageMemoryA; |
uint32_t AverageGioA; |
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uint8_t SClkDpmEnabledLevels; |
uint8_t MClkDpmEnabledLevels; |
uint8_t LClkDpmEnabledLevels; |
uint8_t PCIeDpmEnabledLevels; |
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uint8_t UVDDpmEnabledLevels; |
uint8_t SAMUDpmEnabledLevels; |
uint8_t ACPDpmEnabledLevels; |
uint8_t VCEDpmEnabledLevels; |
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uint32_t DRAM_LOG_ADDR_H; |
uint32_t DRAM_LOG_ADDR_L; |
uint32_t DRAM_LOG_PHY_ADDR_H; |
uint32_t DRAM_LOG_PHY_ADDR_L; |
uint32_t DRAM_LOG_BUFF_SIZE; |
uint32_t UlvEnterC; |
uint32_t UlvTime; |
uint32_t Reserved[3]; |
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}; |
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typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; |
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struct SMU7_Discrete_VoltageLevel |
{ |
uint16_t Voltage; |
uint16_t StdVoltageHiSidd; |
uint16_t StdVoltageLoSidd; |
uint8_t Smio; |
uint8_t padding; |
}; |
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typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; |
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struct SMU7_Discrete_GraphicsLevel |
{ |
uint32_t Flags; |
uint32_t MinVddc; |
uint32_t MinVddcPhases; |
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uint32_t SclkFrequency; |
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uint8_t padding1[2]; |
uint16_t ActivityLevel; |
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uint32_t CgSpllFuncCntl3; |
uint32_t CgSpllFuncCntl4; |
uint32_t SpllSpreadSpectrum; |
uint32_t SpllSpreadSpectrum2; |
uint32_t CcPwrDynRm; |
uint32_t CcPwrDynRm1; |
uint8_t SclkDid; |
uint8_t DisplayWatermark; |
uint8_t EnabledForActivity; |
uint8_t EnabledForThrottle; |
uint8_t UpH; |
uint8_t DownH; |
uint8_t VoltageDownH; |
uint8_t PowerThrottle; |
uint8_t DeepSleepDivId; |
uint8_t padding[3]; |
}; |
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typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; |
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struct SMU7_Discrete_ACPILevel |
{ |
uint32_t Flags; |
uint32_t MinVddc; |
uint32_t MinVddcPhases; |
uint32_t SclkFrequency; |
uint8_t SclkDid; |
uint8_t DisplayWatermark; |
uint8_t DeepSleepDivId; |
uint8_t padding; |
uint32_t CgSpllFuncCntl; |
uint32_t CgSpllFuncCntl2; |
uint32_t CgSpllFuncCntl3; |
uint32_t CgSpllFuncCntl4; |
uint32_t SpllSpreadSpectrum; |
uint32_t SpllSpreadSpectrum2; |
uint32_t CcPwrDynRm; |
uint32_t CcPwrDynRm1; |
}; |
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typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; |
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struct SMU7_Discrete_Ulv |
{ |
uint32_t CcPwrDynRm; |
uint32_t CcPwrDynRm1; |
uint16_t VddcOffset; |
uint8_t VddcOffsetVid; |
uint8_t VddcPhase; |
uint32_t Reserved; |
}; |
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typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; |
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struct SMU7_Discrete_MemoryLevel |
{ |
uint32_t MinVddc; |
uint32_t MinVddcPhases; |
uint32_t MinVddci; |
uint32_t MinMvdd; |
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uint32_t MclkFrequency; |
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uint8_t EdcReadEnable; |
uint8_t EdcWriteEnable; |
uint8_t RttEnable; |
uint8_t StutterEnable; |
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uint8_t StrobeEnable; |
uint8_t StrobeRatio; |
uint8_t EnabledForThrottle; |
uint8_t EnabledForActivity; |
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uint8_t UpH; |
uint8_t DownH; |
uint8_t VoltageDownH; |
uint8_t padding; |
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uint16_t ActivityLevel; |
uint8_t DisplayWatermark; |
uint8_t padding1; |
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uint32_t MpllFuncCntl; |
uint32_t MpllFuncCntl_1; |
uint32_t MpllFuncCntl_2; |
uint32_t MpllAdFuncCntl; |
uint32_t MpllDqFuncCntl; |
uint32_t MclkPwrmgtCntl; |
uint32_t DllCntl; |
uint32_t MpllSs1; |
uint32_t MpllSs2; |
}; |
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typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; |
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struct SMU7_Discrete_LinkLevel |
{ |
uint8_t PcieGenSpeed; |
uint8_t PcieLaneCount; |
uint8_t EnabledForActivity; |
uint8_t Padding; |
uint32_t DownT; |
uint32_t UpT; |
uint32_t Reserved; |
}; |
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typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; |
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struct SMU7_Discrete_MCArbDramTimingTableEntry |
{ |
uint32_t McArbDramTiming; |
uint32_t McArbDramTiming2; |
uint8_t McArbBurstTime; |
uint8_t padding[3]; |
}; |
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typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; |
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struct SMU7_Discrete_MCArbDramTimingTable |
{ |
SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; |
}; |
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typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; |
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struct SMU7_Discrete_UvdLevel |
{ |
uint32_t VclkFrequency; |
uint32_t DclkFrequency; |
uint16_t MinVddc; |
uint8_t MinVddcPhases; |
uint8_t VclkDivider; |
uint8_t DclkDivider; |
uint8_t padding[3]; |
}; |
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typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; |
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struct SMU7_Discrete_ExtClkLevel |
{ |
uint32_t Frequency; |
uint16_t MinVoltage; |
uint8_t MinPhases; |
uint8_t Divider; |
}; |
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typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; |
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struct SMU7_Discrete_StateInfo |
{ |
uint32_t SclkFrequency; |
uint32_t MclkFrequency; |
uint32_t VclkFrequency; |
uint32_t DclkFrequency; |
uint32_t SamclkFrequency; |
uint32_t AclkFrequency; |
uint32_t EclkFrequency; |
uint16_t MvddVoltage; |
uint16_t padding16; |
uint8_t DisplayWatermark; |
uint8_t McArbIndex; |
uint8_t McRegIndex; |
uint8_t SeqIndex; |
uint8_t SclkDid; |
int8_t SclkIndex; |
int8_t MclkIndex; |
uint8_t PCIeGen; |
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}; |
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typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; |
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struct SMU7_Discrete_DpmTable |
{ |
SMU7_PIDController GraphicsPIDController; |
SMU7_PIDController MemoryPIDController; |
SMU7_PIDController LinkPIDController; |
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uint32_t SystemFlags; |
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uint32_t SmioMaskVddcVid; |
uint32_t SmioMaskVddcPhase; |
uint32_t SmioMaskVddciVid; |
uint32_t SmioMaskMvddVid; |
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uint32_t VddcLevelCount; |
uint32_t VddciLevelCount; |
uint32_t MvddLevelCount; |
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SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; |
// SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; |
SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; |
SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; |
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uint8_t GraphicsDpmLevelCount; |
uint8_t MemoryDpmLevelCount; |
uint8_t LinkLevelCount; |
uint8_t UvdLevelCount; |
uint8_t VceLevelCount; |
uint8_t AcpLevelCount; |
uint8_t SamuLevelCount; |
uint8_t MasterDeepSleepControl; |
uint32_t Reserved[5]; |
// uint32_t SamuDefaultLevel; |
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SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; |
SMU7_Discrete_MemoryLevel MemoryACPILevel; |
SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; |
SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; |
SMU7_Discrete_ACPILevel ACPILevel; |
SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; |
SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; |
SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; |
SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; |
SMU7_Discrete_Ulv Ulv; |
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uint32_t SclkStepSize; |
uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; |
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uint8_t UvdBootLevel; |
uint8_t VceBootLevel; |
uint8_t AcpBootLevel; |
uint8_t SamuBootLevel; |
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uint8_t UVDInterval; |
uint8_t VCEInterval; |
uint8_t ACPInterval; |
uint8_t SAMUInterval; |
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uint8_t GraphicsBootLevel; |
uint8_t GraphicsVoltageChangeEnable; |
uint8_t GraphicsThermThrottleEnable; |
uint8_t GraphicsInterval; |
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uint8_t VoltageInterval; |
uint8_t ThermalInterval; |
uint16_t TemperatureLimitHigh; |
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uint16_t TemperatureLimitLow; |
uint8_t MemoryBootLevel; |
uint8_t MemoryVoltageChangeEnable; |
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uint8_t MemoryInterval; |
uint8_t MemoryThermThrottleEnable; |
uint16_t VddcVddciDelta; |
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uint16_t VoltageResponseTime; |
uint16_t PhaseResponseTime; |
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uint8_t PCIeBootLinkLevel; |
uint8_t PCIeGenInterval; |
uint8_t DTEInterval; |
uint8_t DTEMode; |
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uint8_t SVI2Enable; |
uint8_t VRHotGpio; |
uint8_t AcDcGpio; |
uint8_t ThermGpio; |
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uint16_t PPM_PkgPwrLimit; |
uint16_t PPM_TemperatureLimit; |
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uint16_t DefaultTdp; |
uint16_t TargetTdp; |
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uint16_t FpsHighT; |
uint16_t FpsLowT; |
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uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; |
uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; |
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uint8_t DTEAmbientTempBase; |
uint8_t DTETjOffset; |
uint8_t GpuTjMax; |
uint8_t GpuTjHyst; |
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uint16_t BootVddc; |
uint16_t BootVddci; |
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uint16_t BootMVdd; |
uint16_t padding; |
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uint32_t BAPM_TEMP_GRADIENT; |
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uint32_t LowSclkInterruptT; |
}; |
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typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; |
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#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 |
#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY |
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struct SMU7_Discrete_MCRegisterAddress |
{ |
uint16_t s0; |
uint16_t s1; |
}; |
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typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; |
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struct SMU7_Discrete_MCRegisterSet |
{ |
uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
}; |
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typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; |
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struct SMU7_Discrete_MCRegisters |
{ |
uint8_t last; |
uint8_t reserved[3]; |
SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; |
SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; |
}; |
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typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; |
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struct SMU7_Discrete_PmFuses { |
// dw0-dw1 |
uint8_t BapmVddCVidHiSidd[8]; |
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// dw2-dw3 |
uint8_t BapmVddCVidLoSidd[8]; |
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// dw4-dw5 |
uint8_t VddCVid[8]; |
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// dw6 |
uint8_t SviLoadLineEn; |
uint8_t SviLoadLineVddC; |
uint8_t SviLoadLineTrimVddC; |
uint8_t SviLoadLineOffsetVddC; |
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// dw7 |
uint16_t TDC_VDDC_PkgLimit; |
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; |
uint8_t TDC_MAWt; |
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// dw8 |
uint8_t TdcWaterfallCtl; |
uint8_t LPMLTemperatureMin; |
uint8_t LPMLTemperatureMax; |
uint8_t Reserved; |
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// dw9-dw10 |
uint8_t BapmVddCVidHiSidd2[8]; |
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// dw11-dw12 |
uint32_t Reserved6[2]; |
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// dw13-dw16 |
uint8_t GnbLPML[16]; |
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// dw17 |
uint8_t GnbLPMLMaxVid; |
uint8_t GnbLPMLMinVid; |
uint8_t Reserved1[2]; |
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// dw18 |
uint16_t BapmVddCBaseLeakageHiSidd; |
uint16_t BapmVddCBaseLeakageLoSidd; |
}; |
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typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; |
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#pragma pack(pop) |
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#endif |
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