| 358,6 → 358,10 |
|---|
| #define CC_SYS_RB_BACKEND_DISABLE 0xe80 |
| #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 |
| |
| #define SRBM_READ_ERROR 0xE98 |
| #define SRBM_INT_CNTL 0xEA0 |
| #define SRBM_INT_ACK 0xEA8 |
| |
| #define SRBM_STATUS2 0x0EC4 |
| #define DMA_BUSY (1 << 5) |
| #define DMA1_BUSY (1 << 6) |
| 901,6 → 905,16 |
|---|
| /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ |
| #define CRTC_STATUS_FRAME_COUNT 0x6e98 |
| |
| /* Audio clocks */ |
| #define DCCG_AUDIO_DTO_SOURCE 0x05ac |
| # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ |
| # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ |
| |
| #define DCCG_AUDIO_DTO0_PHASE 0x05b0 |
| #define DCCG_AUDIO_DTO0_MODULE 0x05b4 |
| #define DCCG_AUDIO_DTO1_PHASE 0x05c0 |
| #define DCCG_AUDIO_DTO1_MODULE 0x05c4 |
| |
| #define AFMT_AUDIO_SRC_CONTROL 0x713c |
| #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) |
| /* AFMT_AUDIO_SRC_SELECT |
| 1542,6 → 1556,7 |
|---|
| #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 |
| #define UVD_RBC_RB_RPTR 0xF690 |
| #define UVD_RBC_RB_WPTR 0xF694 |
| #define UVD_STATUS 0xf6bc |
| |
| #define UVD_CGC_CTRL 0xF4B0 |
| # define DCM (1 << 0) |
| 1632,6 → 1647,23 |
|---|
| #define PACKET3_MPEG_INDEX 0x3A |
| #define PACKET3_COPY_DW 0x3B |
| #define PACKET3_WAIT_REG_MEM 0x3C |
| #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
| /* 0 - always |
| * 1 - < |
| * 2 - <= |
| * 3 - == |
| * 4 - != |
| * 5 - >= |
| * 6 - > |
| */ |
| #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
| /* 0 - reg |
| * 1 - mem |
| */ |
| #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
| /* 0 - me |
| * 1 - pfp |
| */ |
| #define PACKET3_MEM_WRITE 0x3D |
| #define PACKET3_COPY_DATA 0x40 |
| #define PACKET3_CP_DMA 0x41 |
| 1835,6 → 1867,7 |
|---|
| #define DMA_PACKET_TRAP 0x7 |
| #define DMA_PACKET_SRBM_WRITE 0x9 |
| #define DMA_PACKET_CONSTANT_FILL 0xd |
| #define DMA_PACKET_POLL_REG_MEM 0xe |
| #define DMA_PACKET_NOP 0xf |
| |
| #define VCE_STATUS 0x20004 |
| 1846,6 → 1879,7 |
|---|
| #define VCE_VCPU_CACHE_SIZE1 0x20030 |
| #define VCE_VCPU_CACHE_OFFSET2 0x20034 |
| #define VCE_VCPU_CACHE_SIZE2 0x20038 |
| #define VCE_VCPU_SCRATCH7 0x200dc |
| #define VCE_SOFT_RESET 0x20120 |
| #define VCE_ECPU_SOFT_RESET (1 << 0) |
| #define VCE_FME_SOFT_RESET (1 << 2) |
| 1860,6 → 1894,7 |
|---|
| #define VCE_RB_RPTR 0x2018c |
| #define VCE_RB_WPTR 0x20190 |
| #define VCE_CLOCK_GATING_A 0x202f8 |
| # define CGC_DYN_CLOCK_MODE (1 << 16) |
| #define VCE_CLOCK_GATING_B 0x202fc |
| #define VCE_UENC_CLOCK_GATING 0x205bc |
| #define VCE_UENC_REG_CLOCK_GATING 0x205c0 |
| 1884,4 → 1919,31 |
|---|
| #define VCE_CMD_IB_AUTO 0x00000005 |
| #define VCE_CMD_SEMAPHORE 0x00000006 |
| |
| /* discrete vce clocks */ |
| #define CG_VCEPLL_FUNC_CNTL 0xc0030600 |
| # define VCEPLL_RESET_MASK 0x00000001 |
| # define VCEPLL_SLEEP_MASK 0x00000002 |
| # define VCEPLL_BYPASS_EN_MASK 0x00000004 |
| # define VCEPLL_CTLREQ_MASK 0x00000008 |
| # define VCEPLL_VCO_MODE_MASK 0x00000600 |
| # define VCEPLL_REF_DIV_MASK 0x003F0000 |
| # define VCEPLL_CTLACK_MASK 0x40000000 |
| # define VCEPLL_CTLACK2_MASK 0x80000000 |
| #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 |
| # define VCEPLL_PDIV_A(x) ((x) << 0) |
| # define VCEPLL_PDIV_A_MASK 0x0000007F |
| # define VCEPLL_PDIV_B(x) ((x) << 8) |
| # define VCEPLL_PDIV_B_MASK 0x00007F00 |
| # define EVCLK_SRC_SEL(x) ((x) << 20) |
| # define EVCLK_SRC_SEL_MASK 0x01F00000 |
| # define ECCLK_SRC_SEL(x) ((x) << 25) |
| # define ECCLK_SRC_SEL_MASK 0x3E000000 |
| #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 |
| # define VCEPLL_FB_DIV(x) ((x) << 0) |
| # define VCEPLL_FB_DIV_MASK 0x01FFFFFF |
| #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 |
| #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 |
| #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 |
| # define VCEPLL_SSEN_MASK 0x00000001 |
| |
| #endif |