| 28,7 → 28,37 |
|---|
| |
| #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
| #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 |
| #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
| |
| /* discrete uvd clocks */ |
| #define CG_UPLL_FUNC_CNTL 0x634 |
| # define UPLL_RESET_MASK 0x00000001 |
| # define UPLL_SLEEP_MASK 0x00000002 |
| # define UPLL_BYPASS_EN_MASK 0x00000004 |
| # define UPLL_CTLREQ_MASK 0x00000008 |
| # define UPLL_VCO_MODE_MASK 0x00000600 |
| # define UPLL_REF_DIV_MASK 0x003F0000 |
| # define UPLL_CTLACK_MASK 0x40000000 |
| # define UPLL_CTLACK2_MASK 0x80000000 |
| #define CG_UPLL_FUNC_CNTL_2 0x638 |
| # define UPLL_PDIV_A(x) ((x) << 0) |
| # define UPLL_PDIV_A_MASK 0x0000007F |
| # define UPLL_PDIV_B(x) ((x) << 8) |
| # define UPLL_PDIV_B_MASK 0x00007F00 |
| # define VCLK_SRC_SEL(x) ((x) << 20) |
| # define VCLK_SRC_SEL_MASK 0x01F00000 |
| # define DCLK_SRC_SEL(x) ((x) << 25) |
| # define DCLK_SRC_SEL_MASK 0x3E000000 |
| #define CG_UPLL_FUNC_CNTL_3 0x63C |
| # define UPLL_FB_DIV(x) ((x) << 0) |
| # define UPLL_FB_DIV_MASK 0x01FFFFFF |
| #define CG_UPLL_FUNC_CNTL_4 0x644 |
| # define UPLL_SPARE_ISPARE9 0x00020000 |
| #define CG_UPLL_FUNC_CNTL_5 0x648 |
| # define RESET_ANTI_MUX_MASK 0x00000200 |
| #define CG_UPLL_SPREAD_SPECTRUM 0x650 |
| # define SSEN_MASK 0x00000001 |
| |
| #define CG_MULT_THERMAL_STATUS 0x714 |
| #define ASIC_MAX_TEMP(x) ((x) << 0) |
| #define ASIC_MAX_TEMP_MASK 0x000001ff |
| 58,9 → 88,24 |
|---|
| #define VGA_HDP_CONTROL 0x328 |
| #define VGA_MEMORY_DISABLE (1 << 4) |
| |
| #define CG_CLKPIN_CNTL 0x660 |
| # define XTALIN_DIVIDE (1 << 1) |
| #define CG_CLKPIN_CNTL_2 0x664 |
| # define MUX_TCLK_TO_XCLK (1 << 8) |
| |
| #define DMIF_ADDR_CONFIG 0xBD4 |
| |
| #define DMIF_ADDR_CALC 0xC00 |
| |
| #define SRBM_STATUS 0xE50 |
| #define GRBM_RQ_PENDING (1 << 5) |
| #define VMC_BUSY (1 << 8) |
| #define MCB_BUSY (1 << 9) |
| #define MCB_NON_DISPLAY_BUSY (1 << 10) |
| #define MCC_BUSY (1 << 11) |
| #define MCD_BUSY (1 << 12) |
| #define SEM_BUSY (1 << 14) |
| #define IH_BUSY (1 << 17) |
| |
| #define SRBM_SOFT_RESET 0x0E60 |
| #define SOFT_RESET_BIF (1 << 1) |
| 81,6 → 126,10 |
|---|
| #define CC_SYS_RB_BACKEND_DISABLE 0xe80 |
| #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 |
| |
| #define SRBM_STATUS2 0x0EC4 |
| #define DMA_BUSY (1 << 5) |
| #define DMA1_BUSY (1 << 6) |
| |
| #define VM_L2_CNTL 0x1400 |
| #define ENABLE_L2_CACHE (1 << 0) |
| #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
| 781,18 → 830,18 |
|---|
| # define THREAD_TRACE_FINISH (55 << 0) |
| |
| /* |
| * UVD |
| */ |
| #define UVD_UDEC_ADDR_CONFIG 0xEF4C |
| #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 |
| #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 |
| #define UVD_RBC_RB_RPTR 0xF690 |
| #define UVD_RBC_RB_WPTR 0xF694 |
| |
| /* |
| * PM4 |
| */ |
| #define PACKET_TYPE0 0 |
| #define PACKET_TYPE1 1 |
| #define PACKET_TYPE2 2 |
| #define PACKET_TYPE3 3 |
| |
| #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
| #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
| #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
| #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
| #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
| (((reg) >> 2) & 0xFFFF) | \ |
| ((n) & 0x3FFF) << 16) |
| #define CP_PACKET2 0x80000000 |
| 801,7 → 850,7 |
|---|
| |
| #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
| |
| #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
| #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
| (((op) & 0xFF) << 8) | \ |
| ((n) & 0x3FFF) << 16) |
| |