122,6 → 122,11 |
#define GUI_ACTIVE (1<<31) |
#define GRBM_STATUS2 0x8014 |
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#define CG_MULT_THERMAL_STATUS 0x740 |
#define ASIC_T(x) ((x) << 16) |
#define ASIC_T_MASK 0x3FF0000 |
#define ASIC_T_SHIFT 16 |
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#define HDP_HOST_PATH_CNTL 0x2C00 |
#define HDP_NONSURFACE_BASE 0x2C04 |
#define HDP_NONSURFACE_INFO 0x2C08 |
128,10 → 133,12 |
#define HDP_NONSURFACE_SIZE 0x2C0C |
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
#define HDP_TILING_CONFIG 0x2F3C |
#define HDP_DEBUG1 0x2F34 |
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#define MC_SHARED_CHMAP 0x2004 |
#define NOOFCHAN_SHIFT 12 |
#define NOOFCHAN_MASK 0x00003000 |
#define MC_SHARED_CHREMAP 0x2008 |
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#define MC_ARB_RAMCFG 0x2760 |
#define NOOFBANK_SHIFT 0 |
297,6 → 304,7 |
#define BILINEAR_PRECISION_8_BIT (1 << 31) |
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#define TCP_CNTL 0x9610 |
#define TCP_CHAN_STEER 0x9614 |
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#define VGT_CACHE_INVALIDATION 0x88C4 |
#define CACHE_INVALIDATION(x) ((x)<<0) |
345,4 → 353,49 |
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#define SRBM_STATUS 0x0E50 |
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#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c |
#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c |
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/* PCIE link stuff */ |
#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
# define LC_LINK_WIDTH_SHIFT 0 |
# define LC_LINK_WIDTH_MASK 0x7 |
# define LC_LINK_WIDTH_X0 0 |
# define LC_LINK_WIDTH_X1 1 |
# define LC_LINK_WIDTH_X2 2 |
# define LC_LINK_WIDTH_X4 3 |
# define LC_LINK_WIDTH_X8 4 |
# define LC_LINK_WIDTH_X16 6 |
# define LC_LINK_WIDTH_RD_SHIFT 4 |
# define LC_LINK_WIDTH_RD_MASK 0x70 |
# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) |
# define LC_RECONFIG_NOW (1 << 8) |
# define LC_RENEGOTIATION_SUPPORT (1 << 9) |
# define LC_RENEGOTIATE_EN (1 << 10) |
# define LC_SHORT_RECONFIG_EN (1 << 11) |
# define LC_UPCONFIGURE_SUPPORT (1 << 12) |
# define LC_UPCONFIGURE_DIS (1 << 13) |
#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
# define LC_GEN2_EN_STRAP (1 << 0) |
# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |
# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) |
# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) |
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) |
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 |
# define LC_CURRENT_DATA_RATE (1 << 11) |
# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) |
# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) |
# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) |
#define MM_CFGREGS_CNTL 0x544c |
# define MM_WR_TO_CFG_EN (1 << 3) |
#define LINK_CNTL2 0x88 /* F0 */ |
# define TARGET_LINK_SPEED_MASK (0xf << 0) |
# define SELECTABLE_DEEMPHASIS (1 << 6) |
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#endif |