| 239,6 → 239,7 |
|---|
| // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
| WREG32(SCRATCH_UMSK, 0); |
| rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
| } |
| |
| static int rv770_cp_load_microcode(struct radeon_device *rdev) |
| 499,6 → 500,8 |
|---|
| WREG32(GB_TILING_CONFIG, gb_tiling_config); |
| WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
| WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); |
| |
| WREG32(CGTS_SYS_TCC_DISABLE, 0); |
| WREG32(CGTS_TCC_DISABLE, 0); |
| 802,7 → 805,7 |
|---|
| |
| static int rv770_startup(struct radeon_device *rdev) |
| { |
| struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| struct radeon_ring *ring; |
| int r; |
| |
| /* enable pcie gen2 link */ |
| 849,6 → 852,18 |
|---|
| if (r) |
| return r; |
| |
| r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| return r; |
| } |
| |
| r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); |
| return r; |
| } |
| |
| /* Enable IRQ */ |
| r = r600_irq_init(rdev); |
| if (r) { |
| 858,11 → 873,20 |
|---|
| } |
| r600_irq_set(rdev); |
| |
| ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
| R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
| 0, 0xfffff, RADEON_CP_PACKET2); |
| if (r) |
| return r; |
| |
| ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
| r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, |
| DMA_RB_RPTR, DMA_RB_WPTR, |
| 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
| if (r) |
| return r; |
| |
| r = rv770_cp_load_microcode(rdev); |
| if (r) |
| return r; |
| 870,6 → 894,10 |
|---|
| if (r) |
| return r; |
| |
| r = r600_dma_resume(rdev); |
| if (r) |
| return r; |
| |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 949,6 → 977,9 |
|---|
| rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
| r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
| |
| rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
| r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
| |
| rdev->ih.ring_obj = NULL; |
| r600_ih_ring_init(rdev, 64 * 1024); |
| |