| 2050,6 → 2050,52 |
|---|
| } |
| } |
| |
| /* get the current sclk in 10 khz units */ |
| u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev) |
| { |
| struct radeon_ps *rps = rdev->pm.dpm.current_ps; |
| struct rv6xx_ps *ps = rv6xx_get_ps(rps); |
| struct rv6xx_pl *pl; |
| u32 current_index = |
| (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> |
| CURRENT_PROFILE_INDEX_SHIFT; |
| |
| if (current_index > 2) { |
| return 0; |
| } else { |
| if (current_index == 0) |
| pl = &ps->low; |
| else if (current_index == 1) |
| pl = &ps->medium; |
| else /* current_index == 2 */ |
| pl = &ps->high; |
| return pl->sclk; |
| } |
| } |
| |
| /* get the current mclk in 10 khz units */ |
| u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev) |
| { |
| struct radeon_ps *rps = rdev->pm.dpm.current_ps; |
| struct rv6xx_ps *ps = rv6xx_get_ps(rps); |
| struct rv6xx_pl *pl; |
| u32 current_index = |
| (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >> |
| CURRENT_PROFILE_INDEX_SHIFT; |
| |
| if (current_index > 2) { |
| return 0; |
| } else { |
| if (current_index == 0) |
| pl = &ps->low; |
| else if (current_index == 1) |
| pl = &ps->medium; |
| else /* current_index == 2 */ |
| pl = &ps->high; |
| return pl->mclk; |
| } |
| } |
| |
| void rv6xx_dpm_fini(struct radeon_device *rdev) |
| { |
| int i; |