| 109,7 → 109,6 |
|---|
| uint32_t size_reg; |
| uint32_t tmp; |
| |
| radeon_gart_restore(rdev); |
| tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
| tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
| WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
| 174,10 → 173,13 |
|---|
| /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
| * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
| if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
| WREG32_MC(RS480_MC_MISC_CNTL, |
| (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); |
| tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
| tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; |
| WREG32_MC(RS480_MC_MISC_CNTL, tmp); |
| } else { |
| WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
| tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
| tmp |= RS480_GART_INDEX_REG_EN; |
| WREG32_MC(RS480_MC_MISC_CNTL, tmp); |
| } |
| /* Enable gart */ |
| WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
| 206,24 → 208,26 |
|---|
| radeon_gart_table_ram_free(rdev); |
| } |
| |
| #define RS400_PTE_UNSNOOPED (1 << 0) |
| #define RS400_PTE_WRITEABLE (1 << 2) |
| #define RS400_PTE_READABLE (1 << 3) |
| |
| int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, |
| uint64_t addr, uint32_t flags) |
| { |
| uint32_t entry; |
| u32 *gtt = rdev->gart.ptr; |
| |
| if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| return -EINVAL; |
| } |
| |
| entry = (lower_32_bits(addr) & PAGE_MASK) | |
| ((upper_32_bits(addr) & 0xff) << 4) | |
| RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
| ((upper_32_bits(addr) & 0xff) << 4); |
| if (flags & RADEON_GART_PAGE_READ) |
| addr |= RS400_PTE_READABLE; |
| if (flags & RADEON_GART_PAGE_WRITE) |
| addr |= RS400_PTE_WRITEABLE; |
| if (!(flags & RADEON_GART_PAGE_SNOOP)) |
| entry |= RS400_PTE_UNSNOOPED; |
| entry = cpu_to_le32(entry); |
| gtt[i] = entry; |
| return 0; |
| } |
| |
| int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
| 271,19 → 275,26 |
|---|
| |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| unsigned long flags; |
| uint32_t r; |
| |
| spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
| WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
| r = RREG32(RS480_NB_MC_DATA); |
| WREG32(RS480_NB_MC_INDEX, 0xff); |
| spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| return r; |
| } |
| |
| void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| unsigned long flags; |
| |
| spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
| WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
| WREG32(RS480_NB_MC_DATA, (v)); |
| WREG32(RS480_NB_MC_INDEX, 0xff); |
| spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| } |
| |
| #if defined(CONFIG_DEBUG_FS) |
| 498,6 → 509,9 |
|---|
| return r; |
| r300_set_reg_safe(rdev); |
| |
| /* Initialize power management */ |
| radeon_pm_init(rdev); |
| |
| rdev->accel_working = true; |
| r = rs400_startup(rdev); |
| if (r) { |