| 28,6 → 28,7 |
|---|
| #include <linux/seq_file.h> |
| #include <drm/drmP.h> |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "rs400d.h" |
| |
| /* This files gather functions specifics to : rs400,rs480 */ |
| 53,13 → 54,7 |
|---|
| rdev->mc.gtt_size = 32 * 1024 * 1024; |
| return; |
| } |
| if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| /* FIXME: RS400 & RS480 seems to have issue with GART size |
| * if 4G of system memory (needs more testing) */ |
| rdev->mc.gtt_size = 32 * 1024 * 1024; |
| DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n"); |
| } |
| } |
| |
| void rs400_gart_tlb_flush(struct radeon_device *rdev) |
| { |
| 82,7 → 77,7 |
|---|
| int r; |
| |
| if (rdev->gart.table.ram.ptr) { |
| WARN(1, "RS400 GART already initialized.\n"); |
| WARN(1, "RS400 GART already initialized\n"); |
| return 0; |
| } |
| /* Check gart size */ |
| 202,11 → 197,14 |
|---|
| |
| void rs400_gart_fini(struct radeon_device *rdev) |
| { |
| radeon_gart_fini(rdev); |
| rs400_gart_disable(rdev); |
| radeon_gart_table_ram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| |
| #define RS400_PTE_WRITEABLE (1 << 2) |
| #define RS400_PTE_READABLE (1 << 3) |
| |
| int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| { |
| uint32_t entry; |
| 217,7 → 215,7 |
|---|
| |
| entry = (lower_32_bits(addr) & PAGE_MASK) | |
| ((upper_32_bits(addr) & 0xff) << 4) | |
| 0xc; |
| RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
| entry = cpu_to_le32(entry); |
| rdev->gart.table.ram.ptr[i] = entry; |
| return 0; |
| 230,8 → 228,8 |
|---|
| |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32(0x0150); |
| if (tmp & (1 << 2)) { |
| tmp = RREG32(RADEON_MC_STATUS); |
| if (tmp & RADEON_MC_IDLE) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| 241,13 → 239,11 |
|---|
| |
| void rs400_gpu_init(struct radeon_device *rdev) |
| { |
| /* FIXME: HDP same place on rs400 ? */ |
| r100_hdp_reset(rdev); |
| /* FIXME: is this correct ? */ |
| r420_pipes_init(rdev); |
| if (rs400_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
| "programming pipes. Bad things might happen. %08x\n", RREG32(0x150)); |
| "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
| } |
| } |
| |
| 263,7 → 259,9 |
|---|
| r100_vram_init_sizes(rdev); |
| base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
| radeon_vram_location(rdev, &rdev->mc, base); |
| rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
| radeon_gtt_location(rdev, &rdev->mc); |
| radeon_update_bandwidth_info(rdev); |
| } |
| |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| 304,9 → 302,9 |
|---|
| seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
| tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
| seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
| tmp = RREG32_MC(0x100); |
| tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); |
| seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
| tmp = RREG32(0x134); |
| tmp = RREG32(RS690_HDP_FB_LOCATION); |
| seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
| } else { |
| tmp = RREG32(RADEON_AGP_BASE); |
| 388,6 → 386,8 |
|---|
| { |
| int r; |
| |
| r100_set_common_regs(rdev); |
| |
| rs400_mc_program(rdev); |
| /* Resume clock */ |
| r300_clock_startup(rdev); |
| 405,12 → 405,9 |
|---|
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| if (r) { |
| dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| 433,6 → 430,8 |
|---|
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* restore some register to sane defaults */ |
| r100_restore_sanity(rdev); |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| 447,7 → 446,7 |
|---|
| return r; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| if (radeon_asic_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| 459,8 → 458,6 |
|---|
| |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Initialize power management */ |
| radeon_pm_init(rdev); |
| /* initialize memory controller */ |
| rs400_mc_init(rdev); |
| /* Fence driver */ |