| 223,6 → 223,22 |
|---|
| return 0; |
| } |
| |
| int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32(0x0150); |
| if (tmp & (1 << 2)) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| |
| void rs400_gpu_init(struct radeon_device *rdev) |
| { |
| /* FIXME: HDP same place on rs400 ? */ |
| 229,9 → 245,9 |
|---|
| r100_hdp_reset(rdev); |
| /* FIXME: is this correct ? */ |
| r420_pipes_init(rdev); |
| if (r300_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| if (rs400_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
| "programming pipes. Bad things might happen. %08x\n", RREG32(0x150)); |
| } |
| } |
| |
| 370,8 → 386,8 |
|---|
| r100_mc_stop(rdev, &save); |
| |
| /* Wait for mc idle */ |
| if (r300_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| if (rs400_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); |
| WREG32(R_000148_MC_FB_LOCATION, |
| S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |