| 352,7 → 352,7 |
|---|
| u32 tmp; |
| |
| /* Setup GPU memory space */ |
| tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); |
| tmp = RREG32(R_00015C_NB_TOM); |
| rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| 387,6 → 387,7 |
|---|
| r300_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| rs400_gpu_init(rdev); |
| r100_enable_bm(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = rs400_gart_enable(rdev); |
| 393,7 → 394,6 |
|---|
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // r100_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| 447,10 → 447,9 |
|---|
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| radeon_combios_asic_init(rdev->ddev); |
| } |
| if (radeon_boot_test_post_card(rdev) == false) |
| return -EINVAL; |
| |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| 467,7 → 466,7 |
|---|
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| r = radeon_bo_init(rdev); |
| if (r) |
| return r; |
| r = rs400_gart_init(rdev); |