| 49,7 → 49,7 |
|---|
| |
| int radeon_sa_bo_manager_init(struct radeon_device *rdev, |
| struct radeon_sa_manager *sa_manager, |
| unsigned size, u32 domain) |
| unsigned size, u32 align, u32 domain, u32 flags) |
| { |
| int i, r; |
| |
| 57,6 → 57,7 |
|---|
| sa_manager->bo = NULL; |
| sa_manager->size = size; |
| sa_manager->domain = domain; |
| sa_manager->align = align; |
| sa_manager->hole = &sa_manager->olist; |
| INIT_LIST_HEAD(&sa_manager->olist); |
| for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 63,8 → 64,8 |
|---|
| INIT_LIST_HEAD(&sa_manager->flist[i]); |
| } |
| |
| r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true, |
| domain, NULL, &sa_manager->bo); |
| r = radeon_bo_create(rdev, size, align, true, |
| domain, flags, NULL, &sa_manager->bo); |
| if (r) { |
| dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r); |
| return r; |
| 311,13 → 312,13 |
|---|
| int radeon_sa_bo_new(struct radeon_device *rdev, |
| struct radeon_sa_manager *sa_manager, |
| struct radeon_sa_bo **sa_bo, |
| unsigned size, unsigned align, bool block) |
| unsigned size, unsigned align) |
| { |
| struct radeon_fence *fences[RADEON_NUM_RINGS]; |
| unsigned tries[RADEON_NUM_RINGS]; |
| int i, r; |
| |
| BUG_ON(align > RADEON_GPU_PAGE_SIZE); |
| BUG_ON(align > sa_manager->align); |
| BUG_ON(size > sa_manager->size); |
| |
| *sa_bo = kmalloc(sizeof(struct radeon_sa_bo), GFP_KERNEL); |
| 352,14 → 353,11 |
|---|
| r = radeon_fence_wait_any(rdev, fences, false); |
| spin_lock(&sa_manager->wq.lock); |
| /* if we have nothing to wait for block */ |
| if (r == -ENOENT && block) { |
| // r = wait_event_interruptible_locked( |
| // sa_manager->wq, |
| // radeon_sa_event(sa_manager, size, align) |
| // ); |
| |
| } else if (r == -ENOENT) { |
| r = -ENOMEM; |
| if (r == -ENOENT) { |
| r = wait_event_interruptible( |
| sa_manager->wq, |
| radeon_sa_event(sa_manager, size, align) |
| ); |
| } |
| |
| } while (!r); |
| 401,13 → 399,15 |
|---|
| |
| spin_lock(&sa_manager->wq.lock); |
| list_for_each_entry(i, &sa_manager->olist, olist) { |
| uint64_t soffset = i->soffset + sa_manager->gpu_addr; |
| uint64_t eoffset = i->eoffset + sa_manager->gpu_addr; |
| if (&i->olist == sa_manager->hole) { |
| seq_printf(m, ">"); |
| } else { |
| seq_printf(m, " "); |
| } |
| seq_printf(m, "[0x%08x 0x%08x] size %8d", |
| i->soffset, i->eoffset, i->eoffset - i->soffset); |
| seq_printf(m, "[0x%010llx 0x%010llx] size %8lld", |
| soffset, eoffset, eoffset - soffset); |
| if (i->fence) { |
| seq_printf(m, " protected by 0x%016llx on ring %d", |
| i->fence->seq, i->fence->ring); |